| commit | a053159b83d5b00fdc911d613fd8d4ce1767fe7e | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Tue Jan 03 07:26:27 2023 -0800 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Tue Jan 03 07:26:27 2023 -0800 |
| tree | efca25e9d1f6e8e7e6fd8706173b64d4b9cb12f3 | |
| parent | a53fc7730c9f460e0b0aaf09d0d3d972a24ee310 [diff] |
update repo
This is the example-socs design P&R with 3.3V standard cells for GFMPW. pnr_socs repo contains the open source flow to regenerate this gds file.
As there is only one vdd for the whole chip, this design assumes one can run the design at a vdd somewhere between 3.3V and 5V that allows to have both the IO and harness functioning properly and not destroying the 3.3V logic gates.
