| commit | e04f17c9ac17999cd7aeae9d902359badfac7c37 | [log] [tgz] |
|---|---|---|
| author | Staf Verhaegen <staf.verhaegen@chipflow.io> | Mon Dec 05 11:13:26 2022 +0100 |
| committer | Staf Verhaegen <staf.verhaegen@chipflow.io> | Mon Dec 05 17:25:28 2022 +0100 |
| tree | d500e89ceeaee7573e34fdab1605c154a6874d8a | |
| parent | 16ca86676765ae4b93eb84b85980d32036b4de72 [diff] |
GDS file for tape-out
This is the example-socs design P&R with 3.3V standard cells for GFMPW. pnr_socs repo contains the open source flow to regenerate this gds file.
As there is only one vdd for the whole chip, this design assumes one can run the design at a vdd somewhere between 3.3V and 5V that allows to have both the IO and harness functioning properly and not destroying the 3.3V logic gates.