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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-027 / refs/heads/main
commit16d39c377d06030796a7f5194636d549ea858308[log] [tgz]
authorJeff DiCorpo <jeffdi@efabless.com>Tue Jan 03 07:26:12 2023 -0800
committerJeff DiCorpo <jeffdi@efabless.com>Tue Jan 03 07:26:12 2023 -0800
treef4b438ffb9c8b3577ca99ea357cd7dee89d5b748
parent32e735d20c7384ddd4eab7fedca66d29bf805e67 [diff]
update repo
6 files changed
tree: f4b438ffb9c8b3577ca99ea357cd7dee89d5b748
  1. .github/
  2. cocotb_tests/
  3. def/
  4. docs/
  5. gds/
  6. lef/
  7. lib/
  8. mag/
  9. maglef/
  10. openlane/
  11. sdc/
  12. sdf/
  13. signoff/
  14. spef/
  15. spi/
  16. tapeout/
  17. verilog/
  18. .gitignore
  19. gds2gltf.py
  20. LICENSE
  21. Makefile
  22. README.md
README.md

Avalon Semiconductors AS2650 8-bit micro-processor

License CI

This is a partial implementation of the abandoned Signetics 2650 CPU architecture from 1975.

Only a subset of the full feature set is implemented here. The following features are part of the S2650, but missing from the SA2650:

  • Interrupts
  • Extended I/O (wrte, rede) instructions
  • Memory paging (address space limited to 8192 bytes, emulating a S2650 that is ‘stuck’ on page 0)

Some additional funcionality is also present, utilizing opcodes that went unused in the original S2650 to add new instructions:

  • mul (opcode 'h90, no arguments) - Multiplies r0 and r1, and stores the 16-bit result in r2 (LSB) and r3 (MSB)
  • xchg (opcode 'h91, no arguments) - Exchanges the values of r0 and r1
  • strs (opcode 'h10, no arguments) - Stores the value on top of the call stack into r0 (LSB) and r1 (MSB)
  • lods (opcode `‘h11’, no arguments) - Loads the value on top of the call stack from r0 (LSB) and r1 (MSB)

Please see this repository for Documentation on the CPU architecture, as well as an assembler, emulator and example programs.