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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-027 / f6cfc320238f9b37c24ca905a006e6404c109a10
commitf6cfc320238f9b37c24ca905a006e6404c109a10[log] [tgz]
authorLuca Horn <l.horn@geiger-edelmetalle.de>Wed Dec 07 14:41:01 2022 +0100
committerLuca Horn <l.horn@geiger-edelmetalle.de>Wed Dec 07 14:41:01 2022 +0100
treeaa60dc28f8f114bb9bed65eae782a3af63cac303
parent8df3d0b4b91ed5f3b37be9923783b12fadf2dca3 [diff]
Update workflow file (5).
1 file changed
tree: aa60dc28f8f114bb9bed65eae782a3af63cac303
  1. .github/
  2. cocotb_tests/
  3. def/
  4. docs/
  5. gds/
  6. lef/
  7. lib/
  8. mag/
  9. maglef/
  10. openlane/
  11. sdc/
  12. sdf/
  13. signoff/
  14. spef/
  15. spi/
  16. verilog/
  17. .gitignore
  18. LICENSE
  19. Makefile
  20. README.md
README.md

Avalon Semiconductors AS2650 8-bit micro-processor

License UPRJ_CI Caravel Build

This is a partial implementation of the abandoned Signetics 2650 CPU architecture from 1975.

Only a subset of the full feature set is implemented here. The following features are part of the S2650, but missing from the SA2650:

  • Interrupts
  • Decimal Adjust Register (dar) instructions
  • Extended I/O (wrte, rede) instructions
  • Memory paging (address space limited to 8192 bytes, emulating a S2650 that is ‘stuck’ on page 0)

Please see this repository for Documentation on the CPU architecture, as well as an assembler, emulator and example programs.