Update workflow file (4).
diff --git a/.github/workflows/user_project_ci.yml b/.github/workflows/user_project_ci.yml
index f9a4f4d..164835f 100644
--- a/.github/workflows/user_project_ci.yml
+++ b/.github/workflows/user_project_ci.yml
@@ -102,7 +102,15 @@
export OUTPUT=$OUTPUT_DIRECTORY/logs/precheck.log
make precheck
- make run-precheck
+ docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) \
+ -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
+ -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) \
+ -e PDK_PATH=$(PDK_ROOT)/$(PDK) \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -e PDKPATH=$(PDKPATH) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+ efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)/$(PDK)"
cnt=$(grep -c "All Checks Passed" "$OUTPUT")
if ! [[ $cnt ]]; then cnt=0; fi
diff --git a/.gitignore b/.gitignore
index 1ad543c..9897e10 100644
--- a/.gitignore
+++ b/.gitignore
@@ -12,3 +12,4 @@
/deps/timing-scripts/
/venv/
/mpw_precheck/
+*.gltf
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index a53ea25..2e27c43 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -49,7 +49,8 @@
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $::env(DESIGN_DIR)/../../verilog/rtl/wrapped_as2650.v"
+ $::env(DESIGN_DIR)/../../verilog/rtl/wrapped_as2650.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/as2650.v"
set ::env(EXTRA_LEFS) "\
$::env(DESIGN_DIR)/../../lef/wrapped_as2650.lef"
