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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-027 / 46ec9dd1b1a6a1462238d720106e271deae21f7c
commit46ec9dd1b1a6a1462238d720106e271deae21f7c[log] [tgz]
authorLuca Horn <l.horn@geiger-edelmetalle.de>Thu Dec 08 15:17:35 2022 +0100
committerLuca Horn <l.horn@geiger-edelmetalle.de>Thu Dec 08 15:17:35 2022 +0100
tree6573e658dba9f20e801b0f796ee3c39996203c86
parent42ea81e561677f791e8c4ebf5682edbefd83165c [diff]
Better multithreading code in gds2gltf.
26 files changed
tree: 6573e658dba9f20e801b0f796ee3c39996203c86
  1. .github/
  2. cocotb_tests/
  3. def/
  4. docs/
  5. gds/
  6. lef/
  7. lib/
  8. mag/
  9. maglef/
  10. openlane/
  11. sdc/
  12. sdf/
  13. signoff/
  14. spef/
  15. spi/
  16. verilog/
  17. .gitignore
  18. gds2gltf.py
  19. LICENSE
  20. Makefile
  21. README.md
README.md

Avalon Semiconductors AS2650 8-bit micro-processor

License CI

This is a partial implementation of the abandoned Signetics 2650 CPU architecture from 1975.

Only a subset of the full feature set is implemented here. The following features are part of the S2650, but missing from the SA2650:

  • Interrupts
  • Extended I/O (wrte, rede) instructions
  • Memory paging (address space limited to 8192 bytes, emulating a S2650 that is ‘stuck’ on page 0)

Some additional funcionality is also present, utilizing opcodes that went unused in the original S2650 to add new instructions:

  • mul (opcode 'h90, no arguments) - Multiplies r0 and r1, and stores the 16-bit result in r2 (LSB) and r3 (MSB)
  • xchg (opcode 'h91, no arguments) - Exchanges the values of r0 and r1
  • strs (opcode 'h10, no arguments) - Stores the value on top of the call stack into r0 (LSB) and r1 (MSB)
  • lods (opcode `‘h11’, no arguments) - Loads the value on top of the call stack from r0 (LSB) and r1 (MSB)

Please see this repository for Documentation on the CPU architecture, as well as an assembler, emulator and example programs.