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# TinyTapeout project information
wokwi_id: 350175937959035475 # If using wokwi, set this to your project's ID
# source_files: # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here
# - verilog/rtl/counter.v
# - verilog/rtl/decoder.v
# top_module: "seven_segment_seconds" # put the name of your top module here, make it unique by prepending your github username
# As everyone will have access to all designs, try to make it easy for someone new to your design to know what
# it does and how to operate it.
# Here is an example:
# This info will be automatically collected and used to make a datasheet for the chip.
author: "Alexander Shabarshin" # Your name
discord: "Shaos#3571" # Your discord handle - make sure to include the # part as well
title: "TestAsyncTrimux" # Project title
description: "This is a test circuit for 3-rail async ternary selector" # Short description of what your project does
how_it_works: "Every ternary signal is represented by 3 binary - Xn, Xo, Xp (and only 1 is high)" # Longer description of how the project works
how_to_test: "Prepare data and change selection" # Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed
external_hw: "" # Describe any external hardware needed
language: "wokwi" # other examples include Verilog, Amaranth, VHDL, etc
doc_link: "" # URL to longer form documentation, eg the in your repository
clock_hz: 0 # Clock frequency in Hz (if required) we are expecting max clock frequency to be ~6khz. Provided on input 0.
picture: "wokwi-sch-async.png" # relative path to a picture in your repository
inputs: # a description of what the inputs do
- clock
- reset
- Sn
- So
- Sp
- Nn
- No
- Np
- On
- Oo
- Op
- Pn
- Po
- Pp
- T1
- T2
- Cn # segment a # a description of what the outputs do
- Co # segment b
- Cp # segment c
- OutReady # segment d
- ErrN # segment e
- ErrO # segment f
- ErrP # segment g
- ErrOut # dot
- ErrAny
- T1out
- T2out
- iclock