Step 1:  Create new cells for new GPIO default vectors.
Creating new layout file /root/project/mag/gpio_defaults_block_009.mag
Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_009.v
Layout file /root/project/mag/gpio_defaults_block_009.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_009.v already exists and does not need to be generated.
Creating new layout file /root/project/mag/gpio_defaults_block_007.mag
Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_007.v
Creating new layout file /root/project/mag/gpio_defaults_block_087.mag
Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_087.v
Layout file /root/project/mag/gpio_defaults_block_007.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_007.v already exists and does not need to be generated.
Creating new layout file /root/project/mag/gpio_defaults_block_046.mag
Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_046.v
Layout file /root/project/mag/gpio_defaults_block_046.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_046.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_046.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_046.v already exists and does not need to be generated.
Creating new layout file /root/project/mag/gpio_defaults_block_006.mag
Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v
Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
Creating new layout file /root/project/mag/gpio_defaults_block_00a.mag
Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v
Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_046.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_046.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_046.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_046.v already exists and does not need to be generated.
Step 2:  Modify top-level layouts to use the specified defaults.
Done.