final gds oasis

commit: b2c7723f77f9270e6b4059027b05613a4651f320 [log] [tgz]
author: Jeff DiCorpo <jeffdi@efabless.com> Mon Dec 12 23:48:36 2022 -0800
committer: Jeff DiCorpo <jeffdi@efabless.com> Mon Dec 12 23:48:36 2022 -0800
tree: 499b4825617756b39ecc9809c8dab96f4f76a52a
parent: c356d427af79874f974a745d18ec667a83fbbdeb [diff]
diff --git a/gds/tiny_user_project.gds b/gds/tiny_user_project.gds
deleted file mode 100644
index 0a68478..0000000
--- a/gds/tiny_user_project.gds
+++ /dev/null
Binary files differ

diff --git a/gds/tiny_user_project.gds.gz b/gds/tiny_user_project.gds.gz
new file mode 100644
index 0000000..b032747
--- /dev/null
+++ b/gds/tiny_user_project.gds.gz
Binary files differ

diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds
deleted file mode 100644
index 0eaf6ee..0000000
--- a/gds/user_project_wrapper.gds
+++ /dev/null
Binary files differ

diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
new file mode 100644
index 0000000..9895da2
--- /dev/null
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ

diff --git a/mpw_precheck/logs/gds.info b/mpw_precheck/logs/gds.info
new file mode 100644
index 0000000..1fad91d
--- /dev/null
+++ b/mpw_precheck/logs/gds.info

@@ -0,0 +1 @@
+user_project_wrapper.gds: c6954de5738af2f4c9ef9f64fdbd49d9a0dcbdad
\ No newline at end of file

diff --git a/mpw_precheck/logs/git.info b/mpw_precheck/logs/git.info
new file mode 100644
index 0000000..9ce80c6
--- /dev/null
+++ b/mpw_precheck/logs/git.info

@@ -0,0 +1,3 @@
+Repository: https://github.com/shaos/tiny_silicon_2.git
+Branch: main
+Commit: c356d427af79874f974a745d18ec667a83fbbdeb

diff --git a/mpw_precheck/logs/klayout_beol_check.log b/mpw_precheck/logs/klayout_beol_check.log
new file mode 100644
index 0000000..8458862
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.log

@@ -0,0 +1,421 @@
+2022-12-05 05:54:52 +0000: Memory Usage (543004K) : Starting running GF180MCU Klayout DRC runset on /root/testasynctrimux/gds/user_project_wrapper.gds
+2022-12-05 05:54:52 +0000: Memory Usage (543004K) : Ruby Version for klayout: 2.0.0
+2022-12-05 05:54:52 +0000: Memory Usage (553024K) : Loading database to memory is complete.
+2022-12-05 05:54:52 +0000: Memory Usage (553024K) : GF180MCU Klayout DRC runset output at: /mnt/uffs/user/u9715_ashabar/design/testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/outputs/reports/klayout_beol_check.xml
+2022-12-05 05:54:52 +0000: Memory Usage (553024K) : Number of threads to use 4
+2022-12-05 05:54:52 +0000: Memory Usage (553024K) : flat  mode is enabled.
+2022-12-05 05:54:52 +0000: Memory Usage (553024K) : Read in polygons from layers.
+2022-12-05 05:54:57 +0000: Memory Usage (656160K) : Starting deriving base layers.
+2022-12-05 05:55:00 +0000: Memory Usage (756756K) : Evaluate switches.
+2022-12-05 05:55:00 +0000: Memory Usage (756756K) : FEOL is disabled.
+2022-12-05 05:55:00 +0000: Memory Usage (756756K) : BEOL is enabled.
+2022-12-05 05:55:00 +0000: Memory Usage (756756K) : connectivity rules are enabled.
+2022-12-05 05:55:00 +0000: Memory Usage (756756K) : METAL_TOP Selected is 9K
+2022-12-05 05:55:00 +0000: Memory Usage (756756K) : METAL_STACK Selected is 5LM
+2022-12-05 05:55:00 +0000: Memory Usage (756756K) : Wedge enabled  true
+2022-12-05 05:55:00 +0000: Memory Usage (756756K) : Ball enabled  true
+2022-12-05 05:55:00 +0000: Memory Usage (756756K) : Gold enabled  true
+2022-12-05 05:55:00 +0000: Memory Usage (756756K) : MIM Option selected B
+/opt/checks/tech-files/gf180mcuC_mr.drc:543: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/gf180mcuC_mr.drc:463: warning: previous definition of OFFGRID was here
+2022-12-05 05:55:00 +0000: Memory Usage (756756K) : Offgrid enabled  true
+2022-12-05 05:55:00 +0000: Memory Usage (756756K) : Construct connectivity for the design.
+2022-12-05 05:55:03 +0000: Memory Usage (756756K) : Connectivity rules enabled, Netlist object will be generated.
+2022-12-05 05:55:08 +0000: Memory Usage (859688K) : Total area of the design is 8997120.228799999 um^2.
+2022-12-05 05:55:08 +0000: Memory Usage (859688K) : Total no. of polygons in the design is 730783
+2022-12-05 05:55:08 +0000: Memory Usage (859688K) : Initialization and base layers definition.
+2022-12-05 05:55:08 +0000: Memory Usage (859688K) : Starting GF180MCU DRC rules.
+2022-12-05 05:55:08 +0000: Memory Usage (859688K) : BEOL section
+2022-12-05 05:55:08 +0000: Memory Usage (859688K) : Executing rule M1.1
+2022-12-05 05:55:08 +0000: Memory Usage (859688K) : Executing rule M1.2a
+2022-12-05 05:55:19 +0000: Memory Usage (859688K) : Executing rule M1.2b
+2022-12-05 05:55:24 +0000: Memory Usage (859688K) : Executing rule M1.3
+2022-12-05 05:55:24 +0000: Memory Usage (859688K) : Executing rule M2.1
+2022-12-05 05:55:24 +0000: Memory Usage (859688K) : Executing rule M2.2a
+2022-12-05 05:55:24 +0000: Memory Usage (859688K) : Executing rule M2.2b
+2022-12-05 05:55:24 +0000: Memory Usage (859688K) : Executing rule M2.3
+2022-12-05 05:55:24 +0000: Memory Usage (859688K) : Executing rule M3.1
+2022-12-05 05:55:24 +0000: Memory Usage (859688K) : Executing rule M3.2a
+2022-12-05 05:55:24 +0000: Memory Usage (859688K) : Executing rule M3.2b
+2022-12-05 05:55:24 +0000: Memory Usage (859688K) : Executing rule M3.3
+2022-12-05 05:55:24 +0000: Memory Usage (859688K) : Executing rule M4.1
+2022-12-05 05:55:24 +0000: Memory Usage (859688K) : Executing rule M4.2a
+2022-12-05 05:55:24 +0000: Memory Usage (859688K) : Executing rule M4.2b
+2022-12-05 05:55:25 +0000: Memory Usage (859688K) : Executing rule M4.3
+2022-12-05 05:55:25 +0000: Memory Usage (859688K) : Executing rule M5.1
+2022-12-05 05:55:25 +0000: Memory Usage (859688K) : Executing rule M5.2a
+2022-12-05 05:55:25 +0000: Memory Usage (859688K) : Executing rule M5.2b
+2022-12-05 05:55:25 +0000: Memory Usage (859688K) : Executing rule M5.3
+2022-12-05 05:55:25 +0000: Memory Usage (859688K) : Executing rule V1.1
+2022-12-05 05:55:25 +0000: Memory Usage (859688K) : Executing rule V1.2a
+2022-12-05 05:55:25 +0000: Memory Usage (859688K) : Executing rule V1.2b
+2022-12-05 05:55:25 +0000: Memory Usage (859688K) : Executing rule V1.3a
+2022-12-05 05:55:31 +0000: Memory Usage (947640K) : Executing rule V1.3c
+2022-12-05 05:55:32 +0000: Memory Usage (947640K) : Executing rule V1.3d
+2022-12-05 05:55:33 +0000: Memory Usage (999916K) : Executing rule V1.4a
+2022-12-05 05:55:34 +0000: Memory Usage (999916K) : Executing rule V1.4b
+2022-12-05 05:55:34 +0000: Memory Usage (999916K) : Executing rule V1.4c
+2022-12-05 05:55:34 +0000: Memory Usage (999916K) : Executing rule V2.1
+2022-12-05 05:55:34 +0000: Memory Usage (999916K) : Executing rule V2.2a
+2022-12-05 05:55:34 +0000: Memory Usage (999916K) : Executing rule V2.2b
+2022-12-05 05:55:34 +0000: Memory Usage (999916K) : Executing rule V2.3b
+2022-12-05 05:55:34 +0000: Memory Usage (999916K) : Executing rule V2.3c
+2022-12-05 05:55:35 +0000: Memory Usage (999916K) : Executing rule V2.3d
+2022-12-05 05:55:35 +0000: Memory Usage (999916K) : Executing rule V2.4a
+2022-12-05 05:55:35 +0000: Memory Usage (999916K) : Executing rule V2.4b
+2022-12-05 05:55:35 +0000: Memory Usage (999916K) : Executing rule V2.4c
+2022-12-05 05:55:35 +0000: Memory Usage (999916K) : Executing rule V3.1
+2022-12-05 05:55:35 +0000: Memory Usage (999916K) : Executing rule V3.2a
+2022-12-05 05:55:36 +0000: Memory Usage (999916K) : Executing rule V3.2b
+2022-12-05 05:55:36 +0000: Memory Usage (999916K) : Executing rule V3.3b
+2022-12-05 05:55:36 +0000: Memory Usage (999916K) : Executing rule V3.3c
+2022-12-05 05:55:36 +0000: Memory Usage (999916K) : Executing rule V3.3d
+2022-12-05 05:55:36 +0000: Memory Usage (999916K) : Executing rule V3.4a
+2022-12-05 05:55:36 +0000: Memory Usage (999916K) : Executing rule V3.4b
+2022-12-05 05:55:36 +0000: Memory Usage (999916K) : Executing rule V3.4c
+2022-12-05 05:55:37 +0000: Memory Usage (999916K) : Executing rule V4.1
+2022-12-05 05:55:37 +0000: Memory Usage (999916K) : Executing rule V4.2a
+2022-12-05 05:55:38 +0000: Memory Usage (999916K) : Executing rule V4.2b
+2022-12-05 05:55:38 +0000: Memory Usage (999916K) : Executing rule V4.3b
+2022-12-05 05:55:39 +0000: Memory Usage (999916K) : Executing rule V4.3c
+2022-12-05 05:55:40 +0000: Memory Usage (999916K) : Executing rule V4.3d
+2022-12-05 05:55:40 +0000: Memory Usage (999916K) : Executing rule V4.4a
+2022-12-05 05:55:40 +0000: Memory Usage (999916K) : Executing rule V4.4b
+2022-12-05 05:55:42 +0000: Memory Usage (1004012K) : Executing rule V4.4c
+2022-12-05 05:55:42 +0000: Memory Usage (1004012K) : Executing rule V5.1
+2022-12-05 05:55:42 +0000: Memory Usage (1004012K) : Executing rule V5.2a
+2022-12-05 05:55:42 +0000: Memory Usage (1004012K) : Executing rule V5.2b
+2022-12-05 05:55:42 +0000: Memory Usage (1004012K) : Executing rule V5.3b
+2022-12-05 05:55:42 +0000: Memory Usage (1004012K) : Executing rule V5.3c
+2022-12-05 05:55:42 +0000: Memory Usage (1004012K) : Executing rule V5.3d
+2022-12-05 05:55:42 +0000: Memory Usage (1004012K) : Executing rule V5.4a
+2022-12-05 05:55:42 +0000: Memory Usage (1004012K) : Executing rule V5.4b
+2022-12-05 05:55:43 +0000: Memory Usage (1004012K) : Executing rule V5.4c
+2022-12-05 05:55:43 +0000: Memory Usage (1004012K) : MetalTop thickness 9k/11k section
+2022-12-05 05:55:43 +0000: Memory Usage (1004012K) : Executing rule MT.1
+2022-12-05 05:55:43 +0000: Memory Usage (1004012K) : Executing rule MT.2a
+2022-12-05 05:55:43 +0000: Memory Usage (1004012K) : Executing rule MT.2b
+2022-12-05 05:55:43 +0000: Memory Usage (1004012K) : Executing rule MT.4
+2022-12-05 05:55:43 +0000: Memory Usage (1004012K) : Executing rule MC.1
+2022-12-05 05:55:43 +0000: Memory Usage (1004012K) : Executing rule MC.2
+2022-12-05 05:55:43 +0000: Memory Usage (1004012K) : Executing rule MC.3
+2022-12-05 05:55:43 +0000: Memory Usage (1004012K) : Executing rule MC.4
+2022-12-05 05:55:43 +0000: Memory Usage (1014968K) : Executing rule PRES.1
+2022-12-05 05:55:43 +0000: Memory Usage (1014968K) : Executing rule PRES.2
+2022-12-05 05:55:43 +0000: Memory Usage (1014968K) : Executing rule PRES.3
+2022-12-05 05:55:43 +0000: Memory Usage (1014968K) : Executing rule PRES.4
+2022-12-05 05:55:43 +0000: Memory Usage (1014968K) : Executing rule PRES.5
+2022-12-05 05:55:44 +0000: Memory Usage (1014968K) : Executing rule PRES.6
+2022-12-05 05:55:44 +0000: Memory Usage (1014968K) : Executing rule PRES.7
+2022-12-05 05:55:44 +0000: Memory Usage (1020716K) : Executing rule PRES.9a
+2022-12-05 05:55:44 +0000: Memory Usage (1020716K) : Executing rule PRES.9b
+2022-12-05 05:55:44 +0000: Memory Usage (1023276K) : Executing rule LRES.1
+2022-12-05 05:55:44 +0000: Memory Usage (1023276K) : Executing rule LRES.2
+2022-12-05 05:55:44 +0000: Memory Usage (1023276K) : Executing rule LRES.3
+2022-12-05 05:55:44 +0000: Memory Usage (1023276K) : Executing rule LRES.4
+2022-12-05 05:55:44 +0000: Memory Usage (1023276K) : Executing rule LRES.5
+2022-12-05 05:55:45 +0000: Memory Usage (1034228K) : Executing rule LRES.6
+2022-12-05 05:55:45 +0000: Memory Usage (1034228K) : Executing rule LRES.7
+2022-12-05 05:55:45 +0000: Memory Usage (1036788K) : Executing rule LRES.9a
+2022-12-05 05:55:46 +0000: Memory Usage (1036788K) : Executing rule LRES.9b
+2022-12-05 05:55:47 +0000: Memory Usage (1051028K) : Executing rule HRES.1
+2022-12-05 05:55:47 +0000: Memory Usage (1051028K) : Executing rule HRES.2
+2022-12-05 05:55:47 +0000: Memory Usage (1051028K) : Executing rule HRES.3
+2022-12-05 05:55:47 +0000: Memory Usage (1051028K) : Executing rule HRES.4
+2022-12-05 05:55:47 +0000: Memory Usage (1051028K) : Executing rule HRES.5
+2022-12-05 05:55:47 +0000: Memory Usage (1051028K) : Executing rule HRES.6
+2022-12-05 05:55:48 +0000: Memory Usage (1063536K) : Executing rule HRES.7
+2022-12-05 05:55:48 +0000: Memory Usage (1063536K) : Executing rule HRES.8
+2022-12-05 05:55:48 +0000: Memory Usage (1063536K) : Executing rule HRES.9
+2022-12-05 05:55:48 +0000: Memory Usage (1063536K) : Executing rule HRES.10
+2022-12-05 05:55:48 +0000: Memory Usage (1067724K) : Executing rule HRES.12a
+2022-12-05 05:55:48 +0000: Memory Usage (1067724K) : Executing rule HRES.12b
+2022-12-05 05:55:48 +0000: Memory Usage (1067724K) : MIM Capacitor Option B section
+2022-12-05 05:55:48 +0000: Memory Usage (1067724K) : Executing rule MIMTM.1
+2022-12-05 05:55:48 +0000: Memory Usage (1067724K) : Executing rule MIMTM.2
+2022-12-05 05:55:48 +0000: Memory Usage (1067724K) : Executing rule MIMTM.3
+2022-12-05 05:55:49 +0000: Memory Usage (1067724K) : Executing rule MIMTM.4
+2022-12-05 05:55:49 +0000: Memory Usage (1067724K) : Executing rule MIMTM.5
+2022-12-05 05:55:49 +0000: Memory Usage (1076568K) : Executing rule MIMTM.6
+2022-12-05 05:55:49 +0000: Memory Usage (1076568K) : Executing rule MIMTM.7
+2022-12-05 05:55:49 +0000: Memory Usage (1076568K) : Executing rule MIMTM.8a
+2022-12-05 05:55:49 +0000: Memory Usage (1076568K) : Executing rule MIMTM.8b
+2022-12-05 05:55:49 +0000: Memory Usage (1076568K) : Executing rule MIMTM.9
+2022-12-05 05:55:49 +0000: Memory Usage (1076568K) : Executing rule MIMTM.10
+2022-12-05 05:55:49 +0000: Memory Usage (1076568K) : Executing rule MIMTM.11
+2022-12-05 05:55:49 +0000: Memory Usage (1076568K) : Executing rule NAT.1
+2022-12-05 05:55:49 +0000: Memory Usage (1079932K) : Executing rule NAT.2
+2022-12-05 05:55:49 +0000: Memory Usage (1079932K) : Executing rule NAT.3
+2022-12-05 05:55:49 +0000: Memory Usage (1079932K) : Executing rule NAT.4
+2022-12-05 05:55:50 +0000: Memory Usage (1083468K) : Executing rule NAT.5
+2022-12-05 05:55:51 +0000: Memory Usage (1093216K) : CONNECTIVITY_RULES section
+2022-12-05 05:55:51 +0000: Memory Usage (1093216K) : Executing rule NAT.6
+2022-12-05 05:55:52 +0000: Memory Usage (1093216K) : Executing rule NAT.7
+2022-12-05 05:55:52 +0000: Memory Usage (1093216K) : Executing rule NAT.8
+2022-12-05 05:55:52 +0000: Memory Usage (1093216K) : Executing rule NAT.9
+2022-12-05 05:55:52 +0000: Memory Usage (1093216K) : Executing rule NAT.10
+2022-12-05 05:55:52 +0000: Memory Usage (1093216K) : Executing rule NAT.11
+2022-12-05 05:55:52 +0000: Memory Usage (1093216K) : Executing rule NAT.12
+2022-12-05 05:55:52 +0000: Memory Usage (1097724K) : Executing rule BJT.1
+2022-12-05 05:55:52 +0000: Memory Usage (1097724K) : Executing rule BJT.2
+2022-12-05 05:55:52 +0000: Memory Usage (1124516K) : Executing rule BJT.3
+2022-12-05 05:55:52 +0000: Memory Usage (1124516K) : Executing rule DE.2
+2022-12-05 05:55:52 +0000: Memory Usage (1124516K) : Executing rule DE.3
+2022-12-05 05:55:52 +0000: Memory Usage (1124516K) : Executing rule DE.4
+2022-12-05 05:55:53 +0000: Memory Usage (1127288K) : Executing rule LVS_BJT.1
+2022-12-05 05:55:53 +0000: Memory Usage (1127288K) : Executing rule O.DF.3a
+2022-12-05 05:55:53 +0000: Memory Usage (1127288K) : Executing rule O.DF.6
+2022-12-05 05:55:53 +0000: Memory Usage (1127288K) : Executing rule O.DF.9
+2022-12-05 05:55:53 +0000: Memory Usage (1127288K) : Executing rule O.PL.2
+2022-12-05 05:55:54 +0000: Memory Usage (1142444K) : Executing rule O.PL.3a
+2022-12-05 05:55:56 +0000: Memory Usage (1200944K) : Executing rule O.PL.4
+2022-12-05 05:55:56 +0000: Memory Usage (1200944K) : Executing rule O.SB.2
+2022-12-05 05:55:56 +0000: Memory Usage (1200944K) : Executing rule O.SB.3
+2022-12-05 05:55:56 +0000: Memory Usage (1200944K) : Executing rule O.SB.4
+2022-12-05 05:55:56 +0000: Memory Usage (1200944K) : Executing rule O.SB.5b_3.3V
+2022-12-05 05:55:56 +0000: Memory Usage (1200944K) : Executing rule O.SB.9
+2022-12-05 05:55:56 +0000: Memory Usage (1200944K) : Executing rule O.SB.11
+2022-12-05 05:55:56 +0000: Memory Usage (1200944K) : Executing rule O.SB.13_3.3V
+2022-12-05 05:55:56 +0000: Memory Usage (1200944K) : Executing rule O.SB.13_5V
+2022-12-05 05:55:56 +0000: Memory Usage (1200944K) : Executing rule O.CO.7
+2022-12-05 05:55:59 +0000: Memory Usage (1340108K) : Executing rule O.PL.ORT
+2022-12-05 05:56:02 +0000: Memory Usage (1340108K) : Executing rule EF.01
+2022-12-05 05:56:02 +0000: Memory Usage (1340108K) : Executing rule EF.02
+2022-12-05 05:56:02 +0000: Memory Usage (1340108K) : Executing rule EF.03
+2022-12-05 05:56:03 +0000: Memory Usage (1340108K) : Executing rule EF.04a
+2022-12-05 05:56:03 +0000: Memory Usage (1340108K) : Executing rule EF.04b
+2022-12-05 05:56:03 +0000: Memory Usage (1340108K) : Executing rule EF.04c
+2022-12-05 05:56:03 +0000: Memory Usage (1340108K) : Executing rule EF.04d
+2022-12-05 05:56:03 +0000: Memory Usage (1340108K) : Executing rule EF.05
+2022-12-05 05:56:03 +0000: Memory Usage (1340108K) : Executing rule EF.06
+2022-12-05 05:56:03 +0000: Memory Usage (1340108K) : Executing rule EF.07
+2022-12-05 05:56:03 +0000: Memory Usage (1340108K) : Executing rule EF.08
+2022-12-05 05:56:03 +0000: Memory Usage (1340108K) : Executing rule EF.09
+2022-12-05 05:56:03 +0000: Memory Usage (1340108K) : Executing rule EF.10
+2022-12-05 05:56:04 +0000: Memory Usage (1340108K) : Executing rule EF.11
+2022-12-05 05:56:04 +0000: Memory Usage (1340108K) : Executing rule EF.12
+2022-12-05 05:56:04 +0000: Memory Usage (1340108K) : Executing rule EF.13
+2022-12-05 05:56:04 +0000: Memory Usage (1340108K) : Executing rule EF.14
+2022-12-05 05:56:04 +0000: Memory Usage (1340108K) : Executing rule EF.15
+2022-12-05 05:56:04 +0000: Memory Usage (1340108K) : Executing rule EF.16a
+2022-12-05 05:56:04 +0000: Memory Usage (1340108K) : Executing rule EF.16b
+2022-12-05 05:56:04 +0000: Memory Usage (1340108K) : Executing rule EF.17
+2022-12-05 05:56:04 +0000: Memory Usage (1340108K) : Executing rule EF.18
+2022-12-05 05:56:06 +0000: Memory Usage (1420720K) : Executing rule EF.19
+2022-12-05 05:56:07 +0000: Memory Usage (1420720K) : Executing rule EF.20
+2022-12-05 05:56:08 +0000: Memory Usage (1420720K) : Executing rule EF.21
+2022-12-05 05:56:08 +0000: Memory Usage (1420720K) : Executing rule EF.22a
+2022-12-05 05:56:08 +0000: Memory Usage (1420720K) : Executing rule EF.22b
+2022-12-05 05:56:08 +0000: Memory Usage (1420720K) : Executing rule MDN.1
+2022-12-05 05:56:08 +0000: Memory Usage (1420720K) : CONNECTIVITY_RULES section
+2022-12-05 05:56:08 +0000: Memory Usage (1420720K) : Executing rule MDN.2a
+2022-12-05 05:56:08 +0000: Memory Usage (1420720K) : Executing rule MDN.2b
+2022-12-05 05:56:09 +0000: Memory Usage (1420720K) : Executing rule MDN.3a
+2022-12-05 05:56:09 +0000: Memory Usage (1420720K) : Executing rule MDN.3b
+2022-12-05 05:56:09 +0000: Memory Usage (1420720K) : Executing rule MDN.4a
+2022-12-05 05:56:09 +0000: Memory Usage (1420720K) : Executing rule MDN.4b
+2022-12-05 05:56:09 +0000: Memory Usage (1420720K) : Executing rule MDN.5ai
+2022-12-05 05:56:09 +0000: Memory Usage (1420720K) : Executing rule MDN.5aii
+2022-12-05 05:56:09 +0000: Memory Usage (1420720K) : Executing rule MDN.5b
+2022-12-05 05:56:09 +0000: Memory Usage (1420720K) : Executing rule MDN.5c
+2022-12-05 05:56:10 +0000: Memory Usage (1420720K) : Executing rule MDN.6
+2022-12-05 05:56:10 +0000: Memory Usage (1420720K) : Executing rule MDN.6a
+2022-12-05 05:56:10 +0000: Memory Usage (1420720K) : Executing rule MDN.7
+2022-12-05 05:56:10 +0000: Memory Usage (1420720K) : Executing rule MDN.7a
+2022-12-05 05:56:11 +0000: Memory Usage (1420720K) : CONNECTIVITY_RULES section
+2022-12-05 05:56:11 +0000: Memory Usage (1420720K) : Executing rule MDN.8a
+2022-12-05 05:56:11 +0000: Memory Usage (1420720K) : Executing rule MDN.8b
+2022-12-05 05:56:11 +0000: Memory Usage (1420720K) : Executing rule MDN.9
+2022-12-05 05:56:11 +0000: Memory Usage (1433580K) : Executing rule MDN.10a
+2022-12-05 05:56:11 +0000: Memory Usage (1433580K) : Executing rule MDN.10b
+2022-12-05 05:56:12 +0000: Memory Usage (1433580K) : Executing rule MDN.10c
+2022-12-05 05:56:14 +0000: Memory Usage (1460580K) : Executing rule MDN.10d
+2022-12-05 05:56:14 +0000: Memory Usage (1460580K) : Executing rule MDN.10ei
+2022-12-05 05:56:15 +0000: Memory Usage (1461300K) : Executing rule MDN.10eii
+2022-12-05 05:56:15 +0000: Memory Usage (1467192K) : Executing rule MDN.10f
+2022-12-05 05:56:16 +0000: Memory Usage (1515212K) : Executing rule MDN.11
+2022-12-05 05:56:16 +0000: Memory Usage (1522116K) : Executing rule MDN.12
+2022-12-05 05:56:17 +0000: Memory Usage (1522116K) : Executing rule MDN.13a
+2022-12-05 05:56:18 +0000: Memory Usage (1525556K) : Executing rule MDN.13b
+2022-12-05 05:56:18 +0000: Memory Usage (1525556K) : Executing rule MDN.13c
+2022-12-05 05:56:19 +0000: Memory Usage (1561176K) : Executing rule MDN.13d
+2022-12-05 05:56:19 +0000: Memory Usage (1561176K) : Executing rule MDN.14
+2022-12-05 05:56:19 +0000: Memory Usage (1561176K) : Executing rule MDN.15a
+2022-12-05 05:56:19 +0000: Memory Usage (1561176K) : Executing rule MDN.15b
+2022-12-05 05:56:20 +0000: Memory Usage (1561176K) : Executing rule MDN.17
+2022-12-05 05:56:21 +0000: Memory Usage (1572792K) : Executing rule MDP.1
+2022-12-05 05:56:21 +0000: Memory Usage (1599584K) : Executing rule MDP.1a
+2022-12-05 05:57:53 +0000: Memory Usage (2191984K) : Executing rule MDP.2
+2022-12-05 05:57:54 +0000: Memory Usage (2210112K) : Executing rule MDP.3
+2022-12-05 05:57:54 +0000: Memory Usage (2210112K) : Executing rule MDP.3ai
+2022-12-05 05:57:55 +0000: Memory Usage (2210112K) : Executing rule MDP.3aii
+2022-12-05 05:57:55 +0000: Memory Usage (2210112K) : Executing rule MDP.3b
+2022-12-05 05:57:55 +0000: Memory Usage (2210112K) : Executing rule MDP.3c
+2022-12-05 05:57:55 +0000: Memory Usage (2210112K) : Executing rule MDP.3d
+2022-12-05 05:57:55 +0000: Memory Usage (2210112K) : Executing rule MDP.4
+2022-12-05 05:58:01 +0000: Memory Usage (2227144K) : Executing rule MDP.4a
+2022-12-05 05:58:01 +0000: Memory Usage (2227144K) : Executing rule MDP.4b
+2022-12-05 05:58:01 +0000: Memory Usage (2227144K) : Executing rule MDP.5
+2022-12-05 05:58:02 +0000: Memory Usage (2229200K) : Executing rule MDP.5a
+2022-12-05 05:58:02 +0000: Memory Usage (2229200K) : Executing rule MDP.6
+2022-12-05 05:58:02 +0000: Memory Usage (2229200K) : Executing rule MDP.6a
+2022-12-05 05:58:02 +0000: Memory Usage (2229200K) : Executing rule MDP.7
+2022-12-05 05:58:02 +0000: Memory Usage (2229200K) : Executing rule MDP.8
+2022-12-05 05:58:02 +0000: Memory Usage (2229200K) : Executing rule MDP.9a
+2022-12-05 05:58:02 +0000: Memory Usage (2229200K) : Executing rule MDP.9b
+2022-12-05 05:58:02 +0000: Memory Usage (2229200K) : Executing rule MDP.9c
+2022-12-05 05:58:03 +0000: Memory Usage (2268040K) : Executing rule MDP.9d
+2022-12-05 05:58:06 +0000: Memory Usage (2329448K) : Executing rule MDP.9ei
+2022-12-05 05:58:07 +0000: Memory Usage (2353788K) : Executing rule MDP.9eii
+2022-12-05 05:58:07 +0000: Memory Usage (2353788K) : Executing rule MDP.9f
+2022-12-05 05:58:08 +0000: Memory Usage (2370112K) : Executing rule MDP.10
+2022-12-05 05:58:08 +0000: Memory Usage (2370112K) : CONNECTIVITY_RULES section
+2022-12-05 05:58:08 +0000: Memory Usage (2370112K) : Executing rule MDP.10a
+2022-12-05 05:58:08 +0000: Memory Usage (2370112K) : Executing rule MDP.10b
+2022-12-05 05:58:09 +0000: Memory Usage (2370112K) : Executing rule MDP.11
+2022-12-05 05:58:09 +0000: Memory Usage (2370112K) : Executing rule MDP.12
+2022-12-05 05:58:09 +0000: Memory Usage (2389976K) : Executing rule MDP.13a
+2022-12-05 05:58:10 +0000: Memory Usage (2406316K) : Executing rule MDP.13b
+2022-12-05 05:58:10 +0000: Memory Usage (2406316K) : Executing rule MDP.13c
+2022-12-05 05:58:11 +0000: Memory Usage (2430704K) : Executing rule MDP.15
+2022-12-05 05:58:11 +0000: Memory Usage (2430704K) : Executing rule MDP.16a
+2022-12-05 05:58:11 +0000: Memory Usage (2430704K) : Executing rule MDP.16b
+2022-12-05 05:58:11 +0000: Memory Usage (2430704K) : Executing rule MDP.17a
+2022-12-05 05:58:11 +0000: Memory Usage (2430704K) : Executing rule MDP.17c
+2022-12-05 05:58:11 +0000: Memory Usage (2430704K) : Executing rule Y.NW.2b_3.3V
+2022-12-05 05:58:11 +0000: Memory Usage (2430704K) : Executing rule Y.NW.2b_5V
+2022-12-05 05:58:11 +0000: Memory Usage (2430704K) : Executing rule Y.DF.6_5V
+2022-12-05 05:58:11 +0000: Memory Usage (2430704K) : Executing rule Y.DF.16_3.3V
+2022-12-05 05:58:12 +0000: Memory Usage (2430704K) : Executing rule Y.DF.16_5V
+2022-12-05 05:58:12 +0000: Memory Usage (2430704K) : Executing rule Y.PL.1_3.3V
+2022-12-05 05:58:12 +0000: Memory Usage (2430704K) : Executing rule Y.PL.1_5V
+2022-12-05 05:58:12 +0000: Memory Usage (2430704K) : Executing rule Y.PL.2_3.3V
+2022-12-05 05:58:14 +0000: Memory Usage (2444792K) : Executing rule Y.PL.2_5V
+2022-12-05 05:58:15 +0000: Memory Usage (2461200K) : Executing rule Y.PL.4_5V
+2022-12-05 05:58:15 +0000: Memory Usage (2461200K) : Executing rule Y.PL.5a_3.3V
+2022-12-05 05:58:15 +0000: Memory Usage (2461200K) : Executing rule Y.PL.5a_5V
+2022-12-05 05:58:15 +0000: Memory Usage (2461200K) : Executing rule Y.PL.5b_3.3V
+2022-12-05 05:58:15 +0000: Memory Usage (2461200K) : Executing rule Y.PL.5b_5V
+2022-12-05 05:58:15 +0000: Memory Usage (2461200K) : Executing rule S.DF.4c_MV
+2022-12-05 05:58:16 +0000: Memory Usage (2461200K) : Executing rule S.DF.6_MV
+2022-12-05 05:58:16 +0000: Memory Usage (2461200K) : Executing rule S.DF.7_MV
+2022-12-05 05:58:16 +0000: Memory Usage (2461200K) : Executing rule S.DF.8_MV
+2022-12-05 05:58:16 +0000: Memory Usage (2461200K) : Executing rule S.DF.16_MV
+2022-12-05 05:58:16 +0000: Memory Usage (2479932K) : Executing rule S.PL.5a_MV
+2022-12-05 05:58:16 +0000: Memory Usage (2479932K) : Executing rule S.PL.5b_MV
+2022-12-05 05:58:16 +0000: Memory Usage (2479932K) : Executing rule S.CO.4_MV
+2022-12-05 05:58:16 +0000: Memory Usage (2479932K) : Executing rule S.DF.4c_LV
+2022-12-05 05:58:17 +0000: Memory Usage (2479932K) : Executing rule S.DF.16_LV
+2022-12-05 05:58:17 +0000: Memory Usage (2497244K) : Executing rule S.CO.3_LV
+2022-12-05 05:58:17 +0000: Memory Usage (2497244K) : Executing rule S.CO.4_LV
+2022-12-05 05:58:17 +0000: Memory Usage (2497244K) : Executing rule S.CO.6_ii_LV
+2022-12-05 05:58:17 +0000: Memory Usage (2497244K) : Executing rule S.M1.1_LV
+2022-12-05 05:58:17 +0000: Memory Usage (2497244K) : OFFGRID-ANGLES section
+2022-12-05 05:58:17 +0000: Memory Usage (2497244K) : Executing rule comp_OFFGRID
+2022-12-05 05:58:17 +0000: Memory Usage (2497244K) : Executing rule dnwell_OFFGRID
+2022-12-05 05:58:18 +0000: Memory Usage (2497244K) : Executing rule nwell_OFFGRID
+2022-12-05 05:58:18 +0000: Memory Usage (2497244K) : Executing rule lvpwell_OFFGRID
+2022-12-05 05:58:18 +0000: Memory Usage (2497244K) : Executing rule dualgate_OFFGRID
+2022-12-05 05:58:18 +0000: Memory Usage (2497244K) : Executing rule poly2_OFFGRID
+2022-12-05 05:58:18 +0000: Memory Usage (2497244K) : Executing rule nplus_OFFGRID
+2022-12-05 05:58:18 +0000: Memory Usage (2497244K) : Executing rule pplus_OFFGRID
+2022-12-05 05:58:18 +0000: Memory Usage (2497244K) : Executing rule sab_OFFGRID
+2022-12-05 05:58:18 +0000: Memory Usage (2497244K) : Executing rule esd_OFFGRID
+2022-12-05 05:58:18 +0000: Memory Usage (2497244K) : Executing rule contact_OFFGRID
+2022-12-05 05:58:18 +0000: Memory Usage (2497244K) : Executing rule metal1_OFFGRID
+2022-12-05 05:58:19 +0000: Memory Usage (2497244K) : Executing rule via1_OFFGRID
+2022-12-05 05:58:19 +0000: Memory Usage (2497244K) : Executing rule metal2_OFFGRID
+2022-12-05 05:58:19 +0000: Memory Usage (2497244K) : Executing rule via2_OFFGRID
+2022-12-05 05:58:19 +0000: Memory Usage (2497244K) : Executing rule metal3_OFFGRID
+2022-12-05 05:58:19 +0000: Memory Usage (2497244K) : Executing rule via3_OFFGRID
+2022-12-05 05:58:19 +0000: Memory Usage (2497244K) : Executing rule metal4_OFFGRID
+2022-12-05 05:58:19 +0000: Memory Usage (2497244K) : Executing rule via4_OFFGRID
+2022-12-05 05:58:19 +0000: Memory Usage (2497244K) : Executing rule metal5_OFFGRID
+2022-12-05 05:58:19 +0000: Memory Usage (2497244K) : Executing rule via5_OFFGRID
+2022-12-05 05:58:19 +0000: Memory Usage (2497244K) : Executing rule metaltop_OFFGRID
+2022-12-05 05:58:19 +0000: Memory Usage (2497244K) : Executing rule pad_OFFGRID
+2022-12-05 05:58:19 +0000: Memory Usage (2497244K) : Executing rule resistor_OFFGRID
+2022-12-05 05:58:19 +0000: Memory Usage (2497244K) : Executing rule fhres_OFFGRID
+2022-12-05 05:58:20 +0000: Memory Usage (2497244K) : Executing rule fusetop_OFFGRID
+2022-12-05 05:58:20 +0000: Memory Usage (2497244K) : Executing rule fusewindow_d_OFFGRID
+2022-12-05 05:58:20 +0000: Memory Usage (2497244K) : Executing rule polyfuse_OFFGRID
+2022-12-05 05:58:20 +0000: Memory Usage (2497244K) : Executing rule mvsd_OFFGRID
+2022-12-05 05:58:20 +0000: Memory Usage (2497244K) : Executing rule mvpsd_OFFGRID
+2022-12-05 05:58:20 +0000: Memory Usage (2497244K) : Executing rule nat_OFFGRID
+2022-12-05 05:58:20 +0000: Memory Usage (2497244K) : Executing rule comp_dummy_OFFGRID
+2022-12-05 05:58:20 +0000: Memory Usage (2497244K) : Executing rule poly2_dummy_OFFGRID
+2022-12-05 05:58:20 +0000: Memory Usage (2497244K) : Executing rule metal1_dummy_OFFGRID
+2022-12-05 05:58:20 +0000: Memory Usage (2497244K) : Executing rule metal2_dummy_OFFGRID
+2022-12-05 05:58:20 +0000: Memory Usage (2497244K) : Executing rule metal3_dummy_OFFGRID
+2022-12-05 05:58:20 +0000: Memory Usage (2497244K) : Executing rule metal4_dummy_OFFGRID
+2022-12-05 05:58:20 +0000: Memory Usage (2497244K) : Executing rule metal5_dummy_OFFGRID
+2022-12-05 05:58:20 +0000: Memory Usage (2497244K) : Executing rule metaltop_dummy_OFFGRID
+2022-12-05 05:58:21 +0000: Memory Usage (2497244K) : Executing rule comp_label_OFFGRID
+2022-12-05 05:58:21 +0000: Memory Usage (2497244K) : Executing rule poly2_label_OFFGRID
+2022-12-05 05:58:21 +0000: Memory Usage (2497244K) : Executing rule metal1_label_OFFGRID
+2022-12-05 05:58:21 +0000: Memory Usage (2497244K) : Executing rule metal2_label_OFFGRID
+2022-12-05 05:58:21 +0000: Memory Usage (2497244K) : Executing rule metal3_label_OFFGRID
+2022-12-05 05:58:21 +0000: Memory Usage (2497244K) : Executing rule metal4_label_OFFGRID
+2022-12-05 05:58:21 +0000: Memory Usage (2497244K) : Executing rule metal5_label_OFFGRID
+2022-12-05 05:58:21 +0000: Memory Usage (2497244K) : Executing rule metaltop_label_OFFGRID
+2022-12-05 05:58:21 +0000: Memory Usage (2497244K) : Executing rule metal1_slot_OFFGRID
+2022-12-05 05:58:21 +0000: Memory Usage (2497244K) : Executing rule metal2_slot_OFFGRID
+2022-12-05 05:58:21 +0000: Memory Usage (2497244K) : Executing rule metal3_slot_OFFGRID
+2022-12-05 05:58:21 +0000: Memory Usage (2497244K) : Executing rule metal4_slot_OFFGRID
+2022-12-05 05:58:21 +0000: Memory Usage (2497244K) : Executing rule metal5_slot_OFFGRID
+2022-12-05 05:58:22 +0000: Memory Usage (2497244K) : Executing rule metaltop_slot_OFFGRID
+2022-12-05 05:58:22 +0000: Memory Usage (2497244K) : Executing rule ubmpperi_OFFGRID
+2022-12-05 05:58:22 +0000: Memory Usage (2497244K) : Executing rule ubmparray_OFFGRID
+2022-12-05 05:58:22 +0000: Memory Usage (2497244K) : Executing rule ubmeplate_OFFGRID
+2022-12-05 05:58:22 +0000: Memory Usage (2497244K) : Executing rule schottky_diode_OFFGRID
+2022-12-05 05:58:22 +0000: Memory Usage (2497244K) : Executing rule zener_OFFGRID
+2022-12-05 05:58:22 +0000: Memory Usage (2497244K) : Executing rule res_mk_OFFGRID
+2022-12-05 05:58:22 +0000: Memory Usage (2497244K) : Executing rule opc_drc_OFFGRID
+2022-12-05 05:58:22 +0000: Memory Usage (2497244K) : Executing rule ndmy_OFFGRID
+2022-12-05 05:58:22 +0000: Memory Usage (2497244K) : Executing rule pmndmy_OFFGRID
+2022-12-05 05:58:22 +0000: Memory Usage (2497244K) : Executing rule v5_xtor_OFFGRID
+2022-12-05 05:58:22 +0000: Memory Usage (2497244K) : Executing rule cap_mk_OFFGRID
+2022-12-05 05:58:22 +0000: Memory Usage (2497244K) : Executing rule mos_cap_mk_OFFGRID
+2022-12-05 05:58:22 +0000: Memory Usage (2497244K) : Executing rule ind_mk_OFFGRID
+2022-12-05 05:58:23 +0000: Memory Usage (2497244K) : Executing rule diode_mk_OFFGRID
+2022-12-05 05:58:23 +0000: Memory Usage (2497244K) : Executing rule drc_bjt_OFFGRID
+2022-12-05 05:58:23 +0000: Memory Usage (2497244K) : Executing rule lvs_bjt_OFFGRID
+2022-12-05 05:58:23 +0000: Memory Usage (2497244K) : Executing rule mim_l_mk_OFFGRID
+2022-12-05 05:58:23 +0000: Memory Usage (2497244K) : Executing rule latchup_mk_OFFGRID
+2022-12-05 05:58:23 +0000: Memory Usage (2497244K) : Executing rule guard_ring_mk_OFFGRID
+2022-12-05 05:58:23 +0000: Memory Usage (2497244K) : Executing rule otp_mk_OFFGRID
+2022-12-05 05:58:23 +0000: Memory Usage (2497244K) : Executing rule mtpmark_OFFGRID
+2022-12-05 05:58:23 +0000: Memory Usage (2497244K) : Executing rule neo_ee_mk_OFFGRID
+2022-12-05 05:58:23 +0000: Memory Usage (2497244K) : Executing rule sramcore_OFFGRID
+2022-12-05 05:58:23 +0000: Memory Usage (2497244K) : Executing rule lvs_rf_OFFGRID
+2022-12-05 05:58:23 +0000: Memory Usage (2497244K) : Executing rule lvs_drain_OFFGRID
+2022-12-05 05:58:23 +0000: Memory Usage (2497244K) : Executing rule hvpolyrs_OFFGRID
+2022-12-05 05:58:24 +0000: Memory Usage (2497244K) : Executing rule lvs_io_OFFGRID
+2022-12-05 05:58:24 +0000: Memory Usage (2497244K) : Executing rule probe_mk_OFFGRID
+2022-12-05 05:58:24 +0000: Memory Usage (2497244K) : Executing rule esd_mk_OFFGRID
+2022-12-05 05:58:24 +0000: Memory Usage (2497244K) : Executing rule lvs_source_OFFGRID
+2022-12-05 05:58:24 +0000: Memory Usage (2497244K) : Executing rule well_diode_mk_OFFGRID
+2022-12-05 05:58:24 +0000: Memory Usage (2497244K) : Executing rule ldmos_xtor_OFFGRID
+2022-12-05 05:58:24 +0000: Memory Usage (2497244K) : Executing rule plfuse_OFFGRID
+2022-12-05 05:58:24 +0000: Memory Usage (2497244K) : Executing rule efuse_mk_OFFGRID
+2022-12-05 05:58:24 +0000: Memory Usage (2497244K) : Executing rule mcell_feol_mk_OFFGRID
+2022-12-05 05:58:24 +0000: Memory Usage (2497244K) : Executing rule ymtp_mk_OFFGRID
+2022-12-05 05:58:24 +0000: Memory Usage (2497244K) : Executing rule dev_wf_mk_OFFGRID
+2022-12-05 05:58:24 +0000: Memory Usage (2497244K) : Executing rule metal1_blk_OFFGRID
+2022-12-05 05:58:24 +0000: Memory Usage (2497244K) : Executing rule metal2_blk_OFFGRID
+2022-12-05 05:58:25 +0000: Memory Usage (2497244K) : Executing rule metal3_blk_OFFGRID
+2022-12-05 05:58:25 +0000: Memory Usage (2497244K) : Executing rule metal4_blk_OFFGRID
+2022-12-05 05:58:25 +0000: Memory Usage (2497244K) : Executing rule metal5_blk_OFFGRID
+2022-12-05 05:58:25 +0000: Memory Usage (2497244K) : Executing rule metalt_blk_OFFGRID
+2022-12-05 05:58:25 +0000: Memory Usage (2497244K) : Executing rule pr_bndry_OFFGRID
+2022-12-05 05:58:25 +0000: Memory Usage (2497244K) : Executing rule mdiode_OFFGRID
+2022-12-05 05:58:25 +0000: Memory Usage (2497244K) : Executing rule metal1_res_OFFGRID
+2022-12-05 05:58:25 +0000: Memory Usage (2497244K) : Executing rule metal2_res_OFFGRID
+2022-12-05 05:58:25 +0000: Memory Usage (2497244K) : Executing rule metal3_res_OFFGRID
+2022-12-05 05:58:25 +0000: Memory Usage (2497244K) : Executing rule metal4_res_OFFGRID
+2022-12-05 05:58:25 +0000: Memory Usage (2497244K) : Executing rule metal5_res_OFFGRID
+2022-12-05 05:58:25 +0000: Memory Usage (2497244K) : Executing rule metal6_res_OFFGRID
+2022-12-05 05:58:25 +0000: Memory Usage (2497244K) : Executing rule border_OFFGRID
+VmPeak:	 2497240 kB
+VmHWM:	 2031756 kB
+2022-12-05 05:58:25 +0000: Memory Usage (2497244K) : DRC Total Run time 213.160096 seconds

diff --git a/mpw_precheck/logs/klayout_beol_check.total b/mpw_precheck/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.total

@@ -0,0 +1 @@
+0
\ No newline at end of file

diff --git a/mpw_precheck/logs/klayout_feol_check.log b/mpw_precheck/logs/klayout_feol_check.log
new file mode 100644
index 0000000..85f9013
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.log

@@ -0,0 +1,563 @@
+2022-12-05 05:47:03 +0000: Memory Usage (543004K) : Starting running GF180MCU Klayout DRC runset on /root/testasynctrimux/gds/user_project_wrapper.gds
+2022-12-05 05:47:03 +0000: Memory Usage (543004K) : Ruby Version for klayout: 2.0.0
+2022-12-05 05:47:04 +0000: Memory Usage (553020K) : Loading database to memory is complete.
+2022-12-05 05:47:04 +0000: Memory Usage (553020K) : GF180MCU Klayout DRC runset output at: /mnt/uffs/user/u9715_ashabar/design/testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/outputs/reports/klayout_feol_check.xml
+2022-12-05 05:47:04 +0000: Memory Usage (553020K) : Number of threads to use 4
+2022-12-05 05:47:04 +0000: Memory Usage (553020K) : flat  mode is enabled.
+2022-12-05 05:47:04 +0000: Memory Usage (553020K) : Read in polygons from layers.
+2022-12-05 05:47:08 +0000: Memory Usage (656152K) : Starting deriving base layers.
+2022-12-05 05:47:11 +0000: Memory Usage (756752K) : Evaluate switches.
+2022-12-05 05:47:11 +0000: Memory Usage (756752K) : FEOL is enabled.
+2022-12-05 05:47:11 +0000: Memory Usage (756752K) : BEOL is disabled.
+2022-12-05 05:47:11 +0000: Memory Usage (756752K) : connectivity rules are enabled.
+2022-12-05 05:47:11 +0000: Memory Usage (756752K) : METAL_TOP Selected is 9K
+2022-12-05 05:47:11 +0000: Memory Usage (756752K) : METAL_STACK Selected is 5LM
+2022-12-05 05:47:11 +0000: Memory Usage (756752K) : Wedge enabled  true
+2022-12-05 05:47:11 +0000: Memory Usage (756752K) : Ball enabled  true
+2022-12-05 05:47:11 +0000: Memory Usage (756752K) : Gold enabled  true
+2022-12-05 05:47:11 +0000: Memory Usage (756752K) : MIM Option selected B
+/opt/checks/tech-files/gf180mcuC_mr.drc:543: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/gf180mcuC_mr.drc:463: warning: previous definition of OFFGRID was here
+2022-12-05 05:47:11 +0000: Memory Usage (756752K) : Offgrid enabled  true
+2022-12-05 05:47:11 +0000: Memory Usage (756752K) : Construct connectivity for the design.
+2022-12-05 05:47:14 +0000: Memory Usage (756752K) : Connectivity rules enabled, Netlist object will be generated.
+2022-12-05 05:47:19 +0000: Memory Usage (859692K) : Total area of the design is 8997120.228799999 um^2.
+2022-12-05 05:47:19 +0000: Memory Usage (859692K) : Total no. of polygons in the design is 730783
+2022-12-05 05:47:19 +0000: Memory Usage (859692K) : Initialization and base layers definition.
+2022-12-05 05:47:19 +0000: Memory Usage (859692K) : Starting GF180MCU DRC rules.
+2022-12-05 05:47:19 +0000: Memory Usage (859692K) : FEOL section
+2022-12-05 05:47:19 +0000: Memory Usage (859692K) : Executing rule DN.1
+2022-12-05 05:47:19 +0000: Memory Usage (859692K) : CONNECTIVITY_RULES section
+2022-12-05 05:47:19 +0000: Memory Usage (859692K) : Executing rule DN.2a
+2022-12-05 05:47:19 +0000: Memory Usage (859692K) : Executing rule DN.2b
+2022-12-05 05:47:19 +0000: Memory Usage (859692K) : Executing rule DN.3
+2022-12-05 05:47:19 +0000: Memory Usage (859692K) : Executing rule LPW.1_3.3V
+2022-12-05 05:47:20 +0000: Memory Usage (859692K) : Executing rule LPW.1_5V
+2022-12-05 05:47:20 +0000: Memory Usage (859692K) : CONNECTIVITY_RULES section
+2022-12-05 05:47:20 +0000: Memory Usage (859692K) : Executing rule LPW.2a_3.3V
+2022-12-05 05:47:20 +0000: Memory Usage (859692K) : Executing rule LPW.2a_5V
+2022-12-05 05:47:20 +0000: Memory Usage (859692K) : Executing rule LPW.2b_3.3V
+2022-12-05 05:47:20 +0000: Memory Usage (859692K) : Executing rule LPW.2b_5V
+2022-12-05 05:47:20 +0000: Memory Usage (859692K) : Executing rule LPW.3_3.3V
+2022-12-05 05:47:20 +0000: Memory Usage (859692K) : Executing rule LPW.3_5V
+2022-12-05 05:47:20 +0000: Memory Usage (859692K) : Executing rule LPW.5_3.3V
+2022-12-05 05:47:20 +0000: Memory Usage (859692K) : Executing rule LPW.5_5V
+2022-12-05 05:47:20 +0000: Memory Usage (859692K) : Executing rule LPW.11
+2022-12-05 05:47:20 +0000: Memory Usage (859692K) : Executing rule LPW.12
+2022-12-05 05:47:20 +0000: Memory Usage (859692K) : Executing rule NW.1a_3.3V
+2022-12-05 05:47:20 +0000: Memory Usage (859692K) : Executing rule NW.1a_5V
+2022-12-05 05:47:20 +0000: Memory Usage (859692K) : Executing rule NW.1b_3.3V
+2022-12-05 05:47:20 +0000: Memory Usage (859692K) : Executing rule NW.1b_5V
+2022-12-05 05:47:20 +0000: Memory Usage (859692K) : CONNECTIVITY_RULES section
+2022-12-05 05:47:20 +0000: Memory Usage (859692K) : Executing rule NW.2a_3.3V
+2022-12-05 05:47:21 +0000: Memory Usage (859692K) : Executing rule NW.2a_5V
+2022-12-05 05:47:21 +0000: Memory Usage (859692K) : Executing rule NW.2b_3.3V
+2022-12-05 05:47:21 +0000: Memory Usage (859692K) : Executing rule NW.2b_5V
+2022-12-05 05:47:21 +0000: Memory Usage (859692K) : Executing rule NW.3_3.3V
+2022-12-05 05:47:21 +0000: Memory Usage (859692K) : Executing rule NW.3_5V
+2022-12-05 05:47:21 +0000: Memory Usage (859692K) : Executing rule NW.4_3.3V
+2022-12-05 05:47:21 +0000: Memory Usage (859692K) : Executing rule NW.4_5V
+2022-12-05 05:47:21 +0000: Memory Usage (859692K) : Executing rule NW.5_3.3V
+2022-12-05 05:47:21 +0000: Memory Usage (859692K) : Executing rule NW.5_5V
+2022-12-05 05:47:21 +0000: Memory Usage (859692K) : Executing rule NW.6
+2022-12-05 05:47:21 +0000: Memory Usage (859692K) : Executing rule DF.1a_3.3V
+2022-12-05 05:47:21 +0000: Memory Usage (859692K) : Executing rule DF.1a_5V
+2022-12-05 05:47:21 +0000: Memory Usage (859692K) : Executing rule DF.1c_3.3V
+2022-12-05 05:47:21 +0000: Memory Usage (859692K) : Executing rule DF.1c_5V
+2022-12-05 05:47:25 +0000: Memory Usage (859692K) : Executing rule DF.2a_3.3V
+2022-12-05 05:47:25 +0000: Memory Usage (859692K) : Executing rule DF.2a_5V
+2022-12-05 05:47:26 +0000: Memory Usage (859692K) : Executing rule DF.2b_3.3V
+2022-12-05 05:47:27 +0000: Memory Usage (913672K) : Executing rule DF.2b_5V
+2022-12-05 05:47:28 +0000: Memory Usage (922440K) : Executing rule DF.3a_3.3V
+2022-12-05 05:47:28 +0000: Memory Usage (922440K) : Executing rule DF.3a_5V
+2022-12-05 05:47:30 +0000: Memory Usage (922440K) : Executing rule DF.3b_3.3V
+2022-12-05 05:47:30 +0000: Memory Usage (922440K) : Executing rule DF.3b_5V
+2022-12-05 05:47:30 +0000: Memory Usage (922440K) : Executing rule DF.3c_3.3V
+2022-12-05 05:47:30 +0000: Memory Usage (922440K) : Executing rule DF.3c_5V
+2022-12-05 05:47:31 +0000: Memory Usage (922440K) : Executing rule DF.4a_3.3V
+2022-12-05 05:47:31 +0000: Memory Usage (922440K) : Executing rule DF.4a_5V
+2022-12-05 05:47:31 +0000: Memory Usage (922440K) : Executing rule DF.4b_3.3V
+2022-12-05 05:47:31 +0000: Memory Usage (922440K) : Executing rule DF.4b_5V
+2022-12-05 05:47:32 +0000: Memory Usage (922440K) : Executing rule DF.4c_3.3V
+2022-12-05 05:47:33 +0000: Memory Usage (922440K) : Executing rule DF.4c_5V
+2022-12-05 05:47:34 +0000: Memory Usage (922440K) : Executing rule DF.4d_3.3V
+2022-12-05 05:47:34 +0000: Memory Usage (922440K) : Executing rule DF.4d_5V
+2022-12-05 05:47:34 +0000: Memory Usage (922440K) : Executing rule DF.4e_3.3V
+2022-12-05 05:47:34 +0000: Memory Usage (922440K) : Executing rule DF.4e_5V
+2022-12-05 05:47:34 +0000: Memory Usage (922440K) : Executing rule DF.5_3.3V
+2022-12-05 05:47:35 +0000: Memory Usage (930408K) : Executing rule DF.5_5V
+2022-12-05 05:47:35 +0000: Memory Usage (930972K) : Executing rule DF.6_3.3V
+2022-12-05 05:47:35 +0000: Memory Usage (949084K) : Executing rule DF.6_5V
+2022-12-05 05:47:36 +0000: Memory Usage (993172K) : Executing rule DF.7_3.3V
+2022-12-05 05:47:36 +0000: Memory Usage (993172K) : Executing rule DF.7_5V
+2022-12-05 05:47:36 +0000: Memory Usage (993172K) : Executing rule DF.8_3.3V
+2022-12-05 05:47:36 +0000: Memory Usage (993172K) : Executing rule DF.8_5V
+2022-12-05 05:47:36 +0000: Memory Usage (993172K) : Executing rule DF.9_3.3V
+2022-12-05 05:47:36 +0000: Memory Usage (993172K) : Executing rule DF.9_5V
+2022-12-05 05:47:36 +0000: Memory Usage (993172K) : Executing rule DF.10_3.3V
+2022-12-05 05:47:37 +0000: Memory Usage (993172K) : Executing rule DF.10_5V
+2022-12-05 05:47:37 +0000: Memory Usage (993172K) : Executing rule DF.11_3.3V
+2022-12-05 05:47:37 +0000: Memory Usage (993172K) : Executing rule DF.11_5V
+2022-12-05 05:47:37 +0000: Memory Usage (993172K) : Executing rule DF.12_3.3V
+2022-12-05 05:47:37 +0000: Memory Usage (1042620K) : Executing rule DF.12_5V
+2022-12-05 05:47:38 +0000: Memory Usage (1051532K) : Executing rule DF.13_3.3V
+2022-12-05 05:47:44 +0000: Memory Usage (1019540K) : Executing rule DF.13_5V
+2022-12-05 05:47:47 +0000: Memory Usage (1021052K) : Executing rule DF.14_3.3V
+2022-12-05 05:47:53 +0000: Memory Usage (1029648K) : Executing rule DF.14_5V
+2022-12-05 05:47:57 +0000: Memory Usage (1050884K) : Executing rule DF.16_3.3V
+2022-12-05 05:47:57 +0000: Memory Usage (1050884K) : Executing rule DF.16_5V
+2022-12-05 05:47:57 +0000: Memory Usage (1065992K) : Executing rule DF.17_3.3V
+2022-12-05 05:47:57 +0000: Memory Usage (1065992K) : Executing rule DF.17_5V
+2022-12-05 05:47:57 +0000: Memory Usage (1065992K) : Executing rule DF.18_3.3V
+2022-12-05 05:47:57 +0000: Memory Usage (1065992K) : Executing rule DF.18_5V
+2022-12-05 05:47:58 +0000: Memory Usage (1065992K) : Executing rule DF.19_3.3V
+2022-12-05 05:47:58 +0000: Memory Usage (1065992K) : Executing rule DF.19_5V
+2022-12-05 05:47:58 +0000: Memory Usage (1065992K) : Executing rule DV.1
+2022-12-05 05:47:58 +0000: Memory Usage (1065992K) : Executing rule DV.2
+2022-12-05 05:47:58 +0000: Memory Usage (1065992K) : Executing rule DV.3
+2022-12-05 05:47:58 +0000: Memory Usage (1093884K) : Executing rule DV.5
+2022-12-05 05:47:59 +0000: Memory Usage (1093884K) : Executing rule DV.6
+2022-12-05 05:48:00 +0000: Memory Usage (1103916K) : Executing rule DV.7
+2022-12-05 05:48:01 +0000: Memory Usage (1113944K) : Executing rule DV.8
+2022-12-05 05:48:02 +0000: Memory Usage (1113944K) : Executing rule DV.9
+2022-12-05 05:48:03 +0000: Memory Usage (1113944K) : Executing rule PL.1_3.3V
+2022-12-05 05:48:03 +0000: Memory Usage (1113944K) : Executing rule PL.1_5V
+2022-12-05 05:48:03 +0000: Memory Usage (1113944K) : Executing rule PL.1a_3.3V
+2022-12-05 05:48:03 +0000: Memory Usage (1113944K) : Executing rule PL.1a_5V
+2022-12-05 05:48:03 +0000: Memory Usage (1113944K) : Executing rule PL.2_3.3V
+2022-12-05 05:48:16 +0000: Memory Usage (1291100K) : Executing rule PL.2_5V
+2022-12-05 05:48:16 +0000: Memory Usage (1291100K) : Executing rule PL.3a_3.3V
+2022-12-05 05:48:18 +0000: Memory Usage (1339784K) : Executing rule PL.3a_5V
+2022-12-05 05:48:20 +0000: Memory Usage (1378724K) : Executing rule PL.4_3.3V
+2022-12-05 05:48:20 +0000: Memory Usage (1422928K) : Executing rule PL.4_5V
+2022-12-05 05:48:21 +0000: Memory Usage (1431732K) : Executing rule PL.5a_3.3V
+2022-12-05 05:48:21 +0000: Memory Usage (1431732K) : Executing rule PL.5a_5V
+2022-12-05 05:48:22 +0000: Memory Usage (1440036K) : Executing rule PL.5b_3.3V
+2022-12-05 05:48:22 +0000: Memory Usage (1440036K) : Executing rule PL.5b_5V
+2022-12-05 05:48:26 +0000: Memory Usage (1569808K) : Executing rule PL.6
+2022-12-05 05:48:31 +0000: Memory Usage (1753720K) : Executing rule PL.7_3.3V
+2022-12-05 05:48:31 +0000: Memory Usage (1753720K) : Executing rule PL.7_5V
+2022-12-05 05:48:31 +0000: Memory Usage (1753720K) : Executing rule PL.9
+2022-12-05 05:48:32 +0000: Memory Usage (1763976K) : Executing rule PL.11
+2022-12-05 05:48:32 +0000: Memory Usage (1763976K) : Executing rule PL.12
+2022-12-05 05:48:33 +0000: Memory Usage (1810392K) : Executing rule NP.1
+2022-12-05 05:48:33 +0000: Memory Usage (1810392K) : Executing rule NP.2
+2022-12-05 05:48:33 +0000: Memory Usage (1810392K) : Executing rule NP.3a
+2022-12-05 05:48:34 +0000: Memory Usage (1810392K) : Executing rule NP.3bi
+2022-12-05 05:48:34 +0000: Memory Usage (1810392K) : Executing rule NP.3bii
+2022-12-05 05:48:34 +0000: Memory Usage (1810392K) : Executing rule NP.3ci
+2022-12-05 05:48:35 +0000: Memory Usage (1810392K) : Executing rule NP.3cii
+2022-12-05 05:48:35 +0000: Memory Usage (1810392K) : Executing rule NP.3d
+2022-12-05 05:48:35 +0000: Memory Usage (1811840K) : Executing rule NP.3e
+2022-12-05 05:48:35 +0000: Memory Usage (1811840K) : Executing rule NP.4a
+2022-12-05 05:48:38 +0000: Memory Usage (1864260K) : Executing rule NP.4b
+2022-12-05 05:48:38 +0000: Memory Usage (1864260K) : Executing rule NP.5a
+2022-12-05 05:48:39 +0000: Memory Usage (1864260K) : Executing rule NP.5b
+2022-12-05 05:48:40 +0000: Memory Usage (1875060K) : Executing rule NP.5ci
+2022-12-05 05:48:41 +0000: Memory Usage (1875060K) : Executing rule NP.5cii
+2022-12-05 05:48:41 +0000: Memory Usage (1875060K) : Executing rule NP.5di
+2022-12-05 05:48:41 +0000: Memory Usage (1875060K) : Executing rule NP.5dii
+2022-12-05 05:48:41 +0000: Memory Usage (1875060K) : Executing rule NP.6
+2022-12-05 05:48:44 +0000: Memory Usage (1901524K) : Executing rule NP.7
+2022-12-05 05:48:44 +0000: Memory Usage (1901524K) : Executing rule NP.8a
+2022-12-05 05:48:44 +0000: Memory Usage (1901524K) : Executing rule NP.8b
+2022-12-05 05:48:44 +0000: Memory Usage (1901524K) : Executing rule NP.9
+2022-12-05 05:48:44 +0000: Memory Usage (1901524K) : Executing rule NP.10
+2022-12-05 05:48:45 +0000: Memory Usage (1901524K) : Executing rule NP.11
+2022-12-05 05:48:45 +0000: Memory Usage (1901524K) : Executing rule NP.12
+2022-12-05 05:48:46 +0000: Memory Usage (1901524K) : Executing rule PP.1
+2022-12-05 05:48:46 +0000: Memory Usage (1901524K) : Executing rule PP.2
+2022-12-05 05:48:46 +0000: Memory Usage (1901524K) : Executing rule PP.3a
+2022-12-05 05:48:47 +0000: Memory Usage (1906196K) : Executing rule PP.3bi
+2022-12-05 05:48:50 +0000: Memory Usage (1906196K) : Executing rule PP.3bii
+2022-12-05 05:48:50 +0000: Memory Usage (1913012K) : Executing rule PP.3ci
+2022-12-05 05:48:50 +0000: Memory Usage (1915748K) : Executing rule PP.3cii
+2022-12-05 05:48:51 +0000: Memory Usage (1915748K) : Executing rule PP.3d
+2022-12-05 05:48:51 +0000: Memory Usage (1915748K) : Executing rule PP.3e
+2022-12-05 05:48:51 +0000: Memory Usage (1915748K) : Executing rule PP.4a
+2022-12-05 05:48:53 +0000: Memory Usage (1982872K) : Executing rule PP.4b
+2022-12-05 05:48:53 +0000: Memory Usage (1982872K) : Executing rule PP.5a
+2022-12-05 05:48:54 +0000: Memory Usage (1982872K) : Executing rule PP.5b
+2022-12-05 05:48:55 +0000: Memory Usage (1985200K) : Executing rule PP.5ci
+2022-12-05 05:48:58 +0000: Memory Usage (1985200K) : Executing rule PP.5cii
+2022-12-05 05:48:59 +0000: Memory Usage (1993392K) : Executing rule PP.5di
+2022-12-05 05:49:02 +0000: Memory Usage (2003632K) : Executing rule PP.5dii
+2022-12-05 05:49:06 +0000: Memory Usage (2003632K) : Executing rule PP.6
+2022-12-05 05:49:07 +0000: Memory Usage (2014412K) : Executing rule PP.7
+2022-12-05 05:49:07 +0000: Memory Usage (2014412K) : Executing rule PP.8a
+2022-12-05 05:49:07 +0000: Memory Usage (2014412K) : Executing rule PP.8b
+2022-12-05 05:49:07 +0000: Memory Usage (2014412K) : Executing rule PP.9
+2022-12-05 05:49:07 +0000: Memory Usage (2014412K) : Executing rule PP.10
+2022-12-05 05:49:08 +0000: Memory Usage (2016068K) : Executing rule PP.11
+2022-12-05 05:49:11 +0000: Memory Usage (2016068K) : Executing rule PP.12
+2022-12-05 05:49:12 +0000: Memory Usage (2027180K) : Executing rule SB.1
+2022-12-05 05:49:15 +0000: Memory Usage (2027180K) : Executing rule SB.2
+2022-12-05 05:49:15 +0000: Memory Usage (2027180K) : Executing rule SB.3
+2022-12-05 05:49:15 +0000: Memory Usage (2027180K) : Executing rule SB.4
+2022-12-05 05:49:15 +0000: Memory Usage (2027180K) : Executing rule SB.5a
+2022-12-05 05:49:17 +0000: Memory Usage (2116520K) : Executing rule SB.5b
+2022-12-05 05:49:17 +0000: Memory Usage (2116520K) : Executing rule SB.6
+2022-12-05 05:49:17 +0000: Memory Usage (2116520K) : Executing rule SB.7
+2022-12-05 05:49:17 +0000: Memory Usage (2116520K) : Executing rule SB.8
+2022-12-05 05:49:17 +0000: Memory Usage (2116520K) : Executing rule SB.9
+2022-12-05 05:49:17 +0000: Memory Usage (2116520K) : Executing rule SB.10
+2022-12-05 05:49:17 +0000: Memory Usage (2116520K) : Executing rule SB.11
+2022-12-05 05:49:17 +0000: Memory Usage (2116520K) : Executing rule SB.12
+2022-12-05 05:49:18 +0000: Memory Usage (2116520K) : Executing rule SB.13
+2022-12-05 05:49:18 +0000: Memory Usage (2116520K) : Executing rule SB.14a
+2022-12-05 05:49:18 +0000: Memory Usage (2116520K) : Executing rule SB.14b
+2022-12-05 05:49:18 +0000: Memory Usage (2116520K) : Executing rule SB.15a
+2022-12-05 05:49:20 +0000: Memory Usage (2165236K) : Executing rule SB.15b
+2022-12-05 05:49:20 +0000: Memory Usage (2165236K) : Executing rule SB.16
+2022-12-05 05:49:20 +0000: Memory Usage (2165236K) : Executing rule ESD.1
+2022-12-05 05:49:20 +0000: Memory Usage (2165236K) : Executing rule ESD.2
+2022-12-05 05:49:20 +0000: Memory Usage (2165236K) : Executing rule ESD.3a
+2022-12-05 05:49:20 +0000: Memory Usage (2165236K) : Executing rule ESD.3b
+2022-12-05 05:49:20 +0000: Memory Usage (2165236K) : Executing rule ESD.4a
+2022-12-05 05:49:21 +0000: Memory Usage (2165236K) : Executing rule ESD.4b
+2022-12-05 05:49:21 +0000: Memory Usage (2165236K) : Executing rule ESD.5a
+2022-12-05 05:49:21 +0000: Memory Usage (2165236K) : Executing rule ESD.5b
+2022-12-05 05:49:21 +0000: Memory Usage (2165236K) : Executing rule ESD.6
+2022-12-05 05:49:22 +0000: Memory Usage (2192464K) : Executing rule ESD.7
+2022-12-05 05:49:22 +0000: Memory Usage (2192464K) : Executing rule ESD.8
+2022-12-05 05:49:22 +0000: Memory Usage (2192464K) : Executing rule ESD.pl
+2022-12-05 05:49:23 +0000: Memory Usage (2192464K) : Executing rule ESD.9
+2022-12-05 05:49:23 +0000: Memory Usage (2192464K) : Executing rule ESD.10
+2022-12-05 05:49:23 +0000: Memory Usage (2192464K) : Executing rule CO.1
+2022-12-05 05:49:25 +0000: Memory Usage (2283188K) : Executing rule CO.2a
+2022-12-05 05:49:32 +0000: Memory Usage (2380988K) : Executing rule CO.2b
+2022-12-05 05:49:32 +0000: Memory Usage (2380988K) : Executing rule CO.3
+2022-12-05 05:49:35 +0000: Memory Usage (2519144K) : Executing rule CO.4
+2022-12-05 05:49:41 +0000: Memory Usage (2711548K) : Executing rule CO.5a
+2022-12-05 05:49:41 +0000: Memory Usage (2711548K) : Executing rule CO.5b
+2022-12-05 05:49:41 +0000: Memory Usage (2711548K) : Executing rule CO.6
+2022-12-05 05:50:30 +0000: Memory Usage (2795612K) : Executing rule CO.6a
+2022-12-05 05:51:42 +0000: Memory Usage (3186708K) : Executing rule CO.6b
+2022-12-05 05:51:44 +0000: Memory Usage (3218656K) : Executing rule CO.7
+2022-12-05 05:51:47 +0000: Memory Usage (3308236K) : Executing rule CO.8
+2022-12-05 05:51:49 +0000: Memory Usage (3308236K) : Executing rule CO.9
+2022-12-05 05:51:50 +0000: Memory Usage (3308236K) : Executing rule CO.10
+2022-12-05 05:51:50 +0000: Memory Usage (3308236K) : Executing rule CO.11
+2022-12-05 05:51:54 +0000: Memory Usage (3394420K) : Executing rule MC.1
+2022-12-05 05:51:54 +0000: Memory Usage (3394420K) : Executing rule MC.2
+2022-12-05 05:51:54 +0000: Memory Usage (3394420K) : Executing rule MC.3
+2022-12-05 05:51:54 +0000: Memory Usage (3394420K) : Executing rule MC.4
+2022-12-05 05:51:55 +0000: Memory Usage (3308348K) : Executing rule PRES.1
+2022-12-05 05:51:55 +0000: Memory Usage (3308348K) : Executing rule PRES.2
+2022-12-05 05:51:55 +0000: Memory Usage (3308348K) : Executing rule PRES.3
+2022-12-05 05:51:55 +0000: Memory Usage (3308348K) : Executing rule PRES.4
+2022-12-05 05:51:55 +0000: Memory Usage (3308348K) : Executing rule PRES.5
+2022-12-05 05:51:55 +0000: Memory Usage (3308348K) : Executing rule PRES.6
+2022-12-05 05:51:55 +0000: Memory Usage (3308348K) : Executing rule PRES.7
+2022-12-05 05:51:55 +0000: Memory Usage (3308348K) : Executing rule PRES.9a
+2022-12-05 05:51:56 +0000: Memory Usage (3308348K) : Executing rule PRES.9b
+2022-12-05 05:51:56 +0000: Memory Usage (3308348K) : Executing rule LRES.1
+2022-12-05 05:51:56 +0000: Memory Usage (3308348K) : Executing rule LRES.2
+2022-12-05 05:51:56 +0000: Memory Usage (3308348K) : Executing rule LRES.3
+2022-12-05 05:51:56 +0000: Memory Usage (3308348K) : Executing rule LRES.4
+2022-12-05 05:51:56 +0000: Memory Usage (3308348K) : Executing rule LRES.5
+2022-12-05 05:51:57 +0000: Memory Usage (3308348K) : Executing rule LRES.6
+2022-12-05 05:51:57 +0000: Memory Usage (3308348K) : Executing rule LRES.7
+2022-12-05 05:51:58 +0000: Memory Usage (3308348K) : Executing rule LRES.9a
+2022-12-05 05:51:58 +0000: Memory Usage (3308348K) : Executing rule LRES.9b
+2022-12-05 05:51:59 +0000: Memory Usage (3308348K) : Executing rule HRES.1
+2022-12-05 05:51:59 +0000: Memory Usage (3308348K) : Executing rule HRES.2
+2022-12-05 05:51:59 +0000: Memory Usage (3308348K) : Executing rule HRES.3
+2022-12-05 05:51:59 +0000: Memory Usage (3308348K) : Executing rule HRES.4
+2022-12-05 05:51:59 +0000: Memory Usage (3308348K) : Executing rule HRES.5
+2022-12-05 05:51:59 +0000: Memory Usage (3308348K) : Executing rule HRES.6
+2022-12-05 05:52:00 +0000: Memory Usage (3316540K) : Executing rule HRES.7
+2022-12-05 05:52:00 +0000: Memory Usage (3316540K) : Executing rule HRES.8
+2022-12-05 05:52:00 +0000: Memory Usage (3316540K) : Executing rule HRES.9
+2022-12-05 05:52:01 +0000: Memory Usage (3316540K) : Executing rule HRES.10
+2022-12-05 05:52:01 +0000: Memory Usage (3316540K) : Executing rule HRES.12a
+2022-12-05 05:52:01 +0000: Memory Usage (3316540K) : Executing rule HRES.12b
+2022-12-05 05:52:01 +0000: Memory Usage (3316540K) : MIM Capacitor Option B section
+2022-12-05 05:52:01 +0000: Memory Usage (3316540K) : Executing rule MIMTM.1
+2022-12-05 05:52:01 +0000: Memory Usage (3316540K) : Executing rule MIMTM.2
+2022-12-05 05:52:02 +0000: Memory Usage (3316540K) : Executing rule MIMTM.3
+2022-12-05 05:52:02 +0000: Memory Usage (3316540K) : Executing rule MIMTM.4
+2022-12-05 05:52:02 +0000: Memory Usage (3316540K) : Executing rule MIMTM.5
+2022-12-05 05:52:02 +0000: Memory Usage (3325900K) : Executing rule MIMTM.6
+2022-12-05 05:52:02 +0000: Memory Usage (3325900K) : Executing rule MIMTM.7
+2022-12-05 05:52:02 +0000: Memory Usage (3325900K) : Executing rule MIMTM.8a
+2022-12-05 05:52:02 +0000: Memory Usage (3325900K) : Executing rule MIMTM.8b
+2022-12-05 05:52:02 +0000: Memory Usage (3325900K) : Executing rule MIMTM.9
+2022-12-05 05:52:02 +0000: Memory Usage (3325900K) : Executing rule MIMTM.10
+2022-12-05 05:52:03 +0000: Memory Usage (3325900K) : Executing rule MIMTM.11
+2022-12-05 05:52:03 +0000: Memory Usage (3325900K) : Executing rule NAT.1
+2022-12-05 05:52:03 +0000: Memory Usage (3328384K) : Executing rule NAT.2
+2022-12-05 05:52:03 +0000: Memory Usage (3328384K) : Executing rule NAT.3
+2022-12-05 05:52:03 +0000: Memory Usage (3328384K) : Executing rule NAT.4
+2022-12-05 05:52:04 +0000: Memory Usage (3331932K) : Executing rule NAT.5
+2022-12-05 05:52:05 +0000: Memory Usage (3341676K) : CONNECTIVITY_RULES section
+2022-12-05 05:52:05 +0000: Memory Usage (3341676K) : Executing rule NAT.6
+2022-12-05 05:52:05 +0000: Memory Usage (3341676K) : Executing rule NAT.7
+2022-12-05 05:52:05 +0000: Memory Usage (3341676K) : Executing rule NAT.8
+2022-12-05 05:52:06 +0000: Memory Usage (3341676K) : Executing rule NAT.9
+2022-12-05 05:52:06 +0000: Memory Usage (3341676K) : Executing rule NAT.10
+2022-12-05 05:52:06 +0000: Memory Usage (3341676K) : Executing rule NAT.11
+2022-12-05 05:52:06 +0000: Memory Usage (3341676K) : Executing rule NAT.12
+2022-12-05 05:52:06 +0000: Memory Usage (3345660K) : Executing rule BJT.1
+2022-12-05 05:52:06 +0000: Memory Usage (3345660K) : Executing rule BJT.2
+2022-12-05 05:52:06 +0000: Memory Usage (3372556K) : Executing rule BJT.3
+2022-12-05 05:52:07 +0000: Memory Usage (3372556K) : Executing rule DE.2
+2022-12-05 05:52:07 +0000: Memory Usage (3372556K) : Executing rule DE.3
+2022-12-05 05:52:07 +0000: Memory Usage (3372556K) : Executing rule DE.4
+2022-12-05 05:52:07 +0000: Memory Usage (3375332K) : Executing rule LVS_BJT.1
+2022-12-05 05:52:07 +0000: Memory Usage (3375332K) : Executing rule O.DF.3a
+2022-12-05 05:52:07 +0000: Memory Usage (3375332K) : Executing rule O.DF.6
+2022-12-05 05:52:07 +0000: Memory Usage (3375332K) : Executing rule O.DF.9
+2022-12-05 05:52:07 +0000: Memory Usage (3375332K) : Executing rule O.PL.2
+2022-12-05 05:52:09 +0000: Memory Usage (3390488K) : Executing rule O.PL.3a
+2022-12-05 05:52:10 +0000: Memory Usage (3448988K) : Executing rule O.PL.4
+2022-12-05 05:52:11 +0000: Memory Usage (3448988K) : Executing rule O.SB.2
+2022-12-05 05:52:11 +0000: Memory Usage (3448988K) : Executing rule O.SB.3
+2022-12-05 05:52:11 +0000: Memory Usage (3448988K) : Executing rule O.SB.4
+2022-12-05 05:52:11 +0000: Memory Usage (3448988K) : Executing rule O.SB.5b_3.3V
+2022-12-05 05:52:11 +0000: Memory Usage (3448988K) : Executing rule O.SB.9
+2022-12-05 05:52:11 +0000: Memory Usage (3448988K) : Executing rule O.SB.11
+2022-12-05 05:52:11 +0000: Memory Usage (3448988K) : Executing rule O.SB.13_3.3V
+2022-12-05 05:52:11 +0000: Memory Usage (3448988K) : Executing rule O.SB.13_5V
+2022-12-05 05:52:11 +0000: Memory Usage (3448988K) : Executing rule O.CO.7
+2022-12-05 05:52:14 +0000: Memory Usage (3588144K) : Executing rule O.PL.ORT
+2022-12-05 05:52:18 +0000: Memory Usage (3588144K) : Executing rule EF.01
+2022-12-05 05:52:18 +0000: Memory Usage (3588144K) : Executing rule EF.02
+2022-12-05 05:52:18 +0000: Memory Usage (3588144K) : Executing rule EF.03
+2022-12-05 05:52:18 +0000: Memory Usage (3588144K) : Executing rule EF.04a
+2022-12-05 05:52:19 +0000: Memory Usage (3588144K) : Executing rule EF.04b
+2022-12-05 05:52:19 +0000: Memory Usage (3588144K) : Executing rule EF.04c
+2022-12-05 05:52:19 +0000: Memory Usage (3588144K) : Executing rule EF.04d
+2022-12-05 05:52:19 +0000: Memory Usage (3588144K) : Executing rule EF.05
+2022-12-05 05:52:19 +0000: Memory Usage (3588144K) : Executing rule EF.06
+2022-12-05 05:52:19 +0000: Memory Usage (3588144K) : Executing rule EF.07
+2022-12-05 05:52:19 +0000: Memory Usage (3588144K) : Executing rule EF.08
+2022-12-05 05:52:19 +0000: Memory Usage (3588144K) : Executing rule EF.09
+2022-12-05 05:52:20 +0000: Memory Usage (3588144K) : Executing rule EF.10
+2022-12-05 05:52:20 +0000: Memory Usage (3588144K) : Executing rule EF.11
+2022-12-05 05:52:20 +0000: Memory Usage (3588144K) : Executing rule EF.12
+2022-12-05 05:52:20 +0000: Memory Usage (3588144K) : Executing rule EF.13
+2022-12-05 05:52:20 +0000: Memory Usage (3588144K) : Executing rule EF.14
+2022-12-05 05:52:20 +0000: Memory Usage (3588144K) : Executing rule EF.15
+2022-12-05 05:52:20 +0000: Memory Usage (3588144K) : Executing rule EF.16a
+2022-12-05 05:52:20 +0000: Memory Usage (3588144K) : Executing rule EF.16b
+2022-12-05 05:52:20 +0000: Memory Usage (3588144K) : Executing rule EF.17
+2022-12-05 05:52:20 +0000: Memory Usage (3588144K) : Executing rule EF.18
+2022-12-05 05:52:23 +0000: Memory Usage (3678520K) : Executing rule EF.19
+2022-12-05 05:52:24 +0000: Memory Usage (3678520K) : Executing rule EF.20
+2022-12-05 05:52:24 +0000: Memory Usage (3678520K) : Executing rule EF.21
+2022-12-05 05:52:24 +0000: Memory Usage (3678520K) : Executing rule EF.22a
+2022-12-05 05:52:25 +0000: Memory Usage (3678520K) : Executing rule EF.22b
+2022-12-05 05:52:25 +0000: Memory Usage (3678520K) : Executing rule MDN.1
+2022-12-05 05:52:25 +0000: Memory Usage (3678520K) : CONNECTIVITY_RULES section
+2022-12-05 05:52:25 +0000: Memory Usage (3678520K) : Executing rule MDN.2a
+2022-12-05 05:52:25 +0000: Memory Usage (3678520K) : Executing rule MDN.2b
+2022-12-05 05:52:26 +0000: Memory Usage (3678520K) : Executing rule MDN.3a
+2022-12-05 05:52:26 +0000: Memory Usage (3678520K) : Executing rule MDN.3b
+2022-12-05 05:52:26 +0000: Memory Usage (3678520K) : Executing rule MDN.4a
+2022-12-05 05:52:26 +0000: Memory Usage (3678520K) : Executing rule MDN.4b
+2022-12-05 05:52:26 +0000: Memory Usage (3678520K) : Executing rule MDN.5ai
+2022-12-05 05:52:26 +0000: Memory Usage (3678520K) : Executing rule MDN.5aii
+2022-12-05 05:52:27 +0000: Memory Usage (3678520K) : Executing rule MDN.5b
+2022-12-05 05:52:27 +0000: Memory Usage (3678520K) : Executing rule MDN.5c
+2022-12-05 05:52:27 +0000: Memory Usage (3678520K) : Executing rule MDN.6
+2022-12-05 05:52:28 +0000: Memory Usage (3678520K) : Executing rule MDN.6a
+2022-12-05 05:52:28 +0000: Memory Usage (3678520K) : Executing rule MDN.7
+2022-12-05 05:52:28 +0000: Memory Usage (3678520K) : Executing rule MDN.7a
+2022-12-05 05:52:28 +0000: Memory Usage (3678520K) : CONNECTIVITY_RULES section
+2022-12-05 05:52:28 +0000: Memory Usage (3678520K) : Executing rule MDN.8a
+2022-12-05 05:52:28 +0000: Memory Usage (3678520K) : Executing rule MDN.8b
+2022-12-05 05:52:28 +0000: Memory Usage (3678520K) : Executing rule MDN.9
+2022-12-05 05:52:29 +0000: Memory Usage (3691440K) : Executing rule MDN.10a
+2022-12-05 05:52:29 +0000: Memory Usage (3691440K) : Executing rule MDN.10b
+2022-12-05 05:52:30 +0000: Memory Usage (3691440K) : Executing rule MDN.10c
+2022-12-05 05:52:32 +0000: Memory Usage (3718440K) : Executing rule MDN.10d
+2022-12-05 05:52:32 +0000: Memory Usage (3718440K) : Executing rule MDN.10ei
+2022-12-05 05:52:33 +0000: Memory Usage (3719160K) : Executing rule MDN.10eii
+2022-12-05 05:52:33 +0000: Memory Usage (3725052K) : Executing rule MDN.10f
+2022-12-05 05:52:34 +0000: Memory Usage (3773072K) : Executing rule MDN.11
+2022-12-05 05:52:35 +0000: Memory Usage (3779976K) : Executing rule MDN.12
+2022-12-05 05:52:35 +0000: Memory Usage (3779976K) : Executing rule MDN.13a
+2022-12-05 05:52:36 +0000: Memory Usage (3783416K) : Executing rule MDN.13b
+2022-12-05 05:52:36 +0000: Memory Usage (3783416K) : Executing rule MDN.13c
+2022-12-05 05:52:38 +0000: Memory Usage (3819032K) : Executing rule MDN.13d
+2022-12-05 05:52:38 +0000: Memory Usage (3819032K) : Executing rule MDN.14
+2022-12-05 05:52:38 +0000: Memory Usage (3819032K) : Executing rule MDN.15a
+2022-12-05 05:52:38 +0000: Memory Usage (3819032K) : Executing rule MDN.15b
+2022-12-05 05:52:39 +0000: Memory Usage (3819032K) : Executing rule MDN.17
+2022-12-05 05:52:40 +0000: Memory Usage (3834236K) : Executing rule MDP.1
+2022-12-05 05:52:41 +0000: Memory Usage (3857444K) : Executing rule MDP.1a
+2022-12-05 05:54:13 +0000: Memory Usage (4449844K) : Executing rule MDP.2
+2022-12-05 05:54:14 +0000: Memory Usage (4467972K) : Executing rule MDP.3
+2022-12-05 05:54:14 +0000: Memory Usage (4467972K) : Executing rule MDP.3ai
+2022-12-05 05:54:14 +0000: Memory Usage (4467972K) : Executing rule MDP.3aii
+2022-12-05 05:54:14 +0000: Memory Usage (4467972K) : Executing rule MDP.3b
+2022-12-05 05:54:15 +0000: Memory Usage (4467972K) : Executing rule MDP.3c
+2022-12-05 05:54:15 +0000: Memory Usage (4467972K) : Executing rule MDP.3d
+2022-12-05 05:54:15 +0000: Memory Usage (4467972K) : Executing rule MDP.4
+2022-12-05 05:54:20 +0000: Memory Usage (4484996K) : Executing rule MDP.4a
+2022-12-05 05:54:21 +0000: Memory Usage (4484996K) : Executing rule MDP.4b
+2022-12-05 05:54:21 +0000: Memory Usage (4484996K) : Executing rule MDP.5
+2022-12-05 05:54:22 +0000: Memory Usage (4487036K) : Executing rule MDP.5a
+2022-12-05 05:54:22 +0000: Memory Usage (4487036K) : Executing rule MDP.6
+2022-12-05 05:54:22 +0000: Memory Usage (4487036K) : Executing rule MDP.6a
+2022-12-05 05:54:22 +0000: Memory Usage (4487036K) : Executing rule MDP.7
+2022-12-05 05:54:22 +0000: Memory Usage (4487036K) : Executing rule MDP.8
+2022-12-05 05:54:22 +0000: Memory Usage (4487036K) : Executing rule MDP.9a
+2022-12-05 05:54:22 +0000: Memory Usage (4487036K) : Executing rule MDP.9b
+2022-12-05 05:54:22 +0000: Memory Usage (4487036K) : Executing rule MDP.9c
+2022-12-05 05:54:23 +0000: Memory Usage (4525872K) : Executing rule MDP.9d
+2022-12-05 05:54:27 +0000: Memory Usage (4587276K) : Executing rule MDP.9ei
+2022-12-05 05:54:28 +0000: Memory Usage (4611620K) : Executing rule MDP.9eii
+2022-12-05 05:54:28 +0000: Memory Usage (4611620K) : Executing rule MDP.9f
+2022-12-05 05:54:29 +0000: Memory Usage (4627940K) : Executing rule MDP.10
+2022-12-05 05:54:29 +0000: Memory Usage (4627940K) : CONNECTIVITY_RULES section
+2022-12-05 05:54:29 +0000: Memory Usage (4627940K) : Executing rule MDP.10a
+2022-12-05 05:54:29 +0000: Memory Usage (4627940K) : Executing rule MDP.10b
+2022-12-05 05:54:29 +0000: Memory Usage (4627940K) : Executing rule MDP.11
+2022-12-05 05:54:29 +0000: Memory Usage (4627940K) : Executing rule MDP.12
+2022-12-05 05:54:30 +0000: Memory Usage (4647808K) : Executing rule MDP.13a
+2022-12-05 05:54:31 +0000: Memory Usage (4664148K) : Executing rule MDP.13b
+2022-12-05 05:54:31 +0000: Memory Usage (4664148K) : Executing rule MDP.13c
+2022-12-05 05:54:31 +0000: Memory Usage (4688532K) : Executing rule MDP.15
+2022-12-05 05:54:31 +0000: Memory Usage (4688532K) : Executing rule MDP.16a
+2022-12-05 05:54:32 +0000: Memory Usage (4688532K) : Executing rule MDP.16b
+2022-12-05 05:54:32 +0000: Memory Usage (4688532K) : Executing rule MDP.17a
+2022-12-05 05:54:32 +0000: Memory Usage (4688532K) : Executing rule MDP.17c
+2022-12-05 05:54:32 +0000: Memory Usage (4688532K) : Executing rule Y.NW.2b_3.3V
+2022-12-05 05:54:32 +0000: Memory Usage (4688532K) : Executing rule Y.NW.2b_5V
+2022-12-05 05:54:32 +0000: Memory Usage (4688532K) : Executing rule Y.DF.6_5V
+2022-12-05 05:54:33 +0000: Memory Usage (4688532K) : Executing rule Y.DF.16_3.3V
+2022-12-05 05:54:33 +0000: Memory Usage (4688532K) : Executing rule Y.DF.16_5V
+2022-12-05 05:54:33 +0000: Memory Usage (4688532K) : Executing rule Y.PL.1_3.3V
+2022-12-05 05:54:33 +0000: Memory Usage (4688532K) : Executing rule Y.PL.1_5V
+2022-12-05 05:54:33 +0000: Memory Usage (4688532K) : Executing rule Y.PL.2_3.3V
+2022-12-05 05:54:35 +0000: Memory Usage (4702624K) : Executing rule Y.PL.2_5V
+2022-12-05 05:54:36 +0000: Memory Usage (4719036K) : Executing rule Y.PL.4_5V
+2022-12-05 05:54:36 +0000: Memory Usage (4719036K) : Executing rule Y.PL.5a_3.3V
+2022-12-05 05:54:36 +0000: Memory Usage (4719036K) : Executing rule Y.PL.5a_5V
+2022-12-05 05:54:37 +0000: Memory Usage (4719036K) : Executing rule Y.PL.5b_3.3V
+2022-12-05 05:54:37 +0000: Memory Usage (4719036K) : Executing rule Y.PL.5b_5V
+2022-12-05 05:54:37 +0000: Memory Usage (4719036K) : Executing rule S.DF.4c_MV
+2022-12-05 05:54:37 +0000: Memory Usage (4719036K) : Executing rule S.DF.6_MV
+2022-12-05 05:54:37 +0000: Memory Usage (4719036K) : Executing rule S.DF.7_MV
+2022-12-05 05:54:37 +0000: Memory Usage (4719036K) : Executing rule S.DF.8_MV
+2022-12-05 05:54:37 +0000: Memory Usage (4719036K) : Executing rule S.DF.16_MV
+2022-12-05 05:54:38 +0000: Memory Usage (4737700K) : Executing rule S.PL.5a_MV
+2022-12-05 05:54:38 +0000: Memory Usage (4737700K) : Executing rule S.PL.5b_MV
+2022-12-05 05:54:38 +0000: Memory Usage (4737700K) : Executing rule S.CO.4_MV
+2022-12-05 05:54:38 +0000: Memory Usage (4737700K) : Executing rule S.DF.4c_LV
+2022-12-05 05:54:38 +0000: Memory Usage (4737700K) : Executing rule S.DF.16_LV
+2022-12-05 05:54:39 +0000: Memory Usage (4755016K) : Executing rule S.CO.3_LV
+2022-12-05 05:54:39 +0000: Memory Usage (4755016K) : Executing rule S.CO.4_LV
+2022-12-05 05:54:39 +0000: Memory Usage (4755016K) : Executing rule S.CO.6_ii_LV
+2022-12-05 05:54:39 +0000: Memory Usage (4755016K) : Executing rule S.M1.1_LV
+2022-12-05 05:54:39 +0000: Memory Usage (4755016K) : OFFGRID-ANGLES section
+2022-12-05 05:54:39 +0000: Memory Usage (4755016K) : Executing rule comp_OFFGRID
+2022-12-05 05:54:39 +0000: Memory Usage (4755016K) : Executing rule dnwell_OFFGRID
+2022-12-05 05:54:40 +0000: Memory Usage (4755016K) : Executing rule nwell_OFFGRID
+2022-12-05 05:54:40 +0000: Memory Usage (4755016K) : Executing rule lvpwell_OFFGRID
+2022-12-05 05:54:40 +0000: Memory Usage (4755016K) : Executing rule dualgate_OFFGRID
+2022-12-05 05:54:40 +0000: Memory Usage (4755016K) : Executing rule poly2_OFFGRID
+2022-12-05 05:54:40 +0000: Memory Usage (4755016K) : Executing rule nplus_OFFGRID
+2022-12-05 05:54:40 +0000: Memory Usage (4755016K) : Executing rule pplus_OFFGRID
+2022-12-05 05:54:40 +0000: Memory Usage (4755016K) : Executing rule sab_OFFGRID
+2022-12-05 05:54:40 +0000: Memory Usage (4755016K) : Executing rule esd_OFFGRID
+2022-12-05 05:54:40 +0000: Memory Usage (4755016K) : Executing rule contact_OFFGRID
+2022-12-05 05:54:41 +0000: Memory Usage (4755016K) : Executing rule metal1_OFFGRID
+2022-12-05 05:54:41 +0000: Memory Usage (4755016K) : Executing rule via1_OFFGRID
+2022-12-05 05:54:41 +0000: Memory Usage (4755016K) : Executing rule metal2_OFFGRID
+2022-12-05 05:54:41 +0000: Memory Usage (4755016K) : Executing rule via2_OFFGRID
+2022-12-05 05:54:41 +0000: Memory Usage (4755016K) : Executing rule metal3_OFFGRID
+2022-12-05 05:54:41 +0000: Memory Usage (4755016K) : Executing rule via3_OFFGRID
+2022-12-05 05:54:41 +0000: Memory Usage (4755016K) : Executing rule metal4_OFFGRID
+2022-12-05 05:54:42 +0000: Memory Usage (4755016K) : Executing rule via4_OFFGRID
+2022-12-05 05:54:42 +0000: Memory Usage (4755016K) : Executing rule metal5_OFFGRID
+2022-12-05 05:54:42 +0000: Memory Usage (4755016K) : Executing rule via5_OFFGRID
+2022-12-05 05:54:42 +0000: Memory Usage (4755016K) : Executing rule metaltop_OFFGRID
+2022-12-05 05:54:42 +0000: Memory Usage (4755016K) : Executing rule pad_OFFGRID
+2022-12-05 05:54:42 +0000: Memory Usage (4755016K) : Executing rule resistor_OFFGRID
+2022-12-05 05:54:42 +0000: Memory Usage (4755016K) : Executing rule fhres_OFFGRID
+2022-12-05 05:54:42 +0000: Memory Usage (4755016K) : Executing rule fusetop_OFFGRID
+2022-12-05 05:54:42 +0000: Memory Usage (4755016K) : Executing rule fusewindow_d_OFFGRID
+2022-12-05 05:54:42 +0000: Memory Usage (4755016K) : Executing rule polyfuse_OFFGRID
+2022-12-05 05:54:43 +0000: Memory Usage (4755016K) : Executing rule mvsd_OFFGRID
+2022-12-05 05:54:43 +0000: Memory Usage (4755016K) : Executing rule mvpsd_OFFGRID
+2022-12-05 05:54:43 +0000: Memory Usage (4755016K) : Executing rule nat_OFFGRID
+2022-12-05 05:54:43 +0000: Memory Usage (4755016K) : Executing rule comp_dummy_OFFGRID
+2022-12-05 05:54:43 +0000: Memory Usage (4755016K) : Executing rule poly2_dummy_OFFGRID
+2022-12-05 05:54:43 +0000: Memory Usage (4755016K) : Executing rule metal1_dummy_OFFGRID
+2022-12-05 05:54:43 +0000: Memory Usage (4755016K) : Executing rule metal2_dummy_OFFGRID
+2022-12-05 05:54:43 +0000: Memory Usage (4755016K) : Executing rule metal3_dummy_OFFGRID
+2022-12-05 05:54:43 +0000: Memory Usage (4755016K) : Executing rule metal4_dummy_OFFGRID
+2022-12-05 05:54:44 +0000: Memory Usage (4755016K) : Executing rule metal5_dummy_OFFGRID
+2022-12-05 05:54:44 +0000: Memory Usage (4755016K) : Executing rule metaltop_dummy_OFFGRID
+2022-12-05 05:54:44 +0000: Memory Usage (4755016K) : Executing rule comp_label_OFFGRID
+2022-12-05 05:54:44 +0000: Memory Usage (4755016K) : Executing rule poly2_label_OFFGRID
+2022-12-05 05:54:44 +0000: Memory Usage (4755016K) : Executing rule metal1_label_OFFGRID
+2022-12-05 05:54:44 +0000: Memory Usage (4755016K) : Executing rule metal2_label_OFFGRID
+2022-12-05 05:54:44 +0000: Memory Usage (4755016K) : Executing rule metal3_label_OFFGRID
+2022-12-05 05:54:44 +0000: Memory Usage (4755016K) : Executing rule metal4_label_OFFGRID
+2022-12-05 05:54:44 +0000: Memory Usage (4755016K) : Executing rule metal5_label_OFFGRID
+2022-12-05 05:54:45 +0000: Memory Usage (4755016K) : Executing rule metaltop_label_OFFGRID
+2022-12-05 05:54:45 +0000: Memory Usage (4755016K) : Executing rule metal1_slot_OFFGRID
+2022-12-05 05:54:45 +0000: Memory Usage (4755016K) : Executing rule metal2_slot_OFFGRID
+2022-12-05 05:54:45 +0000: Memory Usage (4755016K) : Executing rule metal3_slot_OFFGRID
+2022-12-05 05:54:45 +0000: Memory Usage (4755016K) : Executing rule metal4_slot_OFFGRID
+2022-12-05 05:54:45 +0000: Memory Usage (4755016K) : Executing rule metal5_slot_OFFGRID
+2022-12-05 05:54:45 +0000: Memory Usage (4755016K) : Executing rule metaltop_slot_OFFGRID
+2022-12-05 05:54:45 +0000: Memory Usage (4755016K) : Executing rule ubmpperi_OFFGRID
+2022-12-05 05:54:45 +0000: Memory Usage (4755016K) : Executing rule ubmparray_OFFGRID
+2022-12-05 05:54:46 +0000: Memory Usage (4755016K) : Executing rule ubmeplate_OFFGRID
+2022-12-05 05:54:46 +0000: Memory Usage (4755016K) : Executing rule schottky_diode_OFFGRID
+2022-12-05 05:54:46 +0000: Memory Usage (4755016K) : Executing rule zener_OFFGRID
+2022-12-05 05:54:46 +0000: Memory Usage (4755016K) : Executing rule res_mk_OFFGRID
+2022-12-05 05:54:46 +0000: Memory Usage (4755016K) : Executing rule opc_drc_OFFGRID
+2022-12-05 05:54:46 +0000: Memory Usage (4755016K) : Executing rule ndmy_OFFGRID
+2022-12-05 05:54:46 +0000: Memory Usage (4755016K) : Executing rule pmndmy_OFFGRID
+2022-12-05 05:54:46 +0000: Memory Usage (4755016K) : Executing rule v5_xtor_OFFGRID
+2022-12-05 05:54:46 +0000: Memory Usage (4755016K) : Executing rule cap_mk_OFFGRID
+2022-12-05 05:54:47 +0000: Memory Usage (4755016K) : Executing rule mos_cap_mk_OFFGRID
+2022-12-05 05:54:47 +0000: Memory Usage (4755016K) : Executing rule ind_mk_OFFGRID
+2022-12-05 05:54:47 +0000: Memory Usage (4755016K) : Executing rule diode_mk_OFFGRID
+2022-12-05 05:54:47 +0000: Memory Usage (4755016K) : Executing rule drc_bjt_OFFGRID
+2022-12-05 05:54:47 +0000: Memory Usage (4755016K) : Executing rule lvs_bjt_OFFGRID
+2022-12-05 05:54:47 +0000: Memory Usage (4755016K) : Executing rule mim_l_mk_OFFGRID
+2022-12-05 05:54:47 +0000: Memory Usage (4755016K) : Executing rule latchup_mk_OFFGRID
+2022-12-05 05:54:47 +0000: Memory Usage (4755016K) : Executing rule guard_ring_mk_OFFGRID
+2022-12-05 05:54:47 +0000: Memory Usage (4755016K) : Executing rule otp_mk_OFFGRID
+2022-12-05 05:54:47 +0000: Memory Usage (4755016K) : Executing rule mtpmark_OFFGRID
+2022-12-05 05:54:48 +0000: Memory Usage (4755016K) : Executing rule neo_ee_mk_OFFGRID
+2022-12-05 05:54:48 +0000: Memory Usage (4755016K) : Executing rule sramcore_OFFGRID
+2022-12-05 05:54:48 +0000: Memory Usage (4755016K) : Executing rule lvs_rf_OFFGRID
+2022-12-05 05:54:48 +0000: Memory Usage (4755016K) : Executing rule lvs_drain_OFFGRID
+2022-12-05 05:54:48 +0000: Memory Usage (4755016K) : Executing rule hvpolyrs_OFFGRID
+2022-12-05 05:54:48 +0000: Memory Usage (4755016K) : Executing rule lvs_io_OFFGRID
+2022-12-05 05:54:48 +0000: Memory Usage (4755016K) : Executing rule probe_mk_OFFGRID
+2022-12-05 05:54:48 +0000: Memory Usage (4755016K) : Executing rule esd_mk_OFFGRID
+2022-12-05 05:54:48 +0000: Memory Usage (4755016K) : Executing rule lvs_source_OFFGRID
+2022-12-05 05:54:49 +0000: Memory Usage (4755016K) : Executing rule well_diode_mk_OFFGRID
+2022-12-05 05:54:49 +0000: Memory Usage (4755016K) : Executing rule ldmos_xtor_OFFGRID
+2022-12-05 05:54:49 +0000: Memory Usage (4755016K) : Executing rule plfuse_OFFGRID
+2022-12-05 05:54:49 +0000: Memory Usage (4755016K) : Executing rule efuse_mk_OFFGRID
+2022-12-05 05:54:49 +0000: Memory Usage (4755016K) : Executing rule mcell_feol_mk_OFFGRID
+2022-12-05 05:54:49 +0000: Memory Usage (4755016K) : Executing rule ymtp_mk_OFFGRID
+2022-12-05 05:54:49 +0000: Memory Usage (4755016K) : Executing rule dev_wf_mk_OFFGRID
+2022-12-05 05:54:49 +0000: Memory Usage (4755016K) : Executing rule metal1_blk_OFFGRID
+2022-12-05 05:54:49 +0000: Memory Usage (4755016K) : Executing rule metal2_blk_OFFGRID
+2022-12-05 05:54:50 +0000: Memory Usage (4755016K) : Executing rule metal3_blk_OFFGRID
+2022-12-05 05:54:50 +0000: Memory Usage (4755016K) : Executing rule metal4_blk_OFFGRID
+2022-12-05 05:54:50 +0000: Memory Usage (4755016K) : Executing rule metal5_blk_OFFGRID
+2022-12-05 05:54:50 +0000: Memory Usage (4755016K) : Executing rule metalt_blk_OFFGRID
+2022-12-05 05:54:50 +0000: Memory Usage (4755016K) : Executing rule pr_bndry_OFFGRID
+2022-12-05 05:54:50 +0000: Memory Usage (4755016K) : Executing rule mdiode_OFFGRID
+2022-12-05 05:54:50 +0000: Memory Usage (4755016K) : Executing rule metal1_res_OFFGRID
+2022-12-05 05:54:50 +0000: Memory Usage (4755016K) : Executing rule metal2_res_OFFGRID
+2022-12-05 05:54:50 +0000: Memory Usage (4755016K) : Executing rule metal3_res_OFFGRID
+2022-12-05 05:54:51 +0000: Memory Usage (4755016K) : Executing rule metal4_res_OFFGRID
+2022-12-05 05:54:51 +0000: Memory Usage (4755016K) : Executing rule metal5_res_OFFGRID
+2022-12-05 05:54:51 +0000: Memory Usage (4755016K) : Executing rule metal6_res_OFFGRID
+2022-12-05 05:54:51 +0000: Memory Usage (4755016K) : Executing rule border_OFFGRID
+VmPeak:	 4755012 kB
+VmHWM:	 4194648 kB
+2022-12-05 05:54:51 +0000: Memory Usage (4755016K) : DRC Total Run time 467.523418 seconds

diff --git a/mpw_precheck/logs/klayout_feol_check.total b/mpw_precheck/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.total

@@ -0,0 +1 @@
+0
\ No newline at end of file

diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.log b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..a997b34
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.log

@@ -0,0 +1,16 @@
+"input" in: gf180mcu_density.lydrc:15
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 534.00M
+"area" in: gf180mcu_density.lydrc:17
+    Elapsed: 0.010s  Memory: 534.00M
+"polygons" in: gf180mcu_density.lydrc:19
+    Polygons (raw): 87436 (flat)  109 (hierarchical)
+    Elapsed: 0.010s  Memory: 535.00M
+"area" in: gf180mcu_density.lydrc:19
+    Elapsed: 0.030s  Memory: 535.00M
+comp_density is Infinity
+"output" in: gf180mcu_density.lydrc:22
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 535.00M
+Writing report database: /mnt/uffs/user/u9715_ashabar/design/testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 0.130s  Memory: 534.00M

diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.total b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.total

@@ -0,0 +1 @@
+0
\ No newline at end of file

diff --git a/mpw_precheck/logs/klayout_offgrid_check.log b/mpw_precheck/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..e7907f7
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.log

@@ -0,0 +1,349 @@
+2022-12-05 05:58:27 +0000: Memory Usage (543004K) : Starting running GF180MCU Klayout DRC runset on /root/testasynctrimux/gds/user_project_wrapper.gds
+2022-12-05 05:58:27 +0000: Memory Usage (543004K) : Ruby Version for klayout: 2.0.0
+2022-12-05 05:58:27 +0000: Memory Usage (553020K) : Loading database to memory is complete.
+2022-12-05 05:58:27 +0000: Memory Usage (553020K) : GF180MCU Klayout DRC runset output at: /mnt/uffs/user/u9715_ashabar/design/testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/outputs/reports/klayout_offgrid_check.xml
+2022-12-05 05:58:27 +0000: Memory Usage (553020K) : Number of threads to use 4
+2022-12-05 05:58:27 +0000: Memory Usage (553020K) : flat  mode is enabled.
+2022-12-05 05:58:27 +0000: Memory Usage (553020K) : Read in polygons from layers.
+2022-12-05 05:58:32 +0000: Memory Usage (656152K) : Starting deriving base layers.
+2022-12-05 05:58:34 +0000: Memory Usage (756748K) : Evaluate switches.
+2022-12-05 05:58:34 +0000: Memory Usage (756748K) : FEOL is disabled.
+2022-12-05 05:58:34 +0000: Memory Usage (756748K) : BEOL is disabled.
+2022-12-05 05:58:34 +0000: Memory Usage (756748K) : connectivity rules are enabled.
+2022-12-05 05:58:34 +0000: Memory Usage (756748K) : METAL_TOP Selected is 9K
+2022-12-05 05:58:34 +0000: Memory Usage (756748K) : METAL_STACK Selected is 5LM
+2022-12-05 05:58:34 +0000: Memory Usage (756748K) : Wedge enabled  true
+2022-12-05 05:58:34 +0000: Memory Usage (756748K) : Ball enabled  true
+2022-12-05 05:58:34 +0000: Memory Usage (756748K) : Gold enabled  true
+2022-12-05 05:58:34 +0000: Memory Usage (756748K) : MIM Option selected B
+/opt/checks/tech-files/gf180mcuC_mr.drc:543: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/gf180mcuC_mr.drc:463: warning: previous definition of OFFGRID was here
+2022-12-05 05:58:34 +0000: Memory Usage (756748K) : Offgrid enabled  true
+2022-12-05 05:58:34 +0000: Memory Usage (756748K) : Connectivity rules enabled, Netlist object will be generated.
+2022-12-05 05:58:34 +0000: Memory Usage (756748K) : Total area of the design is 8997120.228799999 um^2.
+2022-12-05 05:58:34 +0000: Memory Usage (756748K) : Total no. of polygons in the design is 730783
+2022-12-05 05:58:34 +0000: Memory Usage (756748K) : Initialization and base layers definition.
+2022-12-05 05:58:35 +0000: Memory Usage (756748K) : Starting GF180MCU DRC rules.
+2022-12-05 05:58:35 +0000: Memory Usage (756748K) : Executing rule MC.1
+2022-12-05 05:58:35 +0000: Memory Usage (756748K) : Executing rule MC.2
+2022-12-05 05:58:35 +0000: Memory Usage (756748K) : Executing rule MC.3
+2022-12-05 05:58:35 +0000: Memory Usage (756748K) : Executing rule MC.4
+2022-12-05 05:58:35 +0000: Memory Usage (756748K) : Executing rule PRES.1
+2022-12-05 05:58:35 +0000: Memory Usage (756748K) : Executing rule PRES.2
+2022-12-05 05:58:35 +0000: Memory Usage (756748K) : Executing rule PRES.3
+2022-12-05 05:58:35 +0000: Memory Usage (756748K) : Executing rule PRES.4
+2022-12-05 05:58:35 +0000: Memory Usage (756748K) : Executing rule PRES.5
+2022-12-05 05:58:35 +0000: Memory Usage (756748K) : Executing rule PRES.6
+2022-12-05 05:58:35 +0000: Memory Usage (756748K) : Executing rule PRES.7
+2022-12-05 05:58:35 +0000: Memory Usage (756748K) : Executing rule PRES.9a
+2022-12-05 05:58:35 +0000: Memory Usage (756748K) : Executing rule PRES.9b
+2022-12-05 05:58:36 +0000: Memory Usage (756748K) : Executing rule LRES.1
+2022-12-05 05:58:36 +0000: Memory Usage (756748K) : Executing rule LRES.2
+2022-12-05 05:58:36 +0000: Memory Usage (756748K) : Executing rule LRES.3
+2022-12-05 05:58:36 +0000: Memory Usage (756748K) : Executing rule LRES.4
+2022-12-05 05:58:36 +0000: Memory Usage (756748K) : Executing rule LRES.5
+2022-12-05 05:58:36 +0000: Memory Usage (756748K) : Executing rule LRES.6
+2022-12-05 05:58:37 +0000: Memory Usage (756748K) : Executing rule LRES.7
+2022-12-05 05:58:37 +0000: Memory Usage (756748K) : Executing rule LRES.9a
+2022-12-05 05:58:37 +0000: Memory Usage (756748K) : Executing rule LRES.9b
+2022-12-05 05:58:38 +0000: Memory Usage (764252K) : Executing rule HRES.1
+2022-12-05 05:58:38 +0000: Memory Usage (764252K) : Executing rule HRES.2
+2022-12-05 05:58:38 +0000: Memory Usage (764252K) : Executing rule HRES.3
+2022-12-05 05:58:38 +0000: Memory Usage (764252K) : Executing rule HRES.4
+2022-12-05 05:58:38 +0000: Memory Usage (764252K) : Executing rule HRES.5
+2022-12-05 05:58:38 +0000: Memory Usage (764252K) : Executing rule HRES.6
+2022-12-05 05:58:39 +0000: Memory Usage (776732K) : Executing rule HRES.7
+2022-12-05 05:58:39 +0000: Memory Usage (776732K) : Executing rule HRES.8
+2022-12-05 05:58:39 +0000: Memory Usage (776732K) : Executing rule HRES.9
+2022-12-05 05:58:39 +0000: Memory Usage (776732K) : Executing rule HRES.10
+2022-12-05 05:58:40 +0000: Memory Usage (776732K) : Executing rule HRES.12a
+2022-12-05 05:58:40 +0000: Memory Usage (776732K) : Executing rule HRES.12b
+2022-12-05 05:58:40 +0000: Memory Usage (776732K) : MIM Capacitor Option B section
+2022-12-05 05:58:40 +0000: Memory Usage (776732K) : Executing rule MIMTM.1
+2022-12-05 05:58:40 +0000: Memory Usage (776732K) : Executing rule MIMTM.2
+2022-12-05 05:58:40 +0000: Memory Usage (776732K) : Executing rule MIMTM.3
+2022-12-05 05:58:40 +0000: Memory Usage (776732K) : Executing rule MIMTM.4
+2022-12-05 05:58:40 +0000: Memory Usage (776732K) : Executing rule MIMTM.5
+2022-12-05 05:58:40 +0000: Memory Usage (790992K) : Executing rule MIMTM.6
+2022-12-05 05:58:40 +0000: Memory Usage (790992K) : Executing rule MIMTM.7
+2022-12-05 05:58:40 +0000: Memory Usage (790992K) : Executing rule MIMTM.8a
+2022-12-05 05:58:40 +0000: Memory Usage (790992K) : Executing rule MIMTM.8b
+2022-12-05 05:58:40 +0000: Memory Usage (790992K) : Executing rule MIMTM.9
+2022-12-05 05:58:40 +0000: Memory Usage (790992K) : Executing rule MIMTM.10
+2022-12-05 05:58:40 +0000: Memory Usage (790992K) : Executing rule MIMTM.11
+2022-12-05 05:58:41 +0000: Memory Usage (790992K) : Executing rule NAT.1
+2022-12-05 05:58:41 +0000: Memory Usage (793496K) : Executing rule NAT.2
+2022-12-05 05:58:41 +0000: Memory Usage (793496K) : Executing rule NAT.3
+2022-12-05 05:58:41 +0000: Memory Usage (793496K) : Executing rule NAT.4
+2022-12-05 05:58:42 +0000: Memory Usage (797068K) : Executing rule NAT.5
+2022-12-05 05:58:43 +0000: Memory Usage (806812K) : CONNECTIVITY_RULES section
+2022-12-05 05:58:43 +0000: Memory Usage (806812K) : Executing rule NAT.6
+2022-12-05 05:58:43 +0000: Memory Usage (806812K) : Executing rule NAT.7
+2022-12-05 05:58:43 +0000: Memory Usage (806812K) : Executing rule NAT.8
+2022-12-05 05:58:43 +0000: Memory Usage (806812K) : Executing rule NAT.9
+2022-12-05 05:58:43 +0000: Memory Usage (806812K) : Executing rule NAT.10
+2022-12-05 05:58:43 +0000: Memory Usage (806812K) : Executing rule NAT.11
+2022-12-05 05:58:43 +0000: Memory Usage (806812K) : Executing rule NAT.12
+2022-12-05 05:58:43 +0000: Memory Usage (810924K) : Executing rule BJT.1
+2022-12-05 05:58:43 +0000: Memory Usage (810924K) : Executing rule BJT.2
+2022-12-05 05:58:44 +0000: Memory Usage (837756K) : Executing rule BJT.3
+2022-12-05 05:58:44 +0000: Memory Usage (837756K) : Executing rule DE.2
+2022-12-05 05:58:44 +0000: Memory Usage (837756K) : Executing rule DE.3
+2022-12-05 05:58:44 +0000: Memory Usage (837756K) : Executing rule DE.4
+2022-12-05 05:58:44 +0000: Memory Usage (840548K) : Executing rule LVS_BJT.1
+2022-12-05 05:58:44 +0000: Memory Usage (840548K) : Executing rule O.DF.3a
+2022-12-05 05:58:44 +0000: Memory Usage (840548K) : Executing rule O.DF.6
+2022-12-05 05:58:44 +0000: Memory Usage (840548K) : Executing rule O.DF.9
+2022-12-05 05:58:44 +0000: Memory Usage (840548K) : Executing rule O.PL.2
+2022-12-05 05:58:46 +0000: Memory Usage (855688K) : Executing rule O.PL.3a
+2022-12-05 05:58:47 +0000: Memory Usage (914204K) : Executing rule O.PL.4
+2022-12-05 05:58:47 +0000: Memory Usage (914204K) : Executing rule O.SB.2
+2022-12-05 05:58:47 +0000: Memory Usage (914204K) : Executing rule O.SB.3
+2022-12-05 05:58:47 +0000: Memory Usage (914204K) : Executing rule O.SB.4
+2022-12-05 05:58:47 +0000: Memory Usage (914204K) : Executing rule O.SB.5b_3.3V
+2022-12-05 05:58:47 +0000: Memory Usage (914204K) : Executing rule O.SB.9
+2022-12-05 05:58:47 +0000: Memory Usage (914204K) : Executing rule O.SB.11
+2022-12-05 05:58:47 +0000: Memory Usage (914204K) : Executing rule O.SB.13_3.3V
+2022-12-05 05:58:48 +0000: Memory Usage (914204K) : Executing rule O.SB.13_5V
+2022-12-05 05:58:48 +0000: Memory Usage (914204K) : Executing rule O.CO.7
+2022-12-05 05:58:51 +0000: Memory Usage (1053504K) : Executing rule O.PL.ORT
+2022-12-05 05:58:54 +0000: Memory Usage (1053504K) : Executing rule EF.01
+2022-12-05 05:58:54 +0000: Memory Usage (1053504K) : Executing rule EF.02
+2022-12-05 05:58:54 +0000: Memory Usage (1053504K) : Executing rule EF.03
+2022-12-05 05:58:55 +0000: Memory Usage (1053504K) : Executing rule EF.04a
+2022-12-05 05:58:55 +0000: Memory Usage (1053504K) : Executing rule EF.04b
+2022-12-05 05:58:55 +0000: Memory Usage (1053504K) : Executing rule EF.04c
+2022-12-05 05:58:55 +0000: Memory Usage (1053504K) : Executing rule EF.04d
+2022-12-05 05:58:55 +0000: Memory Usage (1053504K) : Executing rule EF.05
+2022-12-05 05:58:55 +0000: Memory Usage (1053504K) : Executing rule EF.06
+2022-12-05 05:58:55 +0000: Memory Usage (1053504K) : Executing rule EF.07
+2022-12-05 05:58:55 +0000: Memory Usage (1053504K) : Executing rule EF.08
+2022-12-05 05:58:55 +0000: Memory Usage (1053504K) : Executing rule EF.09
+2022-12-05 05:58:55 +0000: Memory Usage (1053504K) : Executing rule EF.10
+2022-12-05 05:58:55 +0000: Memory Usage (1053504K) : Executing rule EF.11
+2022-12-05 05:58:55 +0000: Memory Usage (1053504K) : Executing rule EF.12
+2022-12-05 05:58:55 +0000: Memory Usage (1053504K) : Executing rule EF.13
+2022-12-05 05:58:55 +0000: Memory Usage (1053504K) : Executing rule EF.14
+2022-12-05 05:58:56 +0000: Memory Usage (1053504K) : Executing rule EF.15
+2022-12-05 05:58:56 +0000: Memory Usage (1053504K) : Executing rule EF.16a
+2022-12-05 05:58:56 +0000: Memory Usage (1053504K) : Executing rule EF.16b
+2022-12-05 05:58:56 +0000: Memory Usage (1053504K) : Executing rule EF.17
+2022-12-05 05:58:56 +0000: Memory Usage (1053504K) : Executing rule EF.18
+2022-12-05 05:58:58 +0000: Memory Usage (1134184K) : Executing rule EF.19
+2022-12-05 05:58:59 +0000: Memory Usage (1134184K) : Executing rule EF.20
+2022-12-05 05:58:59 +0000: Memory Usage (1134184K) : Executing rule EF.21
+2022-12-05 05:59:00 +0000: Memory Usage (1134184K) : Executing rule EF.22a
+2022-12-05 05:59:00 +0000: Memory Usage (1134184K) : Executing rule EF.22b
+2022-12-05 05:59:00 +0000: Memory Usage (1134184K) : Executing rule MDN.1
+2022-12-05 05:59:00 +0000: Memory Usage (1134184K) : CONNECTIVITY_RULES section
+2022-12-05 05:59:00 +0000: Memory Usage (1134184K) : Executing rule MDN.2a
+2022-12-05 05:59:00 +0000: Memory Usage (1134184K) : Executing rule MDN.2b
+2022-12-05 05:59:01 +0000: Memory Usage (1134184K) : Executing rule MDN.3a
+2022-12-05 05:59:01 +0000: Memory Usage (1134184K) : Executing rule MDN.3b
+2022-12-05 05:59:01 +0000: Memory Usage (1134184K) : Executing rule MDN.4a
+2022-12-05 05:59:01 +0000: Memory Usage (1134184K) : Executing rule MDN.4b
+2022-12-05 05:59:01 +0000: Memory Usage (1134184K) : Executing rule MDN.5ai
+2022-12-05 05:59:01 +0000: Memory Usage (1134184K) : Executing rule MDN.5aii
+2022-12-05 05:59:01 +0000: Memory Usage (1134184K) : Executing rule MDN.5b
+2022-12-05 05:59:01 +0000: Memory Usage (1134184K) : Executing rule MDN.5c
+2022-12-05 05:59:01 +0000: Memory Usage (1134184K) : Executing rule MDN.6
+2022-12-05 05:59:02 +0000: Memory Usage (1134184K) : Executing rule MDN.6a
+2022-12-05 05:59:02 +0000: Memory Usage (1134184K) : Executing rule MDN.7
+2022-12-05 05:59:02 +0000: Memory Usage (1134184K) : Executing rule MDN.7a
+2022-12-05 05:59:02 +0000: Memory Usage (1134184K) : CONNECTIVITY_RULES section
+2022-12-05 05:59:02 +0000: Memory Usage (1134184K) : Executing rule MDN.8a
+2022-12-05 05:59:02 +0000: Memory Usage (1134184K) : Executing rule MDN.8b
+2022-12-05 05:59:02 +0000: Memory Usage (1134184K) : Executing rule MDN.9
+2022-12-05 05:59:03 +0000: Memory Usage (1147040K) : Executing rule MDN.10a
+2022-12-05 05:59:03 +0000: Memory Usage (1147040K) : Executing rule MDN.10b
+2022-12-05 05:59:04 +0000: Memory Usage (1147040K) : Executing rule MDN.10c
+2022-12-05 05:59:05 +0000: Memory Usage (1174040K) : Executing rule MDN.10d
+2022-12-05 05:59:06 +0000: Memory Usage (1174040K) : Executing rule MDN.10ei
+2022-12-05 05:59:06 +0000: Memory Usage (1174764K) : Executing rule MDN.10eii
+2022-12-05 05:59:07 +0000: Memory Usage (1180656K) : Executing rule MDN.10f
+2022-12-05 05:59:07 +0000: Memory Usage (1228672K) : Executing rule MDN.11
+2022-12-05 05:59:08 +0000: Memory Usage (1235580K) : Executing rule MDN.12
+2022-12-05 05:59:08 +0000: Memory Usage (1235580K) : Executing rule MDN.13a
+2022-12-05 05:59:09 +0000: Memory Usage (1237480K) : Executing rule MDN.13b
+2022-12-05 05:59:09 +0000: Memory Usage (1237480K) : Executing rule MDN.13c
+2022-12-05 05:59:11 +0000: Memory Usage (1274636K) : Executing rule MDN.13d
+2022-12-05 05:59:11 +0000: Memory Usage (1274636K) : Executing rule MDN.14
+2022-12-05 05:59:11 +0000: Memory Usage (1274636K) : Executing rule MDN.15a
+2022-12-05 05:59:11 +0000: Memory Usage (1274636K) : Executing rule MDN.15b
+2022-12-05 05:59:12 +0000: Memory Usage (1274636K) : Executing rule MDN.17
+2022-12-05 05:59:12 +0000: Memory Usage (1286004K) : Executing rule MDP.1
+2022-12-05 05:59:13 +0000: Memory Usage (1312796K) : Executing rule MDP.1a
+2022-12-05 06:00:46 +0000: Memory Usage (1905196K) : Executing rule MDP.2
+2022-12-05 06:00:47 +0000: Memory Usage (1923324K) : Executing rule MDP.3
+2022-12-05 06:00:47 +0000: Memory Usage (1923324K) : Executing rule MDP.3ai
+2022-12-05 06:00:48 +0000: Memory Usage (1923324K) : Executing rule MDP.3aii
+2022-12-05 06:00:48 +0000: Memory Usage (1923324K) : Executing rule MDP.3b
+2022-12-05 06:00:48 +0000: Memory Usage (1923324K) : Executing rule MDP.3c
+2022-12-05 06:00:48 +0000: Memory Usage (1923324K) : Executing rule MDP.3d
+2022-12-05 06:00:48 +0000: Memory Usage (1923324K) : Executing rule MDP.4
+2022-12-05 06:00:54 +0000: Memory Usage (1940656K) : Executing rule MDP.4a
+2022-12-05 06:00:54 +0000: Memory Usage (1940656K) : Executing rule MDP.4b
+2022-12-05 06:00:54 +0000: Memory Usage (1940656K) : Executing rule MDP.5
+2022-12-05 06:00:55 +0000: Memory Usage (1942692K) : Executing rule MDP.5a
+2022-12-05 06:00:55 +0000: Memory Usage (1942692K) : Executing rule MDP.6
+2022-12-05 06:00:55 +0000: Memory Usage (1942692K) : Executing rule MDP.6a
+2022-12-05 06:00:55 +0000: Memory Usage (1942692K) : Executing rule MDP.7
+2022-12-05 06:00:55 +0000: Memory Usage (1942692K) : Executing rule MDP.8
+2022-12-05 06:00:55 +0000: Memory Usage (1942692K) : Executing rule MDP.9a
+2022-12-05 06:00:55 +0000: Memory Usage (1942692K) : Executing rule MDP.9b
+2022-12-05 06:00:55 +0000: Memory Usage (1942692K) : Executing rule MDP.9c
+2022-12-05 06:00:56 +0000: Memory Usage (1981528K) : Executing rule MDP.9d
+2022-12-05 06:00:59 +0000: Memory Usage (2042932K) : Executing rule MDP.9ei
+2022-12-05 06:01:00 +0000: Memory Usage (2067280K) : Executing rule MDP.9eii
+2022-12-05 06:01:00 +0000: Memory Usage (2067280K) : Executing rule MDP.9f
+2022-12-05 06:01:01 +0000: Memory Usage (2083600K) : Executing rule MDP.10
+2022-12-05 06:01:01 +0000: Memory Usage (2083600K) : CONNECTIVITY_RULES section
+2022-12-05 06:01:01 +0000: Memory Usage (2083600K) : Executing rule MDP.10a
+2022-12-05 06:01:01 +0000: Memory Usage (2083600K) : Executing rule MDP.10b
+2022-12-05 06:01:01 +0000: Memory Usage (2083600K) : Executing rule MDP.11
+2022-12-05 06:01:02 +0000: Memory Usage (2083600K) : Executing rule MDP.12
+2022-12-05 06:01:02 +0000: Memory Usage (2103464K) : Executing rule MDP.13a
+2022-12-05 06:01:03 +0000: Memory Usage (2119804K) : Executing rule MDP.13b
+2022-12-05 06:01:03 +0000: Memory Usage (2119804K) : Executing rule MDP.13c
+2022-12-05 06:01:04 +0000: Memory Usage (2144188K) : Executing rule MDP.15
+2022-12-05 06:01:04 +0000: Memory Usage (2144188K) : Executing rule MDP.16a
+2022-12-05 06:01:04 +0000: Memory Usage (2144188K) : Executing rule MDP.16b
+2022-12-05 06:01:04 +0000: Memory Usage (2144188K) : Executing rule MDP.17a
+2022-12-05 06:01:04 +0000: Memory Usage (2144188K) : Executing rule MDP.17c
+2022-12-05 06:01:04 +0000: Memory Usage (2144188K) : Executing rule Y.NW.2b_3.3V
+2022-12-05 06:01:04 +0000: Memory Usage (2144188K) : Executing rule Y.NW.2b_5V
+2022-12-05 06:01:04 +0000: Memory Usage (2144188K) : Executing rule Y.DF.6_5V
+2022-12-05 06:01:04 +0000: Memory Usage (2144188K) : Executing rule Y.DF.16_3.3V
+2022-12-05 06:01:05 +0000: Memory Usage (2144188K) : Executing rule Y.DF.16_5V
+2022-12-05 06:01:05 +0000: Memory Usage (2144188K) : Executing rule Y.PL.1_3.3V
+2022-12-05 06:01:05 +0000: Memory Usage (2144188K) : Executing rule Y.PL.1_5V
+2022-12-05 06:01:05 +0000: Memory Usage (2144188K) : Executing rule Y.PL.2_3.3V
+2022-12-05 06:01:07 +0000: Memory Usage (2158280K) : Executing rule Y.PL.2_5V
+2022-12-05 06:01:08 +0000: Memory Usage (2174692K) : Executing rule Y.PL.4_5V
+2022-12-05 06:01:08 +0000: Memory Usage (2174692K) : Executing rule Y.PL.5a_3.3V
+2022-12-05 06:01:08 +0000: Memory Usage (2174692K) : Executing rule Y.PL.5a_5V
+2022-12-05 06:01:08 +0000: Memory Usage (2174692K) : Executing rule Y.PL.5b_3.3V
+2022-12-05 06:01:08 +0000: Memory Usage (2174692K) : Executing rule Y.PL.5b_5V
+2022-12-05 06:01:08 +0000: Memory Usage (2174692K) : Executing rule S.DF.4c_MV
+2022-12-05 06:01:09 +0000: Memory Usage (2174692K) : Executing rule S.DF.6_MV
+2022-12-05 06:01:09 +0000: Memory Usage (2174692K) : Executing rule S.DF.7_MV
+2022-12-05 06:01:09 +0000: Memory Usage (2174692K) : Executing rule S.DF.8_MV
+2022-12-05 06:01:09 +0000: Memory Usage (2174692K) : Executing rule S.DF.16_MV
+2022-12-05 06:01:09 +0000: Memory Usage (2193356K) : Executing rule S.PL.5a_MV
+2022-12-05 06:01:09 +0000: Memory Usage (2193356K) : Executing rule S.PL.5b_MV
+2022-12-05 06:01:09 +0000: Memory Usage (2193356K) : Executing rule S.CO.4_MV
+2022-12-05 06:01:09 +0000: Memory Usage (2193356K) : Executing rule S.DF.4c_LV
+2022-12-05 06:01:10 +0000: Memory Usage (2193356K) : Executing rule S.DF.16_LV
+2022-12-05 06:01:10 +0000: Memory Usage (2210668K) : Executing rule S.CO.3_LV
+2022-12-05 06:01:10 +0000: Memory Usage (2210668K) : Executing rule S.CO.4_LV
+2022-12-05 06:01:10 +0000: Memory Usage (2210668K) : Executing rule S.CO.6_ii_LV
+2022-12-05 06:01:10 +0000: Memory Usage (2210668K) : Executing rule S.M1.1_LV
+2022-12-05 06:01:10 +0000: Memory Usage (2210668K) : OFFGRID-ANGLES section
+2022-12-05 06:01:10 +0000: Memory Usage (2210668K) : Executing rule comp_OFFGRID
+2022-12-05 06:01:10 +0000: Memory Usage (2210668K) : Executing rule dnwell_OFFGRID
+2022-12-05 06:01:10 +0000: Memory Usage (2210668K) : Executing rule nwell_OFFGRID
+2022-12-05 06:01:11 +0000: Memory Usage (2210668K) : Executing rule lvpwell_OFFGRID
+2022-12-05 06:01:11 +0000: Memory Usage (2210668K) : Executing rule dualgate_OFFGRID
+2022-12-05 06:01:11 +0000: Memory Usage (2210668K) : Executing rule poly2_OFFGRID
+2022-12-05 06:01:11 +0000: Memory Usage (2210668K) : Executing rule nplus_OFFGRID
+2022-12-05 06:01:11 +0000: Memory Usage (2210668K) : Executing rule pplus_OFFGRID
+2022-12-05 06:01:11 +0000: Memory Usage (2210668K) : Executing rule sab_OFFGRID
+2022-12-05 06:01:11 +0000: Memory Usage (2210668K) : Executing rule esd_OFFGRID
+2022-12-05 06:01:11 +0000: Memory Usage (2210668K) : Executing rule contact_OFFGRID
+2022-12-05 06:01:11 +0000: Memory Usage (2210668K) : Executing rule metal1_OFFGRID
+2022-12-05 06:01:11 +0000: Memory Usage (2210668K) : Executing rule via1_OFFGRID
+2022-12-05 06:01:11 +0000: Memory Usage (2210668K) : Executing rule metal2_OFFGRID
+2022-12-05 06:01:12 +0000: Memory Usage (2210668K) : Executing rule via2_OFFGRID
+2022-12-05 06:01:12 +0000: Memory Usage (2210668K) : Executing rule metal3_OFFGRID
+2022-12-05 06:01:12 +0000: Memory Usage (2210668K) : Executing rule via3_OFFGRID
+2022-12-05 06:01:12 +0000: Memory Usage (2210668K) : Executing rule metal4_OFFGRID
+2022-12-05 06:01:12 +0000: Memory Usage (2210668K) : Executing rule via4_OFFGRID
+2022-12-05 06:01:12 +0000: Memory Usage (2210668K) : Executing rule metal5_OFFGRID
+2022-12-05 06:01:12 +0000: Memory Usage (2210668K) : Executing rule via5_OFFGRID
+2022-12-05 06:01:12 +0000: Memory Usage (2210668K) : Executing rule metaltop_OFFGRID
+2022-12-05 06:01:12 +0000: Memory Usage (2210668K) : Executing rule pad_OFFGRID
+2022-12-05 06:01:12 +0000: Memory Usage (2210668K) : Executing rule resistor_OFFGRID
+2022-12-05 06:01:12 +0000: Memory Usage (2210668K) : Executing rule fhres_OFFGRID
+2022-12-05 06:01:12 +0000: Memory Usage (2210668K) : Executing rule fusetop_OFFGRID
+2022-12-05 06:01:12 +0000: Memory Usage (2210668K) : Executing rule fusewindow_d_OFFGRID
+2022-12-05 06:01:12 +0000: Memory Usage (2210668K) : Executing rule polyfuse_OFFGRID
+2022-12-05 06:01:13 +0000: Memory Usage (2210668K) : Executing rule mvsd_OFFGRID
+2022-12-05 06:01:13 +0000: Memory Usage (2210668K) : Executing rule mvpsd_OFFGRID
+2022-12-05 06:01:13 +0000: Memory Usage (2210668K) : Executing rule nat_OFFGRID
+2022-12-05 06:01:13 +0000: Memory Usage (2210668K) : Executing rule comp_dummy_OFFGRID
+2022-12-05 06:01:13 +0000: Memory Usage (2210668K) : Executing rule poly2_dummy_OFFGRID
+2022-12-05 06:01:13 +0000: Memory Usage (2210668K) : Executing rule metal1_dummy_OFFGRID
+2022-12-05 06:01:13 +0000: Memory Usage (2210668K) : Executing rule metal2_dummy_OFFGRID
+2022-12-05 06:01:13 +0000: Memory Usage (2210668K) : Executing rule metal3_dummy_OFFGRID
+2022-12-05 06:01:13 +0000: Memory Usage (2210668K) : Executing rule metal4_dummy_OFFGRID
+2022-12-05 06:01:13 +0000: Memory Usage (2210668K) : Executing rule metal5_dummy_OFFGRID
+2022-12-05 06:01:13 +0000: Memory Usage (2210668K) : Executing rule metaltop_dummy_OFFGRID
+2022-12-05 06:01:13 +0000: Memory Usage (2210668K) : Executing rule comp_label_OFFGRID
+2022-12-05 06:01:13 +0000: Memory Usage (2210668K) : Executing rule poly2_label_OFFGRID
+2022-12-05 06:01:13 +0000: Memory Usage (2210668K) : Executing rule metal1_label_OFFGRID
+2022-12-05 06:01:14 +0000: Memory Usage (2210668K) : Executing rule metal2_label_OFFGRID
+2022-12-05 06:01:14 +0000: Memory Usage (2210668K) : Executing rule metal3_label_OFFGRID
+2022-12-05 06:01:14 +0000: Memory Usage (2210668K) : Executing rule metal4_label_OFFGRID
+2022-12-05 06:01:14 +0000: Memory Usage (2210668K) : Executing rule metal5_label_OFFGRID
+2022-12-05 06:01:14 +0000: Memory Usage (2210668K) : Executing rule metaltop_label_OFFGRID
+2022-12-05 06:01:14 +0000: Memory Usage (2210668K) : Executing rule metal1_slot_OFFGRID
+2022-12-05 06:01:14 +0000: Memory Usage (2210668K) : Executing rule metal2_slot_OFFGRID
+2022-12-05 06:01:14 +0000: Memory Usage (2210668K) : Executing rule metal3_slot_OFFGRID
+2022-12-05 06:01:14 +0000: Memory Usage (2210668K) : Executing rule metal4_slot_OFFGRID
+2022-12-05 06:01:14 +0000: Memory Usage (2210668K) : Executing rule metal5_slot_OFFGRID
+2022-12-05 06:01:14 +0000: Memory Usage (2210668K) : Executing rule metaltop_slot_OFFGRID
+2022-12-05 06:01:14 +0000: Memory Usage (2210668K) : Executing rule ubmpperi_OFFGRID
+2022-12-05 06:01:14 +0000: Memory Usage (2210668K) : Executing rule ubmparray_OFFGRID
+2022-12-05 06:01:14 +0000: Memory Usage (2210668K) : Executing rule ubmeplate_OFFGRID
+2022-12-05 06:01:15 +0000: Memory Usage (2210668K) : Executing rule schottky_diode_OFFGRID
+2022-12-05 06:01:15 +0000: Memory Usage (2210668K) : Executing rule zener_OFFGRID
+2022-12-05 06:01:15 +0000: Memory Usage (2210668K) : Executing rule res_mk_OFFGRID
+2022-12-05 06:01:15 +0000: Memory Usage (2210668K) : Executing rule opc_drc_OFFGRID
+2022-12-05 06:01:15 +0000: Memory Usage (2210668K) : Executing rule ndmy_OFFGRID
+2022-12-05 06:01:15 +0000: Memory Usage (2210668K) : Executing rule pmndmy_OFFGRID
+2022-12-05 06:01:15 +0000: Memory Usage (2210668K) : Executing rule v5_xtor_OFFGRID
+2022-12-05 06:01:15 +0000: Memory Usage (2210668K) : Executing rule cap_mk_OFFGRID
+2022-12-05 06:01:15 +0000: Memory Usage (2210668K) : Executing rule mos_cap_mk_OFFGRID
+2022-12-05 06:01:15 +0000: Memory Usage (2210668K) : Executing rule ind_mk_OFFGRID
+2022-12-05 06:01:15 +0000: Memory Usage (2210668K) : Executing rule diode_mk_OFFGRID
+2022-12-05 06:01:15 +0000: Memory Usage (2210668K) : Executing rule drc_bjt_OFFGRID
+2022-12-05 06:01:15 +0000: Memory Usage (2210668K) : Executing rule lvs_bjt_OFFGRID
+2022-12-05 06:01:15 +0000: Memory Usage (2210668K) : Executing rule mim_l_mk_OFFGRID
+2022-12-05 06:01:16 +0000: Memory Usage (2210668K) : Executing rule latchup_mk_OFFGRID
+2022-12-05 06:01:16 +0000: Memory Usage (2210668K) : Executing rule guard_ring_mk_OFFGRID
+2022-12-05 06:01:16 +0000: Memory Usage (2210668K) : Executing rule otp_mk_OFFGRID
+2022-12-05 06:01:16 +0000: Memory Usage (2210668K) : Executing rule mtpmark_OFFGRID
+2022-12-05 06:01:16 +0000: Memory Usage (2210668K) : Executing rule neo_ee_mk_OFFGRID
+2022-12-05 06:01:16 +0000: Memory Usage (2210668K) : Executing rule sramcore_OFFGRID
+2022-12-05 06:01:16 +0000: Memory Usage (2210668K) : Executing rule lvs_rf_OFFGRID
+2022-12-05 06:01:16 +0000: Memory Usage (2210668K) : Executing rule lvs_drain_OFFGRID
+2022-12-05 06:01:16 +0000: Memory Usage (2210668K) : Executing rule hvpolyrs_OFFGRID
+2022-12-05 06:01:16 +0000: Memory Usage (2210668K) : Executing rule lvs_io_OFFGRID
+2022-12-05 06:01:16 +0000: Memory Usage (2210668K) : Executing rule probe_mk_OFFGRID
+2022-12-05 06:01:16 +0000: Memory Usage (2210668K) : Executing rule esd_mk_OFFGRID
+2022-12-05 06:01:16 +0000: Memory Usage (2210668K) : Executing rule lvs_source_OFFGRID
+2022-12-05 06:01:16 +0000: Memory Usage (2210668K) : Executing rule well_diode_mk_OFFGRID
+2022-12-05 06:01:17 +0000: Memory Usage (2210668K) : Executing rule ldmos_xtor_OFFGRID
+2022-12-05 06:01:17 +0000: Memory Usage (2210668K) : Executing rule plfuse_OFFGRID
+2022-12-05 06:01:17 +0000: Memory Usage (2210668K) : Executing rule efuse_mk_OFFGRID
+2022-12-05 06:01:17 +0000: Memory Usage (2210668K) : Executing rule mcell_feol_mk_OFFGRID
+2022-12-05 06:01:17 +0000: Memory Usage (2210668K) : Executing rule ymtp_mk_OFFGRID
+2022-12-05 06:01:17 +0000: Memory Usage (2210668K) : Executing rule dev_wf_mk_OFFGRID
+2022-12-05 06:01:17 +0000: Memory Usage (2210668K) : Executing rule metal1_blk_OFFGRID
+2022-12-05 06:01:17 +0000: Memory Usage (2210668K) : Executing rule metal2_blk_OFFGRID
+2022-12-05 06:01:17 +0000: Memory Usage (2210668K) : Executing rule metal3_blk_OFFGRID
+2022-12-05 06:01:17 +0000: Memory Usage (2210668K) : Executing rule metal4_blk_OFFGRID
+2022-12-05 06:01:17 +0000: Memory Usage (2210668K) : Executing rule metal5_blk_OFFGRID
+2022-12-05 06:01:17 +0000: Memory Usage (2210668K) : Executing rule metalt_blk_OFFGRID
+2022-12-05 06:01:17 +0000: Memory Usage (2210668K) : Executing rule pr_bndry_OFFGRID
+2022-12-05 06:01:17 +0000: Memory Usage (2210668K) : Executing rule mdiode_OFFGRID
+2022-12-05 06:01:17 +0000: Memory Usage (2210668K) : Executing rule metal1_res_OFFGRID
+2022-12-05 06:01:18 +0000: Memory Usage (2210668K) : Executing rule metal2_res_OFFGRID
+2022-12-05 06:01:18 +0000: Memory Usage (2210668K) : Executing rule metal3_res_OFFGRID
+2022-12-05 06:01:18 +0000: Memory Usage (2210668K) : Executing rule metal4_res_OFFGRID
+2022-12-05 06:01:18 +0000: Memory Usage (2210668K) : Executing rule metal5_res_OFFGRID
+2022-12-05 06:01:18 +0000: Memory Usage (2210668K) : Executing rule metal6_res_OFFGRID
+2022-12-05 06:01:18 +0000: Memory Usage (2210668K) : Executing rule border_OFFGRID
+VmPeak:	 2210664 kB
+VmHWM:	 1757640 kB
+2022-12-05 06:01:18 +0000: Memory Usage (2210668K) : DRC Total Run time 171.212589 seconds

diff --git a/mpw_precheck/logs/klayout_offgrid_check.total b/mpw_precheck/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.total

@@ -0,0 +1 @@
+0
\ No newline at end of file

diff --git a/mpw_precheck/logs/pdks.info b/mpw_precheck/logs/pdks.info
new file mode 100644
index 0000000..375c57b
--- /dev/null
+++ b/mpw_precheck/logs/pdks.info

@@ -0,0 +1,2 @@
+Open PDKs 120b0bd69c745825a0b8b76f364043a1cd08bb6a
+GF180MCUC PDK a897aa30369d3bcec87d9d50ce9b01f320f854ef
\ No newline at end of file

diff --git a/mpw_precheck/logs/precheck.log b/mpw_precheck/logs/precheck.log
new file mode 100644
index 0000000..06f6c49
--- /dev/null
+++ b/mpw_precheck/logs/precheck.log

@@ -0,0 +1,45 @@
+2022-12-05 05:46:54 - [INFO] - {{Project Git Info}} Repository: https://github.com/shaos/tiny_silicon_2.git | Branch: main | Commit: c356d427af79874f974a745d18ec667a83fbbdeb
+2022-12-05 05:46:54 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: testasynctrimux
+2022-12-05 05:46:54 - [INFO] - {{Project Type Info}} digital
+2022-12-05 05:46:54 - [INFO] - {{Project GDS Info}} user_project_wrapper: c6954de5738af2f4c9ef9f64fdbd49d9a0dcbdad
+2022-12-05 05:46:54 - [INFO] - {{Tools Info}} KLayout: v0.27.12 | Magic: v8.3.340
+2022-12-05 05:46:54 - [INFO] - {{PDKs Info}} GF180MCUC: a897aa30369d3bcec87d9d50ce9b01f320f854ef | Open PDKs: 120b0bd69c745825a0b8b76f364043a1cd08bb6a
+2022-12-05 05:46:54 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/logs'
+2022-12-05 05:46:54 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, GPIO-Defines, XOR, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density]
+2022-12-05 05:46:54 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 7: License
+2022-12-05 05:46:55 - [INFO] - An approved LICENSE (Apache-2.0) was found in testasynctrimux.
+2022-12-05 05:46:55 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-12-05 05:46:56 - [INFO] - An approved LICENSE (Apache-2.0) was found in testasynctrimux.
+2022-12-05 05:46:56 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-12-05 05:46:56 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 23 non-compliant file(s) with the SPDX Standard.
+2022-12-05 05:46:56 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['testasynctrimux/configure.py', 'testasynctrimux/openlane/tiny_user_project/config.json', 'testasynctrimux/sdc/tiny_user_project.sdc', 'testasynctrimux/sdc/user_module.sdc', 'testasynctrimux/sdc/user_project_wrapper.sdc', 'testasynctrimux/sdf/tiny_user_project.sdf', 'testasynctrimux/sdf/user_module.sdf', 'testasynctrimux/sdf/user_project_wrapper.sdf', 'testasynctrimux/sdf/multicorner/nom/user_project_wrapper.ff.sdf', 'testasynctrimux/sdf/multicorner/nom/user_project_wrapper.ss.sdf', 'testasynctrimux/sdf/multicorner/nom/user_project_wrapper.tt.sdf', 'testasynctrimux/spef/tiny_user_project.spef', 'testasynctrimux/spef/user_module.spef', 'testasynctrimux/spef/user_project_wrapper.spef', 'testasynctrimux/spef/multicorner/user_project_wrapper.nom.spef']
+2022-12-05 05:46:56 - [INFO] - For the full SPDX compliance report check: testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/logs/spdx_compliance_report.log
+2022-12-05 05:46:56 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 7: GPIO-Defines
+2022-12-05 05:46:56 - [INFO] - GPIO-DEFINES: Checking verilog/rtl/user_defines.v, parsing files: ['/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_base.v', 'testasynctrimux/verilog/rtl/user_defines.v', '/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_observe.v']
+2022-12-05 05:46:57 - [INFO] - GPIO-DEFINES report path: testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/outputs/reports/gpio_defines.report
+2022-12-05 05:46:57 - [INFO] - {{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid.
+2022-12-05 05:46:57 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 7: XOR
+2022-12-05 05:47:02 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/outputs/user_project_wrapper.xor.gds
+2022-12-05 05:47:02 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
+2022-12-05 05:47:02 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 7: Klayout FEOL
+2022-12-05 05:47:02 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-05 05:47:03 - [INFO] - run: klayout -b -r /opt/checks/tech-files/gf180mcuC_mr.drc -rd input=testasynctrimux/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/outputs/reports/klayout_feol_check.xml -rd feol=true -rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd conn_drc=true >& testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/logs/klayout_feol_check.log
+2022-12-05 05:54:51 - [INFO] - No DRC Violations found
+2022-12-05 05:54:51 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-05 05:54:51 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 7: Klayout BEOL
+2022-12-05 05:54:51 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-05 05:54:51 - [INFO] - run: klayout -b -r /opt/checks/tech-files/gf180mcuC_mr.drc -rd input=testasynctrimux/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/outputs/reports/klayout_beol_check.xml -rd beol=true -rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd conn_drc=true >& testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/logs/klayout_beol_check.log
+2022-12-05 05:58:26 - [INFO] - No DRC Violations found
+2022-12-05 05:58:26 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-05 05:58:26 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 7: Klayout Offgrid
+2022-12-05 05:58:26 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-05 05:58:26 - [INFO] - run: klayout -b -r /opt/checks/tech-files/gf180mcuC_mr.drc -rd input=testasynctrimux/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/outputs/reports/klayout_offgrid_check.xml -rd offgrid=true -rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd conn_drc=true >& testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/logs/klayout_offgrid_check.log
+2022-12-05 06:01:18 - [INFO] - No DRC Violations found
+2022-12-05 06:01:18 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-05 06:01:18 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 7: Klayout Metal Minimum Clear Area Density
+2022-12-05 06:01:18 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-05 06:01:18 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/gf180mcu_density.lydrc -rd input=testasynctrimux/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/outputs/reports/klayout_met_min_ca_density_check.xml >& testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/logs/klayout_met_min_ca_density_check.log
+2022-12-05 06:01:19 - [INFO] - No DRC Violations found
+2022-12-05 06:01:19 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-05 06:01:19 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/logs'
+2022-12-05 06:01:19 - [INFO] - {{SUCCESS}} All Checks Passed !!!

diff --git a/mpw_precheck/logs/spdx_compliance_report.log b/mpw_precheck/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..8293301
--- /dev/null
+++ b/mpw_precheck/logs/spdx_compliance_report.log

@@ -0,0 +1,23 @@
+/root/testasynctrimux/configure.py
+/root/testasynctrimux/openlane/tiny_user_project/config.json
+/root/testasynctrimux/sdc/tiny_user_project.sdc
+/root/testasynctrimux/sdc/user_module.sdc
+/root/testasynctrimux/sdc/user_project_wrapper.sdc
+/root/testasynctrimux/sdf/tiny_user_project.sdf
+/root/testasynctrimux/sdf/user_module.sdf
+/root/testasynctrimux/sdf/user_project_wrapper.sdf
+/root/testasynctrimux/sdf/multicorner/nom/user_project_wrapper.ff.sdf
+/root/testasynctrimux/sdf/multicorner/nom/user_project_wrapper.ss.sdf
+/root/testasynctrimux/sdf/multicorner/nom/user_project_wrapper.tt.sdf
+/root/testasynctrimux/spef/tiny_user_project.spef
+/root/testasynctrimux/spef/user_module.spef
+/root/testasynctrimux/spef/user_project_wrapper.spef
+/root/testasynctrimux/spef/multicorner/user_project_wrapper.nom.spef
+/root/testasynctrimux/verilog/includes/includes.gl+sdf.caravel_user_project
+/root/testasynctrimux/verilog/includes/includes.gl.caravel_user_project
+/root/testasynctrimux/verilog/includes/includes.rtl.caravel_user_project
+/root/testasynctrimux/verilog/rtl/cells.v
+/root/testasynctrimux/verilog/rtl/tiny_user_project.v
+/root/testasynctrimux/verilog/rtl/tiny_user_project.v.jinja2
+/root/testasynctrimux/verilog/rtl/user_module.v
+/root/testasynctrimux/verilog/rtl/wokwi_diagram.json

diff --git a/mpw_precheck/logs/tools.info b/mpw_precheck/logs/tools.info
new file mode 100644
index 0000000..4056146
--- /dev/null
+++ b/mpw_precheck/logs/tools.info

@@ -0,0 +1,2 @@
+KLayout: 0.27.12
+Magic: 8.3.340
\ No newline at end of file

diff --git a/mpw_precheck/logs/xor_check.log b/mpw_precheck/logs/xor_check.log
new file mode 100644
index 0000000..2519dca
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.log

@@ -0,0 +1,546 @@
+Reading file /root/testasynctrimux/gds/user_project_wrapper.gds for cell user_project_wrapper
+dbu=0.001
+cell user_project_wrapper dbu-bbox(ll;ur)=(-9580,-8220;2989900,2991340)
+cell user_project_wrapper dbu-bbox(left,bottom,right,top)=(-9580,-8220,2989900,2991340)
+cell user_project_wrapper dbu-size(width,height)=(2999480,2999560)
+cell user_project_wrapper micron-bbox(left,bottom,right,top)=(-9.58,-8.22,2989.9,2991.34)
+cell user_project_wrapper micron-size(width,height)=(2999.48,2999.56)
+Done.
+
+Magic 8.3 revision 340 - Compiled on Thu Nov 17 13:45:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology gf180mcuC ...
+10 Magic internal units = 1 Lambda
+Input style import: scaleFactor=10, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    obsactive mvobsactive filldiff fillpoly m1hole obsm1 fillm1 obsv1 m2hole obsm2 fillm2 obsv2 m3hole obsm3 fillm3 m4hole obsm4 fillm4 m5hole obsm5 fillm5 glass fillblock lvstext obscomment 
+Scaled tech values by 10 / 1 to match internal grid scaling
+Loading gf180mcuC Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box_gf180mcu.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+The current style is "import".
+The CIF input styles are: import.
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "gf180mcu_fd_sc_mcu7t5v0__antenna".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fill_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fill_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__endcap".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Reading "gf180mcu_fd_sc_mcu7t5v0__tiel".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__filltie".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dlyb_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyb_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyb_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyb_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyb_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_8".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_16".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_3".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_32".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_64".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dlyd_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyd_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyd_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyd_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyd_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dlyc_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyc_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyc_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyc_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyc_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi21_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor3_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor3_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__or3_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__or3_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or3_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or3_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or3_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai21_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1.
+Reading "tiny_user_project".
+    5000 uses
+    10000 uses
+Reading "user_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:   9.580 x 2980.200  (-9.580,  0.000), ( 0.000,  2980.200)  28550.314 
+lambda:   191.60 x 59604.00  (-191.60,  0.00 ), (  0.00,  59604.00)  11420127.00
+internal:   1916 x 596040  ( -1916,  0    ), (     0,  596040)  1142012640
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:   9.700 x 2980.200  ( 2980.200,  0.000), ( 2989.900,  2980.200)  28907.938 
+lambda:   194.00 x 59604.00  ( 59604.00,  0.00 ), ( 59798.00,  59604.00)  11563176.00
+internal:   1940 x 596040  ( 596040,  0    ), ( 597980,  596040)  1156317600
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  2999.480 x 8.220   (-9.580, -8.220), ( 2989.900,  0.000)  24655.725 
+lambda:   59989.60 x 164.40  (-191.60, -164.40), ( 59798.00,  0.00 )  9862291.00
+internal: 599896 x 1644    ( -1916, -1644 ), ( 597980,  0    )  986229024 
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  2999.480 x 11.140  (-9.580,  2980.200), ( 2989.900,  2991.340)  33414.207 
+lambda:   59989.60 x 222.80  (-191.60,  59604.00), ( 59798.00,  59826.80)  13365683.00
+internal: 599896 x 2228    ( -1916,  596040), ( 597980,  598268)  1336568288
+   Generating output for cell xor_target
+
+Magic 8.3 revision 340 - Compiled on Thu Nov 17 13:45:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology gf180mcuC ...
+10 Magic internal units = 1 Lambda
+Input style import: scaleFactor=10, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    obsactive mvobsactive filldiff fillpoly m1hole obsm1 fillm1 obsv1 m2hole obsm2 fillm2 obsv2 m3hole obsm3 fillm3 m4hole obsm4 fillm4 m5hole obsm5 fillm5 glass fillblock lvstext obscomment 
+Scaled tech values by 10 / 1 to match internal grid scaling
+Loading gf180mcuC Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box_gf180mcu.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+The current style is "import".
+The CIF input styles are: import.
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "gf180mcu_fd_sc_mcu7t5v0__tiel".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Reading "gf180mcu_fd_sc_mcu7t5v0__filltie".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Reading "gf180mcu_fd_sc_mcu7t5v0__endcap".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fill_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fill_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_32".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_16".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_8".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__antenna".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_64".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffq_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffq_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__mux2_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__mux2_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__mux2_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__mux2_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__mux2_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__inv_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand3_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand4_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Reading "gf180mcu_fd_sc_mcu7t5v0__xor2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__xor2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__xor2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__xor2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__xor2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi21_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__and3_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__and3_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and3_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and3_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and3_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__and4_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai21_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai31_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai31_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai31_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai31_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai31_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__xnor2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__xnor2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__xnor2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__xnor2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__xnor2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand4_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__and2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__and2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor4_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai211_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi22_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__or2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__or2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor3_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__and4_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__or3_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__or3_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or3_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or3_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or3_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi211_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi221_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi222_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi222_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi222_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi222_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi222_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor4_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__or4_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__or4_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or4_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or4_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or4_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor4_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_8".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.
+Reading "user_proj_example".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "user_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:   9.580 x 2980.200  (-9.580,  0.000), ( 0.000,  2980.200)  28550.314 
+lambda:   191.60 x 59604.00  (-191.60,  0.00 ), (  0.00,  59604.00)  11420127.00
+internal:   1916 x 596040  ( -1916,  0    ), (     0,  596040)  1142012640
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:   9.700 x 2980.200  ( 2980.200,  0.000), ( 2989.900,  2980.200)  28907.938 
+lambda:   194.00 x 59604.00  ( 59604.00,  0.00 ), ( 59798.00,  59604.00)  11563176.00
+internal:   1940 x 596040  ( 596040,  0    ), ( 597980,  596040)  1156317600
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  2999.480 x 8.220   (-9.580, -8.220), ( 2989.900,  0.000)  24655.725 
+lambda:   59989.60 x 164.40  (-191.60, -164.40), ( 59798.00,  0.00 )  9862291.00
+internal: 599896 x 1644    ( -1916, -1644 ), ( 597980,  0    )  986229024 
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  2999.480 x 11.140  (-9.580,  2980.200), ( 2989.900,  2991.340)  33414.207 
+lambda:   59989.60 x 222.80  (-191.60,  59604.00), ( 59798.00,  59826.80)  13365683.00
+internal: 599896 x 2228    ( -1916,  596040), ( 597980,  598268)  1336568288
+   Generating output for cell xor_target
+Reading /mnt/uffs/user/u9715_ashabar/design/testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/outputs/user_project_wrapper_erased.gds ..
+Reading /mnt/uffs/user/u9715_ashabar/design/testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/outputs/user_project_wrapper_empty_erased.gds ..
+--- Running XOR for 36/0 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 329 (flat)  329 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 329 (flat)  329 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+--- Running XOR for 41/0 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 128 (flat)  128 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 128 (flat)  128 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+--- Running XOR for 42/0 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 87 (flat)  87 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 87 (flat)  87 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+--- Running XOR for 46/0 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 4 (flat)  4 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 4 (flat)  4 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+--- Running XOR for 81/0 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 4 (flat)  4 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 4 (flat)  4 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+Writing layout file: /mnt/uffs/user/u9715_ashabar/design/testasynctrimux/jobs/mpw_precheck/42f0ac04-904e-4ff3-894f-86423249b67f/outputs/user_project_wrapper.xor.gds ..
+Total elapsed: 0.110s  Memory: 524.00M

diff --git a/mpw_precheck/logs/xor_check.total b/mpw_precheck/logs/xor_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.total

@@ -0,0 +1 @@
+0
\ No newline at end of file

diff --git a/mpw_precheck/outputs/reports/gpio_defines.report b/mpw_precheck/outputs/reports/gpio_defines.report
new file mode 100644
index 0000000..615b41c
--- /dev/null
+++ b/mpw_precheck/outputs/reports/gpio_defines.report

@@ -0,0 +1,33 @@
+USER_CONFIG_GPIO_5_INIT    10'h046
+USER_CONFIG_GPIO_6_INIT    10'h046
+USER_CONFIG_GPIO_7_INIT    10'h046
+USER_CONFIG_GPIO_8_INIT    10'h006
+USER_CONFIG_GPIO_9_INIT    10'h006
+USER_CONFIG_GPIO_10_INIT   10'h006
+USER_CONFIG_GPIO_11_INIT   10'h006
+USER_CONFIG_GPIO_12_INIT   10'h006
+USER_CONFIG_GPIO_13_INIT   10'h006
+USER_CONFIG_GPIO_14_INIT   10'h006
+USER_CONFIG_GPIO_15_INIT   10'h006
+USER_CONFIG_GPIO_16_INIT   10'h006
+USER_CONFIG_GPIO_17_INIT   10'h006
+USER_CONFIG_GPIO_18_INIT   10'h006
+USER_CONFIG_GPIO_19_INIT   10'h006
+USER_CONFIG_GPIO_20_INIT   10'h006
+USER_CONFIG_GPIO_21_INIT   10'h006
+USER_CONFIG_GPIO_22_INIT   10'h006
+USER_CONFIG_GPIO_23_INIT   10'h006
+USER_CONFIG_GPIO_24_INIT   10'h00a
+USER_CONFIG_GPIO_25_INIT   10'h00a
+USER_CONFIG_GPIO_26_INIT   10'h00a
+USER_CONFIG_GPIO_27_INIT   10'h00a
+USER_CONFIG_GPIO_28_INIT   10'h00a
+USER_CONFIG_GPIO_29_INIT   10'h00a
+USER_CONFIG_GPIO_30_INIT   10'h00a
+USER_CONFIG_GPIO_31_INIT   10'h00a
+USER_CONFIG_GPIO_32_INIT   10'h00a
+USER_CONFIG_GPIO_33_INIT   10'h00a
+USER_CONFIG_GPIO_34_INIT   10'h00a
+USER_CONFIG_GPIO_35_INIT   10'h00a
+USER_CONFIG_GPIO_36_INIT   10'h046
+USER_CONFIG_GPIO_37_INIT   10'h046

diff --git a/mpw_precheck/outputs/reports/klayout_beol_check.xml b/mpw_precheck/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..0368a13
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_beol_check.xml

@@ -0,0 +1,2949 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>DRC Run Report at</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/gf180mcuC_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>M1.1</name>
+   <description>M1.1 : min. metal1 width : 0.23µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M1.2a</name>
+   <description>M1.2a : min. metal1 spacing : 0.23µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M1.2b</name>
+   <description>M1.2b : Space to wide Metal1 (length &amp; width &gt; 10um) : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M1.3</name>
+   <description>M1.3 : Minimum Metal1 area : 0.1444µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M2.1</name>
+   <description>M2.1 : min. metal2 width : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M2.2a</name>
+   <description>M2.2a : min. metal2 spacing : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M2.2b</name>
+   <description>M2.2b : Space to wide Metal2 (length &amp; width &gt; 10um) : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M2.3</name>
+   <description>M2.3 : Minimum metal2 area : 0.1444µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M3.1</name>
+   <description>M3.1 : min. metal3 width : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M3.2a</name>
+   <description>M3.2a : min. metal3 spacing : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M3.2b</name>
+   <description>M3.2b : Space to wide Metal3 (length &amp; width &gt; 10um) : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M3.3</name>
+   <description>M3.3 : Minimum metal3 area : 0.1444µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M4.1</name>
+   <description>M4.1 : min. metal4 width : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M4.2a</name>
+   <description>M4.2a : min. metal4 spacing : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M4.2b</name>
+   <description>M4.2b : Space to wide Metal4 (length &amp; width &gt; 10um) : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M4.3</name>
+   <description>M4.3 : Minimum metal4 area : 0.1444µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M5.1</name>
+   <description>M5.1 : min. metal5 width : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M5.2a</name>
+   <description>M5.2a : min. metal5 spacing : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M5.2b</name>
+   <description>M5.2b : Space to wide Metal5 (length &amp; width &gt; 10um) : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>M5.3</name>
+   <description>M5.3 : Minimum metal5 area : 0.1444µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V1.1</name>
+   <description>V1.1 : Min/max Via1 size . : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V1.2a</name>
+   <description>V1.2a : min. via1 spacing : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V1.2b</name>
+   <description>V1.2b : Via1 Space in 4x4 or larger via1 array : 0.36µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V1.3a</name>
+   <description>V1.3a : metal-1  overlap of via1.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V1.3c</name>
+   <description>V1.3c : metal-1 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V1.3d</name>
+   <description>V1.3d : If metal-1 overlap via1 by &lt; 0.04um on one side, adjacent metal-1 edges overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V1.4a</name>
+   <description>V1.4a : metal-2 overlap of via1.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V1.4b</name>
+   <description>V1.4b : metal-2 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V1.4c</name>
+   <description>V1.4c : If metal-2 overlap via1 by &lt; 0.04um on one side, adjacent metal-2 edges overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V2.1</name>
+   <description>V2.1 : Min/max Via2 size . : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V2.2a</name>
+   <description>V2.2a : min. via2 spacing : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V2.2b</name>
+   <description>V2.2b : Via2 Space in 4x4 or larger via2 array : 0.36µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V2.3b</name>
+   <description>V2.3b : metal2  overlap of via2.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V2.3c</name>
+   <description>V2.3c : metal2 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V2.3d</name>
+   <description>V2.3d : If metal2 overlap via2 by &lt; 0.04um on one side, adjacent metal2 edges overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V2.4a</name>
+   <description>V2.4a : metal3 overlap of via2.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V2.4b</name>
+   <description>V2.4b : metal3 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V2.4c</name>
+   <description>V2.4c : If metal3 overlap via2 by &lt; 0.04um on one side, adjacent metal3 edges overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V3.1</name>
+   <description>V3.1 : Min/max Via3 size . : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V3.2a</name>
+   <description>V3.2a : min. via3 spacing : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V3.2b</name>
+   <description>V3.2b : Via3 Space in 4x4 or larger via3 array : 0.36µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V3.3b</name>
+   <description>V3.3b : metal3  overlap of via3.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V3.3c</name>
+   <description>V3.3c : metal3 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V3.3d</name>
+   <description>V3.3d : If metal3 overlap via3 by &lt; 0.04um on one side, adjacent metal3 edges overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V3.4a</name>
+   <description>V3.4a : metal4 overlap of via3.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V3.4b</name>
+   <description>V3.4b : metal4 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V3.4c</name>
+   <description>V3.4c : If metal4 overlap via3 by &lt; 0.04um on one side, adjacent metal4 edges overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V4.1</name>
+   <description>V4.1 : Min/max Via4 size . : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V4.2a</name>
+   <description>V4.2a : min. via4 spacing : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V4.2b</name>
+   <description>V4.2b : Via4 Space in 4x4 or larger Vian array : 0.36µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V4.3b</name>
+   <description>V4.3b : metal4  overlap of via4.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V4.3c</name>
+   <description>V4.3c : metal4 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V4.3d</name>
+   <description>V4.3d : If metal4 overlap Vian by &lt; 0.04um on one side, adjacent metal4 edges overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V4.4a</name>
+   <description>V4.4a : metal5 overlap of via4.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V4.4b</name>
+   <description>V4.4b : metal5 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V4.4c</name>
+   <description>V4.4c : If metal5 overlap via4 by &lt; 0.04um on one side, adjacent metal5 edges overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V5.1</name>
+   <description>V5.1 : Min/max Via5 size . : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V5.2a</name>
+   <description>V5.2a : min. via5 spacing : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V5.2b</name>
+   <description>V5.2b : Via5 Space in 4x4 or larger via5 array : 0.36µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V5.3b</name>
+   <description>V5.3b : metal5  overlap of via5.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V5.3c</name>
+   <description>V5.3c : metal5 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V5.3d</name>
+   <description>V5.3d : If metal5 overlap via5 by &lt; 0.04um on one side, adjacent metal5 edges overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V5.4a</name>
+   <description>V5.4a : metaltop overlap of via5.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V5.4b</name>
+   <description>V5.4b : metaltop (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>V5.4c</name>
+   <description>V5.4c : If metaltop overlap via5 by &lt; 0.04um on one side, adjacent metaltop edges overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MT.1</name>
+   <description>MT.1 : min. metaltop width : 0.44µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MT.2a</name>
+   <description>MT.2a : min. metaltop spacing : 0.46µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MT.2b</name>
+   <description>MT.2b : Space to wide Metal2 (length &amp; width &gt; 10um) : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MT.4</name>
+   <description>MT.4 : Minimum MetalTop area : 0.5625µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MC.1</name>
+   <description>MC.1 : min. mcell width : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MC.2</name>
+   <description>MC.2 : min. mcell spacing : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MC.3</name>
+   <description>MC.3 : Minimum Mcell area : 0.35µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MC.4</name>
+   <description>MC.4 : Minimum area enclosed by Mcell : 0.35µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.1</name>
+   <description>PRES.1 : Minimum width of Poly2 resistor. : 0.8µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.2</name>
+   <description>PRES.2 : Minimum space between Poly2 resistors. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.3</name>
+   <description>PRES.3 : Minimum space from Poly2 resistor to COMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.4</name>
+   <description>PRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.5</name>
+   <description>PRES.5 : Minimum Plus implant overlap of Poly2 resistor. : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.6</name>
+   <description>PRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction. : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.7</name>
+   <description>PRES.7 : Space from salicide block to contact on Poly2 resistor.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.9a</name>
+   <description>PRES.9a : Pplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.9b</name>
+   <description>PRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.1</name>
+   <description>LRES.1 : Minimum width of Poly2 resistor. : 0.8µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.2</name>
+   <description>LRES.2 : Minimum space between Poly2 resistors. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.3</name>
+   <description>LRES.3 : Minimum space from Poly2 resistor to COMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.4</name>
+   <description>LRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.5</name>
+   <description>LRES.5 : Minimum Nplus implant overlap of Poly2 resistor. : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.6</name>
+   <description>LRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction. : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.7</name>
+   <description>LRES.7 : Space from salicide block to contact on Poly2 resistor.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.9a</name>
+   <description>LRES.9a : Nplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2. </description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.9b</name>
+   <description>LRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.1</name>
+   <description>HRES.1 : Minimum space. Note : Merge if the spacing is less than 0.4 um. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.2</name>
+   <description>HRES.2 : Minimum width of Poly2 resistor. : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.3</name>
+   <description>HRES.3 : Minimum space between Poly2 resistors. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.4</name>
+   <description>HRES.4 : Minimum RESISTOR overlap of Poly2 resistor. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.5</name>
+   <description>HRES.5 : Minimum RESISTOR space to unrelated Poly2. : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.6</name>
+   <description>HRES.6 : Minimum RESISTOR space to COMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.7</name>
+   <description>HRES.7 : Minimum Pplus overlap of contact on Poly2 resistor. : 0.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.8</name>
+   <description>HRES.8 : Space from salicide block to contact on Poly2 resistor.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.9</name>
+   <description>HRES.9 : Minimum salicide block overlap of Poly2 resistor in width direction.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.10</name>
+   <description>HRES.10 : Minimum &amp; maximum Pplus overlap of SAB.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.12a</name>
+   <description>HRES.12a : P type Poly2 resistor (high sheet rho) shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by Pplus space) and width covering the width of Poly2. </description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.12b</name>
+   <description>HRES.12b : If the size of single RES_MK mark layer is greater than 15000 um2 and both side (X and Y) are greater than 80 um. Then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.1</name>
+   <description>MIMTM.1 : Minimum MiM bottom plate spacing to the bottom plate metal (whether adjacent MiM or routing metal). : 1.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.2</name>
+   <description>MIMTM.2 : Minimum MiM bottom plate overlap of Vian-1 layer. [This is applicable for Vian-1 within 1.06um oversize of FuseTop layer (referenced to virtual bottom plate)]. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.3</name>
+   <description>MIMTM.3 : Minimum MiM bottom plate overlap of Top plate.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.4</name>
+   <description>MIMTM.4 : Minimum MiM top plate (FuseTop) overlap of Vian-1. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.5</name>
+   <description>MIMTM.5 : Minimum spacing between top plate and the Vian-1 connecting to the bottom plate. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.6</name>
+   <description>MIMTM.6 : Minimum spacing between unrelated top plates. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.7</name>
+   <description>MIMTM.7 : Min FuseTop enclosure by CAP_MK.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.8a</name>
+   <description>MIMTM.8a : Minimum MIM cap area (defined by FuseTop area) (um2). : 25µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.8b</name>
+   <description>MIMTM.8b : Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required) (um2). : 10000µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.9</name>
+   <description>MIMTM.9 : Min. Via (Vian-1) spacing for sea of Via on MIM top plate. : 0.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.10</name>
+   <description>MIMTM.10 : (a) There cannot be any Vian-2 touching MIM bottom plate Metaln-1. (b) MIM bottom plate Metaln-1 can only be connected through the higher Via (Vian-1).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.11</name>
+   <description>MIMTM.11 : Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed MIMTM.8b rule. : -µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.1</name>
+   <description>NAT.1 : Min. NAT Overlap of COMP of Native Vt NMOS. : 2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.2</name>
+   <description>NAT.2 : Space to unrelated COMP (outside NAT). : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.3</name>
+   <description>NAT.3 : Space to NWell edge. : 0.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.4</name>
+   <description>NAT.4 : Minimum channel length for 3.3V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.5</name>
+   <description>NAT.5 : Minimum channel length for 6.0V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.6</name>
+   <description>NAT.6 : Two or more COMPs if connected to different potential are not allowed under same NAT layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.7</name>
+   <description>NAT.7 : Minimum NAT to NAT spacing. : 0.74µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.8</name>
+   <description>NAT.8 : Min. Dualgate overlap of NAT (for 5V/6V) native VT NMOS only.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.9</name>
+   <description>NAT.9 : Poly interconnect under NAT layer is not allowed, minimum spacing of un-related poly from the NAT layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.10</name>
+   <description>NAT.10 : Nwell, inside NAT layer are not allowed.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.11</name>
+   <description>NAT.11 : NCOMP not intersecting to Poly2, is not allowed inside NAT layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.12</name>
+   <description>NAT.12 : Poly2 not intersecting with COMP is not allowed inside NAT (Poly2 resistor is not allowed inside NAT).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>BJT.1</name>
+   <description>BJT.1 : Min. DRC_BJT overlap of DNWELL for NPN BJT.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>BJT.2</name>
+   <description>BJT.2 : Min. DRC_BJT overlap of PCOM in Psub.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>BJT.3</name>
+   <description>BJT.3 : Minimum space of DRC_BJT layer to unrelated COMP. : 0.1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DE.2</name>
+   <description>DE.2 : Minimum NDMY or PMNDMY size (x or y dimension in um). : 0.8µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DE.3</name>
+   <description>DE.3 : If size greater than 15000 um2 then two sides should not be greater than (um).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DE.4</name>
+   <description>DE.4 : Minimum NDMY to NDMY space (Merge if space is less). : 20µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LVS_BJT.1</name>
+   <description>LVS_BJT.1 : Minimum LVS_BJT enclosure of NPN or PNP Emitter COMP layers</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.DF.3a</name>
+   <description>O.DF.3a : Min. COMP Space. P-substrate tap (PCOMP outside NWELL) can be butted for different voltage devices as the potential is same. : 0.24µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.DF.6</name>
+   <description>O.DF.6 : Min. COMP extend beyond poly2 (it also means source/drain overhang). : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.DF.9</name>
+   <description>O.DF.9 : Min. COMP area (um2). : 0.1444µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.PL.2</name>
+   <description>O.PL.2 : Min. poly2 width. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.PL.3a</name>
+   <description>O.PL.3a : Min. poly2 Space on COMP. : 0.18µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.PL.4</name>
+   <description>O.PL.4 : Min. extension beyond COMP to form Poly2 end cap. : 0.14µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.2</name>
+   <description>O.SB.2 : Min. salicide Block Space. : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.3</name>
+   <description>O.SB.3 : Min. space from salicide block to unrelated COMP. : 0.09µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.4</name>
+   <description>O.SB.4 : Min. space from salicide block to contact.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.5b_3.3V</name>
+   <description>O.SB.5b_3.3V : Min. space from salicide block to unrelated Poly2 on COMP. : 0.1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.9</name>
+   <description>O.SB.9 : Min. salicide block extension beyond unsalicided Poly2. : 0.1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.11</name>
+   <description>O.SB.11 : Min. salicide block overlap with COMP. : 0.04µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.13_3.3V</name>
+   <description>O.SB.13_3.3V : Min. area of silicide block (um2). : 1.488µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.13_5V</name>
+   <description>O.SB.13_5V : Min. area of silicide block (um2). : 2µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.CO.7</name>
+   <description>O.CO.7 : Min. space from COMP contact to Poly2 on COMP. : 0.13µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.PL.ORT</name>
+   <description>O.PL.ORT : Orientation-restricted gates must have the gate width aligned along the X-axis (poly line running horizontally) in reference to wafer notch down. : 0µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.01</name>
+   <description>EF.01 : Min. (Poly2 butt PLFUSE) within EFUSE_MK and Pplus.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.02</name>
+   <description>EF.02 : Min. Max. PLFUSE width. : 0.18µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.03</name>
+   <description>EF.03 : Min. Max. PLFUSE length. : 1.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.04a</name>
+   <description>EF.04a : Min. Max. PLFUSE overlap Poly2 (coinciding permitted) and touch cathode and anode.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.04b</name>
+   <description>EF.04b : PLFUSE must be rectangular. : -µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.04c</name>
+   <description>EF.04c : Cathode Poly2 must be rectangular. : -µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.04d</name>
+   <description>EF.04d : Anode Poly2 must be rectangular. : -µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.05</name>
+   <description>EF.05 : Min./Max. LVS_Source overlap Poly2 (at Anode).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.06</name>
+   <description>EF.06 : Min./Max. Cathode Poly2 width. : 2.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.07</name>
+   <description>EF.07 : Min./Max. Cathode Poly2 length. : 1.84µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.08</name>
+   <description>EF.08 : Min./Max. Anode Poly2 width. : 1.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.09</name>
+   <description>EF.09 : Min./Max. Anode Poly2 length. : 2.43µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.10</name>
+   <description>EF.10 : Min. Cathode Poly2 to Poly2 space. : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.11</name>
+   <description>EF.11 : Min. Anode Poly2 to Poly2 space. : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.12</name>
+   <description>EF.12 : Min. Space of Cathode Contact to PLFUSE end.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.13</name>
+   <description>EF.13 : Min. Space of Anode Contact to PLFUSE end.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.14</name>
+   <description>EF.14 : Min. EFUSE_MK enclose LVS_Source.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.15</name>
+   <description>EF.15 : NO Contact is allowed to touch PLFUSE.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.16a</name>
+   <description>EF.16a : Cathode must contain exact number of Contacts at each ends. : 4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.16b</name>
+   <description>EF.16b : Anode must contain exact number of Contacts at each ends. : 4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.17</name>
+   <description>EF.17 : Min. Space of EFUSE_MK to EFUSE_MK. : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.18</name>
+   <description>EF.18 : PLFUSE must sit on field oxide (NOT COMP), no cross with any COMP, Nplus, Pplus, ESD, SAB, Resistor, Metal1, Metal2.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.19</name>
+   <description>EF.19 : Min. PLFUSE space to Metal1, Metal2.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.20</name>
+   <description>EF.20 : Min. PLFUSE space to COMP, Nplus, Pplus, Resistor, ESD, SAB. : 2.73µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.21</name>
+   <description>EF.21 : Min./Max. eFUSE Poly2 length. : 5.53µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.22a</name>
+   <description>EF.22a : Min./Max. Cathode Poly2 overlap with PLFUSE in width direction. : 1.04µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.22b</name>
+   <description>EF.22b : Min./Max. Anode Poly2 overlap with PLFUSE in width direction. : 0.44µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.1</name>
+   <description>MDN.1 : Min MVSD width (for litho purpose). : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.2a</name>
+   <description>MDN.2a : Min MVSD space [Same Potential]. : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.2b</name>
+   <description>MDN.2b : Min MVSD space [Diff Potential]. : 2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.3a</name>
+   <description>MDN.3a : Min transistor channel length. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.3b</name>
+   <description>MDN.3b : Max transistor channel length: 20 um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.4a</name>
+   <description>MDN.4a : Min transistor channel width. : 4 µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.4b</name>
+   <description>MDN.4b : Max transistor channel width. : 50 um </description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.5ai</name>
+   <description>MDN.5ai : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap non-butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.5aii</name>
+   <description>MDN.5aii : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed. : 0.92µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.5b</name>
+   <description>MDN.5b : Min PCOMP (Pplus AND COMP) space to LDNMOS Source (Nplus AND COMP). Use butted source and p-substrate tab otherwise and that is good for Latch-up immunity as well.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.5c</name>
+   <description>MDN.5c : Maximum distance of the nearest edge of the substrate tab from NCOMP edge. : 15µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.6</name>
+   <description>MDN.6 : ALL LDNMOS shall be covered by Dualgate layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.6a</name>
+   <description>MDN.6a : Min Dualgate enclose NCOMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.7</name>
+   <description>MDN.7 : Each LDNMOS shall be covered by LDMOS_XTOR (GDS#226) mark layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.7a</name>
+   <description>MDN.7a : Min LDMOS_XTOR enclose Dualgate.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.8a</name>
+   <description>MDN.8a : Min LDNMOS drain MVSD space to any other equal potential Nwell space.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.8b</name>
+   <description>MDN.8b : Min LDNMOS drain MVSD space to any other different potential Nwell space.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.9</name>
+   <description>MDN.9 : Min LDNMOS drain MVSD space to NCOMP (Nplus AND COMP) outside LDNMOS drain MVSD. : 4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10a</name>
+   <description>MDN.10a : Min LDNMOS POLY2 width. : 1.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10b</name>
+   <description>MDN.10b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDNMOS drain direction). : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10c</name>
+   <description>MDN.10c : Min/Max POLY2 extension beyond COMP on the field towards LDNMOS drain COMP direction.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10d</name>
+   <description>MDN.10d : Min/Max POLY2 on field space to LDNMOS drain COMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10ei</name>
+   <description>MDN.10ei : Min POLY2 space to Psub tap (source and body tap non-butted).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10eii</name>
+   <description>MDN.10eii : Min POLY2 space to Psub tap (source and body tap butted). : 0.32µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10f</name>
+   <description>MDN.10f : Poly2 interconnect in HV region (LDMOS_XTOR marked region) not allowed. Also, any Poly2 interconnect with poly2 to substrate potential greater than 6V is not allowed.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.11</name>
+   <description>MDN.11 : Min/Max MVSD overlap channel COMP ((((LDMOS_XTOR AND MVSD) AND COMP) AND POLY2) AND NPlus).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.12</name>
+   <description>MDN.12 : Min MVSD enclose NCOMP in the LDNMOS drain and in the direction along the transistor width.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.13a</name>
+   <description>MDN.13a : Max single finger width. : 50µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.13b</name>
+   <description>MDN.13b : Layout shall have alternative source &amp; drain.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.13c</name>
+   <description>MDN.13c : Both sides of the transistor shall be terminated by source.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.13d</name>
+   <description>MDN.13d : Every two poly fingers shall be surrounded by a P-sub guard ring. (Exclude the case when each LDNMOS transistor have full width butting to well tap).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.14</name>
+   <description>MDN.14 : Min MVSD space to any DNWELL.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.15a</name>
+   <description>MDN.15a : Min LDNMOS drain COMP width. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.15b</name>
+   <description>MDN.15b : Min LDNMOS drain COMP enclose contact. : 0µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.17</name>
+   <description>MDN.17 : It is recommended to surround the LDNMOS transistor with non-broken Psub guard ring to improve the latch up immunity. Guideline to improve the latch up immunity.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.1</name>
+   <description>MDP.1 : Minimum transistor channel length. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.1a</name>
+   <description>MDP.1a : Max transistor channel length.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.2</name>
+   <description>MDP.2 : Minimum transistor channel width. : 4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.3</name>
+   <description>MDP.3 : Each LDPMOS shall be surrounded by non-broken Nplus guard ring inside DNWELL</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.3ai</name>
+   <description>MDP.3ai : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap non-butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.3aii</name>
+   <description>MDP.3aii : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.3b</name>
+   <description>MDP.3b : Min NCOMP (Nplus AND COMP) space to PCOMP in DNWELL (Pplus AND COMP AND DNWELL). Use butted source and DNWELL contacts otherwise and that is best for Latch-up immunity as well. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.3c</name>
+   <description>MDP.3c : Maximum distance of the nearest edge of the DNWELL tab (NCOMP inside DNWELL) from PCOMP edge (PCOMP inside DNWELL). : 15µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.3d</name>
+   <description>MDP.3d : The metal connection for the Nplus guard ring recommended to be continuous. The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability. : 10µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.4</name>
+   <description>MDP.4 : DNWELL covering LDPMOS shall be surrounded by non broken Pplus guard. The metal connection for the Pplus guard ring recommended to be continuous, The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.4a</name>
+   <description>MDP.4a : Min PCOMP (Pplus AND COMP) space to DNWELL. : 2.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.4b</name>
+   <description>MDP.4b : Maximum distance of the nearest edge of the DNWELL from the PCOMP Guard ring outside DNWELL. : 15µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.5</name>
+   <description>MDP.5 : Each LDPMOS shall be covered by Dualgate layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.5a</name>
+   <description>MDP.5a : Minimum Dualgate enclose Plus guarding ring PCOMP (Pplus AND COMP). : 0.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.6</name>
+   <description>MDP.6 : Each LDPMOS shall be covered by LDMOS_XTOR (GDS#226) layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.6a</name>
+   <description>MDP.6a : Minimum LDMOS_XTOR enclose Dualgate.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.7</name>
+   <description>MDP.7 : Minimum LDMOS_XTOR layer space to Nwell outside LDMOS_XTOR. : 2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.8</name>
+   <description>MDP.8 : Minimum LDMOS_XTOR layer space to NCOMP outside LDMOS_XTOR. : 1.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9a</name>
+   <description>MDP.9a : Min LDPMOS POLY2 width. : 1.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9b</name>
+   <description>MDP.9b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDMOS drain direction). : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9c</name>
+   <description>MDP.9c : Min/Max POLY2 extension beyond COMP on the field towards LDPMOS drain (MVPSD AND COMP AND Pplus NOT POLY2) direction.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9d</name>
+   <description>MDP.9d : Min/Max POLY2 on field to LDPMOS drain COMP (MVPSD AND COMP AND Pplus NOT POLY2) space.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9ei</name>
+   <description>MDP.9ei : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap non-butted).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9eii</name>
+   <description>MDP.9eii : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap butted).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9f</name>
+   <description>MDP.9f : Poly2 interconnect is not allowed in LDPMOS region (LDMOS_XTOR marked region). : -µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.10</name>
+   <description>MDP.10 : Min/Max MVPSD overlap onto the channel (LDMOS_XTOR AND COMP AND POLY2 AND Pplus).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.10a</name>
+   <description>MDP.10a : Min MVPSD space within LDMOS_XTOR marking [diff potential]. : 2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.10b</name>
+   <description>MDP.10b : Min MVPSD space [same potential]. Merge if space less than 1um. : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.11</name>
+   <description>MDP.11 : Min MVPSD enclosing PCOMP in the drain (MVPSD AND COMP NOT POLY2) direction and in the direction along the transistor width.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.12</name>
+   <description>MDP.12 : Min DNWELL enclose Nplus guard ring (NCOMP). : 0.66µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.13a</name>
+   <description>MDP.13a : Max single finger width. : 50µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.13b</name>
+   <description>MDP.13b : Layout shall have alternative source &amp; drain.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.13c</name>
+   <description>MDP.13c : Both sides of the transistor shall be terminated by source.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.15</name>
+   <description>MDP.15 : Min DNWELL enclosing MVPSD to any DNWELL spacing. : 6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.16a</name>
+   <description>MDP.16a : Min LDPMOS drain COMP width. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.16b</name>
+   <description>MDP.16b : Min LDPMOS drain COMP enclose contact. : 0µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.17a</name>
+   <description>MDP.17a : For better latch up immunity, it is necessary to put DNWELL guard ring between MVPSD Inside DNWELL covered by LDMOS_XTOR and NCOMP (outside DNWELL and outside Nwell) when spacing between them is less than 40um.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.17c</name>
+   <description>MDP.17c : DNWELL guard ring shall have NCOMP tab to be connected to highest potential</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.NW.2b_3.3V</name>
+   <description>Y.NW.2b_3.3V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.NW.2b_5V</name>
+   <description>Y.NW.2b_5V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.DF.6_5V</name>
+   <description>Y.DF.6_5V : Min. COMP extend beyond gate (it also means source/drain overhang) inside YMTP_MK. : 0.15µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.DF.16_3.3V</name>
+   <description>Y.DF.16_3.3V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.27µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.DF.16_5V</name>
+   <description>Y.DF.16_5V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.23µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.1_3.3V</name>
+   <description>Y.PL.1_3.3V : Interconnect Width (inside YMTP_MK). : 0.13µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.1_5V</name>
+   <description>Y.PL.1_5V : Interconnect Width (inside YMTP_MK). This rule is currently not applicable for 5V.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.2_3.3V</name>
+   <description>Y.PL.2_3.3V : Gate Width (Channel Length) (inside YMTP_MK). : 0.13µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.2_5V</name>
+   <description>Y.PL.2_5V : Gate Width (Channel Length) (inside YMTP_MK). : 0.47µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.4_5V</name>
+   <description>Y.PL.4_5V : Poly2 extension beyond COMP to form Poly2 end cap (inside YMTP_MK). : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.5a_3.3V</name>
+   <description>Y.PL.5a_3.3V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.04µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.5a_5V</name>
+   <description>Y.PL.5a_5V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.5b_3.3V</name>
+   <description>Y.PL.5b_3.3V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.04µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.5b_5V</name>
+   <description>Y.PL.5b_5V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.4c_MV</name>
+   <description>S.DF.4c_MV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.45µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.6_MV</name>
+   <description>S.DF.6_MV : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.32µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.7_MV</name>
+   <description>S.DF.7_MV : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.45µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.8_MV</name>
+   <description>S.DF.8_MV : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.45µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.16_MV</name>
+   <description>S.DF.16_MV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.45µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.PL.5a_MV</name>
+   <description>S.PL.5a_MV : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.12µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.PL.5b_MV</name>
+   <description>S.PL.5b_MV : Space from field Poly2 to related COMP. : 0.12µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.CO.4_MV</name>
+   <description>S.CO.4_MV : COMP overlap of contact. : 0.04µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.4c_LV</name>
+   <description>S.DF.4c_LV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.16_LV</name>
+   <description>S.DF.16_LV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.CO.3_LV</name>
+   <description>S.CO.3_LV : Poly2 overlap of contact. : 0.04µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.CO.4_LV</name>
+   <description>S.CO.4_LV : COMP overlap of contact. : 0.03µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.CO.6_ii_LV</name>
+   <description>S.CO.6_ii_LV : (ii) If Metal1 overlaps contact by &lt; 0.04um on one side, adjacent metal1 edges overlap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.M1.1_LV</name>
+   <description>S.M1.1_LV : min. metal1 width : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>comp_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on comp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>comp_angle</name>
+   <description>ACUTE : non 45 degree angle comp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_angle</name>
+   <description>ACUTE : non 45 degree angle dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_angle</name>
+   <description>ACUTE : non 45 degree angle nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvpwell_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on lvpwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvpwell_angle</name>
+   <description>ACUTE : non 45 degree angle lvpwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dualgate_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on dualgate</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dualgate_angle</name>
+   <description>ACUTE : non 45 degree angle dualgate</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly2_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on poly2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly2_angle</name>
+   <description>ACUTE : non 45 degree angle poly2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nplus_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on nplus</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nplus_angle</name>
+   <description>ACUTE : non 45 degree angle nplus</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pplus_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on pplus</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pplus_angle</name>
+   <description>ACUTE : non 45 degree angle pplus</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>sab_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on sab</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>sab_angle</name>
+   <description>ACUTE : non 45 degree angle sab</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>esd_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on esd</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>esd_angle</name>
+   <description>ACUTE : non 45 degree angle esd</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>contact_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on contact</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>contact_angle</name>
+   <description>ACUTE : non 45 degree angle contact</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_angle</name>
+   <description>ACUTE : non 45 degree angle metal1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via1_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on via1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via1_angle</name>
+   <description>ACUTE : non 45 degree angle via1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_angle</name>
+   <description>ACUTE : non 45 degree angle metal2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_angle</name>
+   <description>ACUTE : non 45 degree angle via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_angle</name>
+   <description>ACUTE : non 45 degree angle metal3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_angle</name>
+   <description>ACUTE : non 45 degree angle via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_angle</name>
+   <description>ACUTE : non 45 degree angle metal4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_angle</name>
+   <description>ACUTE : non 45 degree angle via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_angle</name>
+   <description>ACUTE : non 45 degree angle metal5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via5_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on via5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via5_angle</name>
+   <description>ACUTE : non 45 degree angle via5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metaltop</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_angle</name>
+   <description>ACUTE : non 45 degree angle metaltop</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_angle</name>
+   <description>ACUTE : non 45 degree angle pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>resistor_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on resistor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>resistor_angle</name>
+   <description>ACUTE : non 45 degree angle resistor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>fhres_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on fhres</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>fhres_angle</name>
+   <description>ACUTE : non 45 degree angle fhres</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>fusetop_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on fusetop</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>fusetop_angle</name>
+   <description>ACUTE : non 45 degree angle fusetop</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>fusewindow_d_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on fusewindow_d</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>fusewindow_d_angle</name>
+   <description>ACUTE : non 45 degree angle fusewindow_d</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>polyfuse_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on polyfuse</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>polyfuse_angle</name>
+   <description>ACUTE : non 45 degree angle polyfuse</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mvsd_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mvsd</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mvsd_angle</name>
+   <description>ACUTE : non 45 degree angle mvsd</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mvpsd_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mvpsd</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mvpsd_angle</name>
+   <description>ACUTE : non 45 degree angle mvpsd</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nat_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on nat</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nat_angle</name>
+   <description>ACUTE : non 45 degree angle nat</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>comp_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on comp_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>comp_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle comp_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly2_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on poly2_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly2_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle poly2_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal1_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle metal1_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal2_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle metal2_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal3_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle metal3_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal4_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle metal4_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal5_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle metal5_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metaltop_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle metaltop_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>comp_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on comp_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>comp_label_angle</name>
+   <description>ACUTE : non 45 degree angle comp_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly2_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on poly2_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly2_label_angle</name>
+   <description>ACUTE : non 45 degree angle poly2_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal1_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_label_angle</name>
+   <description>ACUTE : non 45 degree angle metal1_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal2_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_label_angle</name>
+   <description>ACUTE : non 45 degree angle metal2_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal3_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_label_angle</name>
+   <description>ACUTE : non 45 degree angle metal3_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal4_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_label_angle</name>
+   <description>ACUTE : non 45 degree angle metal4_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal5_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_label_angle</name>
+   <description>ACUTE : non 45 degree angle metal5_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metaltop_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_label_angle</name>
+   <description>ACUTE : non 45 degree angle metaltop_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_slot_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal1_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_slot_angle</name>
+   <description>ACUTE : non 45 degree angle metal1_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_slot_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal2_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_slot_angle</name>
+   <description>ACUTE : non 45 degree angle metal2_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_slot_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal3_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_slot_angle</name>
+   <description>ACUTE : non 45 degree angle metal3_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_slot_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal4_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_slot_angle</name>
+   <description>ACUTE : non 45 degree angle metal4_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_slot_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal5_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_slot_angle</name>
+   <description>ACUTE : non 45 degree angle metal5_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_slot_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metaltop_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_slot_angle</name>
+   <description>ACUTE : non 45 degree angle metaltop_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ubmpperi_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ubmpperi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ubmpperi_angle</name>
+   <description>ACUTE : non 45 degree angle ubmpperi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ubmparray_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ubmparray</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ubmparray_angle</name>
+   <description>ACUTE : non 45 degree angle ubmparray</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ubmeplate_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ubmeplate</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ubmeplate_angle</name>
+   <description>ACUTE : non 45 degree angle ubmeplate</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>schottky_diode_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on schottky_diode</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>schottky_diode_angle</name>
+   <description>ACUTE : non 45 degree angle schottky_diode</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>zener_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on zener</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>zener_angle</name>
+   <description>ACUTE : non 45 degree angle zener</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>res_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on res_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>res_mk_angle</name>
+   <description>ACUTE : non 45 degree angle res_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>opc_drc_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on opc_drc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>opc_drc_angle</name>
+   <description>ACUTE : non 45 degree angle opc_drc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ndmy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ndmy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ndmy_angle</name>
+   <description>ACUTE : non 45 degree angle ndmy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pmndmy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on pmndmy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pmndmy_angle</name>
+   <description>ACUTE : non 45 degree angle pmndmy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>v5_xtor_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on v5_xtor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>v5_xtor_angle</name>
+   <description>ACUTE : non 45 degree angle v5_xtor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on cap_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap_mk_angle</name>
+   <description>ACUTE : non 45 degree angle cap_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mos_cap_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mos_cap_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mos_cap_mk_angle</name>
+   <description>ACUTE : non 45 degree angle mos_cap_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ind_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ind_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ind_mk_angle</name>
+   <description>ACUTE : non 45 degree angle ind_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diode_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on diode_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diode_mk_angle</name>
+   <description>ACUTE : non 45 degree angle diode_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>drc_bjt_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on drc_bjt</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>drc_bjt_angle</name>
+   <description>ACUTE : non 45 degree angle drc_bjt</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_bjt_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on lvs_bjt</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_bjt_angle</name>
+   <description>ACUTE : non 45 degree angle lvs_bjt</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mim_l_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mim_l_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mim_l_mk_angle</name>
+   <description>ACUTE : non 45 degree angle mim_l_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>latchup_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on latchup_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>latchup_mk_angle</name>
+   <description>ACUTE : non 45 degree angle latchup_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>guard_ring_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on guard_ring_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>guard_ring_mk_angle</name>
+   <description>ACUTE : non 45 degree angle guard_ring_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>otp_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on otp_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>otp_mk_angle</name>
+   <description>ACUTE : non 45 degree angle otp_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mtpmark_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mtpmark</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mtpmark_angle</name>
+   <description>ACUTE : non 45 degree angle mtpmark</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>neo_ee_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on neo_ee_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>neo_ee_mk_angle</name>
+   <description>ACUTE : non 45 degree angle neo_ee_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>sramcore_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on sramcore</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>sramcore_angle</name>
+   <description>ACUTE : non 45 degree angle sramcore</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_rf_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on lvs_rf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_rf_angle</name>
+   <description>ACUTE : non 45 degree angle lvs_rf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_drain_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on lvs_drain</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_drain_angle</name>
+   <description>ACUTE : non 45 degree angle lvs_drain</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvpolyrs_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on hvpolyrs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvpolyrs_angle</name>
+   <description>ACUTE : non 45 degree angle hvpolyrs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_io_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on lvs_io</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_io_angle</name>
+   <description>ACUTE : non 45 degree angle lvs_io</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>probe_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on probe_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>probe_mk_angle</name>
+   <description>ACUTE : non 45 degree angle probe_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>esd_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on esd_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>esd_mk_angle</name>
+   <description>ACUTE : non 45 degree angle esd_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_source_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on lvs_source</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_source_angle</name>
+   <description>ACUTE : non 45 degree angle lvs_source</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>well_diode_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on well_diode_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>well_diode_mk_angle</name>
+   <description>ACUTE : non 45 degree angle well_diode_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ldmos_xtor_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ldmos_xtor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ldmos_xtor_angle</name>
+   <description>ACUTE : non 45 degree angle ldmos_xtor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>plfuse_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on plfuse</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>plfuse_angle</name>
+   <description>ACUTE : non 45 degree angle plfuse</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>efuse_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on efuse_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>efuse_mk_angle</name>
+   <description>ACUTE : non 45 degree angle efuse_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mcell_feol_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mcell_feol_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mcell_feol_mk_angle</name>
+   <description>ACUTE : non 45 degree angle mcell_feol_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ymtp_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ymtp_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ymtp_mk_angle</name>
+   <description>ACUTE : non 45 degree angle ymtp_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dev_wf_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on dev_wf_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dev_wf_mk_angle</name>
+   <description>ACUTE : non 45 degree angle dev_wf_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_blk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal1_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_blk_angle</name>
+   <description>ACUTE : non 45 degree angle metal1_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_blk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal2_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_blk_angle</name>
+   <description>ACUTE : non 45 degree angle metal2_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_blk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal3_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_blk_angle</name>
+   <description>ACUTE : non 45 degree angle metal3_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_blk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal4_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_blk_angle</name>
+   <description>ACUTE : non 45 degree angle metal4_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_blk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal5_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_blk_angle</name>
+   <description>ACUTE : non 45 degree angle metal5_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metalt_blk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metalt_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metalt_blk_angle</name>
+   <description>ACUTE : non 45 degree angle metalt_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pr_bndry_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on pr_bndry</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pr_bndry_angle</name>
+   <description>ACUTE : non 45 degree angle pr_bndry</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mdiode_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mdiode</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mdiode_angle</name>
+   <description>ACUTE : non 45 degree angle mdiode</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_res_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal1_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_res_angle</name>
+   <description>ACUTE : non 45 degree angle metal1_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_res_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal2_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_res_angle</name>
+   <description>ACUTE : non 45 degree angle metal2_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_res_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal3_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_res_angle</name>
+   <description>ACUTE : non 45 degree angle metal3_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_res_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal4_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_res_angle</name>
+   <description>ACUTE : non 45 degree angle metal4_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_res_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal5_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_res_angle</name>
+   <description>ACUTE : non 45 degree angle metal5_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal6_res_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal6_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal6_res_angle</name>
+   <description>ACUTE : non 45 degree angle metal6_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>border_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on border</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>border_angle</name>
+   <description>ACUTE : non 45 degree angle border</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>

diff --git a/mpw_precheck/outputs/reports/klayout_feol_check.xml b/mpw_precheck/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..46e9d88
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_feol_check.xml

@@ -0,0 +1,3789 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>DRC Run Report at</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/gf180mcuC_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>DN.1</name>
+   <description>DN.1 : Min. DNWELL Width : 1.7µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DN.2a</name>
+   <description>DN.2a : Min. DNWELL Space (Equi-potential), Merge if the space is less than : 2.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DN.2b</name>
+   <description>DN.2b : Min. DNWELL Space (Different potential) : 5.42µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DN.3</name>
+   <description>DN.3 : Each DNWELL shall be directly surrounded by PCOMP guard ring tied to the P-substrate potential.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LPW.1_3.3V</name>
+   <description>LPW.1_3.3V : Min. LVPWELL Width. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LPW.1_5V</name>
+   <description>LPW.1_5V : Min. LVPWELL Width. : 0.74µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LPW.2a_3.3V</name>
+   <description>LPW.2a_3.3V : Min. LVPWELL to LVWELL Space (Inside DNWELL) [Different potential]. : 1.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LPW.2a_5V</name>
+   <description>LPW.2a_5V : Min. LVPWELL to LVPWELL Space (Inside DNWELL) [Different potential]. : 1.7µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LPW.2b_3.3V</name>
+   <description>LPW.2b_3.3V : Min. LVPWELL to LVPWELL Space [Equi potential]. : 0.86µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LPW.2b_5V</name>
+   <description>LPW.2b_5V : Min. LVPWELL to LVPWELL Space [Equi potential]. : 0.86µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LPW.3_3.3V</name>
+   <description>LPW.3_3.3V : Min. DNWELL enclose LVPWELL. : 2.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LPW.3_5V</name>
+   <description>LPW.3_5V : Min. DNWELL enclose LVPWELL. : 2.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LPW.5_3.3V</name>
+   <description>LPW.5_3.3V : LVPWELL resistors must be enclosed by DNWELL.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LPW.5_5V</name>
+   <description>LPW.5_5V : LVPWELL resistors must be enclosed by DNWELL.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LPW.11</name>
+   <description>LPW.11 : Min. (LVPWELL outside DNWELL) space to DNWELL. : 1.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LPW.12</name>
+   <description>LPW.12 : LVPWELL cannot overlap with Nwell.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NW.1a_3.3V</name>
+   <description>NW.1a_3.3V : Min. Nwell Width (This is only for litho purpose on the generated area). : 0.86µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NW.1a_5V</name>
+   <description>NW.1a_5V : Min. Nwell Width (This is only for litho purpose on the generated area). : 0.86µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NW.1b_3.3V</name>
+   <description>NW.1b_3.3V : Min. Nwell Width as a resistor (Outside DNWELL only). : 2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NW.1b_5V</name>
+   <description>NW.1b_5V : Min. Nwell Width as a resistor (Outside DNWELL only). : 2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NW.2a_3.3V</name>
+   <description>NW.2a_3.3V : Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NW.2a_5V</name>
+   <description>NW.2a_5V : Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. : 0.74µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NW.2b_3.3V</name>
+   <description>NW.2b_3.3V : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NW.2b_5V</name>
+   <description>NW.2b_5V : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.7µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NW.3_3.3V</name>
+   <description>NW.3_3.3V : Min. Nwell to DNWELL space. : 3.1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NW.3_5V</name>
+   <description>NW.3_5V : Min. Nwell to DNWELL space. : 3.1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NW.4_3.3V</name>
+   <description>NW.4_3.3V : Min. Nwell to LVPWELL space.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NW.4_5V</name>
+   <description>NW.4_5V : Min. Nwell to LVPWELL space.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NW.5_3.3V</name>
+   <description>NW.5_3.3V : Min. DNWELL enclose Nwell. : 0.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NW.5_5V</name>
+   <description>NW.5_5V : Min. DNWELL enclose Nwell. : 0.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NW.6</name>
+   <description>NW.6 : Nwell resistors can only exist outside DNWELL.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.1a_3.3V</name>
+   <description>DF.1a_3.3V : Min. COMP Width. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.1a_5V</name>
+   <description>DF.1a_5V : Min. COMP Width. : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.1c_3.3V</name>
+   <description>DF.1c_3.3V : Min. COMP Width for MOSCAP. : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.1c_5V</name>
+   <description>DF.1c_5V : Min. COMP Width for MOSCAP. : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.2a_3.3V</name>
+   <description>DF.2a_3.3V : Min Channel Width. : nil,0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.2a_5V</name>
+   <description>DF.2a_5V : Min Channel Width. : nil,0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.2b_3.3V</name>
+   <description>DF.2b_3.3V : Max. COMP width for all cases except those used for capacitors, marked by ‘MOS_CAP_MK’ layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.2b_5V</name>
+   <description>DF.2b_5V : Max. COMP width for all cases except those used for capacitors, marked by ‘MOS_CAP_MK’ layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.3a_3.3V</name>
+   <description>DF.3a_3.3V : Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.3a_5V</name>
+   <description>DF.3a_5V : Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. : 0.36µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.3b_3.3V</name>
+   <description>DF.3b_3.3V : Min./Max. NCOMP Space to PCOMP in the same well for butted COMP (MOSCAP butting is not allowed).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.3b_5V</name>
+   <description>DF.3b_5V : Min./Max. NCOMP Space to PCOMP in the same well for butted COMP(MOSCAP butting is not allowed).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.3c_3.3V</name>
+   <description>DF.3c_3.3V : Min. COMP Space in BJT area (area marked by DRC_BJT layer). : 0.32µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.3c_5V</name>
+   <description>DF.3c_5V : Min. COMP Space in BJT area (area marked by DRC_BJT layer) hasn’t been assessed.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.4a_3.3V</name>
+   <description>DF.4a_3.3V : Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. : 0.12µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.4a_5V</name>
+   <description>DF.4a_5V : Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.4b_3.3V</name>
+   <description>DF.4b_3.3V : Min. DNWELL overlap of NCOMP well tap. : 0.62µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.4b_5V</name>
+   <description>DF.4b_5V : Min. DNWELL overlap of NCOMP well tap. : 0.66µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.4c_3.3V</name>
+   <description>DF.4c_3.3V : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.43µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.4c_5V</name>
+   <description>DF.4c_5V : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.4d_3.3V</name>
+   <description>DF.4d_3.3V : Min. (Nwell overlap of NCOMP) outside DNWELL. : 0.12µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.4d_5V</name>
+   <description>DF.4d_5V : Min. (Nwell overlap of NCOMP) outside DNWELL. : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.4e_3.3V</name>
+   <description>DF.4e_3.3V : Min. DNWELL overlap of PCOMP. : 0.93µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.4e_5V</name>
+   <description>DF.4e_5V : Min. DNWELL overlap of PCOMP. : 1.1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.5_3.3V</name>
+   <description>DF.5_3.3V : Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. : 0.12µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.5_5V</name>
+   <description>DF.5_5V : Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.6_3.3V</name>
+   <description>DF.6_3.3V : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.24µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.6_5V</name>
+   <description>DF.6_5V : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.7_3.3V</name>
+   <description>DF.7_3.3V : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.43µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.7_5V</name>
+   <description>DF.7_5V : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.8_3.3V</name>
+   <description>DF.8_3.3V : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.43µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.8_5V</name>
+   <description>DF.8_5V : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.9_3.3V</name>
+   <description>DF.9_3.3V : Min. COMP area (um2). : 0.2025µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.9_5V</name>
+   <description>DF.9_5V : Min. COMP area (um2). : 0.2025µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.10_3.3V</name>
+   <description>DF.10_3.3V : Min. field area (um2). : 0.26µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.10_5V</name>
+   <description>DF.10_5V : Min. field area (um2). : 0.26µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.11_3.3V</name>
+   <description>DF.11_3.3V : Min. Length of butting COMP edge. : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.11_5V</name>
+   <description>DF.11_5V : Min. Length of butting COMP edge. : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.12_3.3V</name>
+   <description>DF.12_3.3V : COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.12_5V</name>
+   <description>DF.12_5V : COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.13_3.3V</name>
+   <description>DF.13_3.3V : Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.13_5V</name>
+   <description>DF.13_5V : Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.14_3.3V</name>
+   <description>DF.14_3.3V : Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.14_5V</name>
+   <description>DF.14_5V : Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.16_3.3V</name>
+   <description>DF.16_3.3V : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.43µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.16_5V</name>
+   <description>DF.16_5V : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.17_3.3V</name>
+   <description>DF.17_3.3V : Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). : 0.12µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.17_5V</name>
+   <description>DF.17_5V : Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.18_3.3V</name>
+   <description>DF.18_3.3V : Min. DNWELL space to (PCOMP outside Nwell and DNWELL). : 2.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.18_5V</name>
+   <description>DF.18_5V : Min. DNWELL space to (PCOMP outside Nwell and DNWELL). : 2.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.19_3.3V</name>
+   <description>DF.19_3.3V : Min. DNWELL space to (NCOMP outside Nwell and DNWELL). : 3.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DF.19_5V</name>
+   <description>DF.19_5V : Min. DNWELL space to (NCOMP outside Nwell and DNWELL). : 3.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DV.1</name>
+   <description>DV.1 : Min. Dualgate enclose DNWELL. : 0.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DV.2</name>
+   <description>DV.2 : Min. Dualgate Space. Merge if Space is less than this design rule. : 0.44µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DV.3</name>
+   <description>DV.3 : Min. Dualgate to COMP space [unrelated]. : 0.24µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DV.5</name>
+   <description>DV.5 : Min. Dualgate width. : 0.7µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DV.6</name>
+   <description>DV.6 : Min. Dualgate enclose COMP (except substrate tap). : 0.24µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DV.7</name>
+   <description>DV.7 : COMP (except substrate tap) can not be partially overlapped by Dualgate.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DV.8</name>
+   <description>DV.8 : Min Dualgate enclose Poly2. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DV.9</name>
+   <description>DV.9 : 3.3V and 5V/6V PMOS cannot be sitting inside same NWELL.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.1_3.3V</name>
+   <description>PL.1_3.3V : Interconnect Width (outside PLFUSE). : 0.18µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.1_5V</name>
+   <description>PL.1_5V : Interconnect Width (outside PLFUSE). : 0.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.1a_3.3V</name>
+   <description>PL.1a_3.3V : Interconnect Width (inside PLFUSE). : 0.18µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.1a_5V</name>
+   <description>PL.1a_5V : Interconnect Width (inside PLFUSE). : 0.18µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.2_3.3V</name>
+   <description>PL.2_3.3V : Gate Width (Channel Length). : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.2_5V</name>
+   <description>PL.2_5V : Gate Width (Channel Length).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.3a_3.3V</name>
+   <description>PL.3a_3.3V : Space on COMP/Field. : 0.24µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.3a_5V</name>
+   <description>PL.3a_5V : Space on COMP/Field. : 0.24µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.4_3.3V</name>
+   <description>PL.4_3.3V : Extension beyond COMP to form Poly2 end cap. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.4_5V</name>
+   <description>PL.4_5V : Extension beyond COMP to form Poly2 end cap. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.5a_3.3V</name>
+   <description>PL.5a_3.3V : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.5a_5V</name>
+   <description>PL.5a_5V : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.5b_3.3V</name>
+   <description>PL.5b_3.3V : Space from field Poly2 to related COMP. : 0.1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.5b_5V</name>
+   <description>PL.5b_5V : Space from field Poly2 to related COMP. : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.6</name>
+   <description>PL.6 : 90 degree bends on the COMP are not allowed.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.7_3.3V</name>
+   <description>PL.7_3.3V : 45 degree bent gate width : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.7_5V</name>
+   <description>PL.7_5V : 45 degree bent gate width : 0.7µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.9</name>
+   <description>PL.9 : Poly2 inter connect connecting 3.3V and 5V areas (area inside and outside Dualgate) are not allowed. They shall be done though metal lines only.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.11</name>
+   <description>PL.11 : V5_Xtor must enclose 5V device.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PL.12</name>
+   <description>PL.12 : V5_Xtor enclose 5V Comp.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.1</name>
+   <description>NP.1 : min. nplus width : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.2</name>
+   <description>NP.2 : min. nplus spacing : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.3a</name>
+   <description>NP.3a : Space to PCOMP for PCOMP: (1) Inside Nwell (2) Outside LVPWELL but inside DNWELL. : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.3bi</name>
+   <description>NP.3bi : Space to PCOMP: For Inside DNWELL, inside LVPWELL:(i) For PCOMP overlap by LVPWELL &lt; 0.43um. : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.3bii</name>
+   <description>NP.3bii : Space to PCOMP: For Inside DNWELL, inside LVPWELL:(ii) For PCOMP overlap by LVPWELL &gt;= 0.43um. : 0.08µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.3ci</name>
+   <description>NP.3ci : Space to PCOMP: For Outside DNWELL:(i) For PCOMP space to Nwell &lt; 0.43um. : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.3cii</name>
+   <description>NP.3cii : Space to PCOMP: For Outside DNWELL:(ii) For PCOMP space to Nwell &gt;= 0.43um. : 0.08µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.3d</name>
+   <description>NP.3d : Min/max space to a butted PCOMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.3e</name>
+   <description>NP.3e : Space to related PCOMP edge adjacent to a butting edge.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.4a</name>
+   <description>NP.4a : Space to related P-channel gate at a butting edge parallel to gate. : 0.32µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.4b</name>
+   <description>NP.4b : Within 0.32um of channel, space to P-channel gate extension perpendicular to the direction of Poly2.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.5a</name>
+   <description>NP.5a : Overlap of N-channel gate. : 0.23µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.5b</name>
+   <description>NP.5b : Extension beyond COMP for the COMP (1) inside LVPWELL (2) outside Nwell and DNWELL. : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.5ci</name>
+   <description>NP.5ci : Extension beyond COMP: For Inside DNWELL: (i)For Nplus &lt; 0.43um from LVPWELL edge for Nwell or DNWELL tap inside DNWELL. : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.5cii</name>
+   <description>NP.5cii : Extension beyond COMP: For Inside DNWELL: (ii) For Nplus &gt;= 0.43um from LVPWELL edge for Nwell or DNWELL tap inside DNWELL. : 0.02µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.5di</name>
+   <description>NP.5di : Extension beyond COMP: For Outside DNWELL, inside Nwell: (i) For Nwell overlap of Nplus &lt; 0.43um. : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.5dii</name>
+   <description>NP.5dii : Extension beyond COMP: For Outside DNWELL, inside Nwell: (ii) For Nwell overlap of Nplus &gt;= 0.43um. : 0.02µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.6</name>
+   <description>NP.6 : Overlap with NCOMP butted to PCOMP. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.7</name>
+   <description>NP.7 : Space to unrelated unsalicided Poly2. : 0.18µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.8a</name>
+   <description>NP.8a : Minimum Nplus area (um2). : 0.35µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.8b</name>
+   <description>NP.8b : Minimum area enclosed by Nplus (um2). : 0.35µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.9</name>
+   <description>NP.9 : Overlap of unsalicided Poly2. : 0.18µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.10</name>
+   <description>NP.10 : Overlap of unsalicided COMP. : 0.18µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.11</name>
+   <description>NP.11 : Butting Nplus and PCOMP is forbidden within 0.43um of Nwell edge (for outside DNWELL) and of LVPWELL edge (for inside DNWELL case).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NP.12</name>
+   <description>NP.12 : Overlap with P-channel poly2 gate extension is forbidden within 0.32um of P-channel gate.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.1</name>
+   <description>PP.1 : min. pplus width : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.2</name>
+   <description>PP.2 : min. pplus spacing : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.3a</name>
+   <description>PP.3a : Space to NCOMP for NCOMP (1) inside LVPWELL (2) outside NWELL and DNWELL. : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.3bi</name>
+   <description>PP.3bi : Space to NCOMP: For Inside DNWELL. (i) NCOMP space to LVPWELL &gt;= 0.43um. : 0.08µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.3bii</name>
+   <description>PP.3bii : Space to NCOMP: For Inside DNWELL. (ii) NCOMP space to LVPWELL &lt; 0.43um. : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.3ci</name>
+   <description>PP.3ci : Space to NCOMP: For Outside DNWELL, inside Nwell: (i) NWELL Overlap of NCOMP &gt;= 0.43um. : 0.08µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.3cii</name>
+   <description>PP.3cii : Space to NCOMP: For Outside DNWELL, inside Nwell: (ii) NWELL Overlap of NCOMP 0.43um. : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.3d</name>
+   <description>PP.3d : Min/max space to a butted NCOMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.3e</name>
+   <description>PP.3e : Space to NCOMP edge adjacent to a butting edge.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.4a</name>
+   <description>PP.4a : Space related to N-channel gate at a butting edge parallel to gate. : 0.32µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.4b</name>
+   <description>PP.4b : Within 0.32um of channel, space to N-channel gate extension perpendicular to the direction of Poly2.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.5a</name>
+   <description>PP.5a : Overlap of P-channel gate. : 0.23µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.5b</name>
+   <description>PP.5b : Extension beyond COMP for COMP (1) Inside NWELL (2) outside LVPWELL but inside DNWELL. : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.5ci</name>
+   <description>PP.5ci : Extension beyond COMP: For Inside DNWELL, inside LVPWELL: (i) For LVPWELL overlap of Pplus &gt;= 0.43um for LVPWELL tap. : 0.02µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.5cii</name>
+   <description>PP.5cii : Extension beyond COMP: For Inside DNWELL, inside LVPWELL: (ii) For LVPWELL overlap of Pplus &lt; 0.43um for the LVPWELL tap. : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.5di</name>
+   <description>PP.5di : Extension beyond COMP: For Outside DNWELL (i) For Pplus to NWELL space &gt;= 0.43um for Pfield or LVPWELL tap. : 0.02µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.5dii</name>
+   <description>PP.5dii : Extension beyond COMP: For Outside DNWELL (ii) For Pplus to NWELL space &lt; 0.43um for Pfield or LVPWELL tap. : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.6</name>
+   <description>PP.6 : Overlap with PCOMP butted to NCOMP. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.7</name>
+   <description>PP.7 : Space to unrelated unsalicided Poly2. : 0.18µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.8a</name>
+   <description>PP.8a : Minimum Pplus area (um2). : 0.35µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.8b</name>
+   <description>PP.8b : Minimum area enclosed by Pplus (um2). : 0.35µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.9</name>
+   <description>PP.9 : Overlap of unsalicided Poly2. : 0.18µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.10</name>
+   <description>PP.10 : Overlap of unsalicided COMP. : 0.18µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.11</name>
+   <description>PP.11 : Butting Pplus and NCOMP is forbidden within 0.43um of Nwell edge (for outside DNWELL) and of LVPWELL edge (for inside DNWELL case).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PP.12</name>
+   <description>PP.12 : Overlap with N-channel Poly2 gate extension is forbidden within 0.32um of N-channel gate.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.1</name>
+   <description>SB.1 : min. sab width : 0.42µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.2</name>
+   <description>SB.2 : min. sab spacing : 0.42µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.3</name>
+   <description>SB.3 : Space from salicide block to unrelated COMP. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.4</name>
+   <description>SB.4 : Space from salicide block to contact.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.5a</name>
+   <description>SB.5a : Space from salicide block to unrelated Poly2 on field. : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.5b</name>
+   <description>SB.5b : Space from salicide block to unrelated Poly2 on COMP. : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.6</name>
+   <description>SB.6 : Salicide block extension beyond related COMP. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.7</name>
+   <description>SB.7 : COMP extension beyond related salicide block. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.8</name>
+   <description>SB.8 : Non-salicided contacts are forbidden.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.9</name>
+   <description>SB.9 : Salicide block extension beyond unsalicided Poly2. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.10</name>
+   <description>SB.10 : Poly2 extension beyond related salicide block. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.11</name>
+   <description>SB.11 : Overlap with COMP. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.12</name>
+   <description>SB.12 : Overlap with Poly2 outside ESD_MK. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.13</name>
+   <description>SB.13 : Min. area (um2). : 2µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.14a</name>
+   <description>SB.14a : Space from unsalicided Nplus Poly2 to unsalicided Pplus Poly2. (Unsalicided Nplus Poly2 must not fall within a square of 0.56um x 0.56um at unsalicided Pplus Poly2 corners). : 0.56µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.14b</name>
+   <description>SB.14b : Space from unsalicided Nplus Poly2 to P-channel gate. (Unsalicided Nplus Poly2 must not fall within a square of 0.56um x 0.56um at P-channel gate corners). : 0.56µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.15a</name>
+   <description>SB.15a : Space from unsalicided Poly2 to unrelated Nplus/Pplus. : 0.18µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.15b</name>
+   <description>SB.15b : Space from unsalicided Poly2 to unrelated Nplus/Pplus along Poly2 line. : 0.32µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>SB.16</name>
+   <description>SB.16 : SAB layer cannot exist on 3.3V and 5V/6V CMOS transistors' Poly and COMP area of the core circuit (Excluding the transistors used for ESD purpose). It can only exist on CMOS transistors marked by LVS_IO, OTP_MK, ESD_MK layers.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ESD.1</name>
+   <description>ESD.1 : Minimum width of an ESD implant area. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ESD.2</name>
+   <description>ESD.2 : Minimum space between two ESD implant areas. (Merge if the space is less than 0.6um). : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ESD.3a</name>
+   <description>ESD.3a : Minimum space to NCOMP. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ESD.3b</name>
+   <description>ESD.3b : Min/max space to a butted PCOMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ESD.4a</name>
+   <description>ESD.4a : Extension beyond NCOMP. : 0.24µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ESD.4b</name>
+   <description>ESD.4b : Minimum overlap of an ESD implant edge to a COMP. : 0.45µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ESD.5a</name>
+   <description>ESD.5a : Minimum ESD area (um2). : 0.49µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ESD.5b</name>
+   <description>ESD.5b : Minimum field area enclosed by ESD implant (um2). : 0.49µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ESD.6</name>
+   <description>ESD.6 : Extension perpendicular to Poly2 gate. : 0.45µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ESD.7</name>
+   <description>ESD.7 : No ESD implant inside PCOMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ESD.8</name>
+   <description>ESD.8 : Minimum space to Nplus/Pplus. : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ESD.pl</name>
+   <description>ESD.pl : Minimum gate length of 5V/6V gate NMOS. : 0.8µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ESD.9</name>
+   <description>ESD.9 : ESD implant layer must be overlapped by Dualgate layer (as ESD implant option is only for 5V/6V devices).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ESD.10</name>
+   <description>ESD.10 : LVS_IO shall be drawn covering I/O MOS active area by minimum overlap.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>CO.1</name>
+   <description>CO.1 : Min/max contact size. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>CO.2a</name>
+   <description>CO.2a : min. contact spacing : 0.25µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>CO.2b</name>
+   <description>CO.2b : Space in 4x4 or larger contact array. : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>CO.3</name>
+   <description>CO.3 : Poly2 overlap of contact. : 0.07µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>CO.4</name>
+   <description>CO.4 : COMP overlap of contact. : 0.07µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>CO.5a</name>
+   <description>CO.5a : Nplus overlap of contact on COMP (Only for contacts to butted Nplus and Pplus COMP areas). : 0.1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>CO.5b</name>
+   <description>CO.5b : Pplus overlap of contact on COMP (Only for contacts to butted Nplus and Pplus COMP areas). : 0.1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>CO.6</name>
+   <description>CO.6 : Metal1 overlap of contact.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>CO.6a</name>
+   <description>CO.6a : (i) Metal1 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>CO.6b</name>
+   <description>CO.6b : (ii) If Metal1 overlaps contact by &lt; 0.04um on one side, adjacent metal1 edges overlap : 0.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>CO.7</name>
+   <description>CO.7 : Space from COMP contact to Poly2 on COMP. : 0.15µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>CO.8</name>
+   <description>CO.8 : Space from Poly2 contact to COMP. : 0.17µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>CO.9</name>
+   <description>CO.9 : Contact on NCOMP to PCOMP butting edge is forbidden (contact must not straddle butting edge).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>CO.10</name>
+   <description>CO.10 : Contact on Poly2 gate over COMP is forbidden.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>CO.11</name>
+   <description>CO.11 : Contact on field oxide is forbidden.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MC.1</name>
+   <description>MC.1 : min. mcell width : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MC.2</name>
+   <description>MC.2 : min. mcell spacing : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MC.3</name>
+   <description>MC.3 : Minimum Mcell area : 0.35µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MC.4</name>
+   <description>MC.4 : Minimum area enclosed by Mcell : 0.35µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.1</name>
+   <description>PRES.1 : Minimum width of Poly2 resistor. : 0.8µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.2</name>
+   <description>PRES.2 : Minimum space between Poly2 resistors. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.3</name>
+   <description>PRES.3 : Minimum space from Poly2 resistor to COMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.4</name>
+   <description>PRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.5</name>
+   <description>PRES.5 : Minimum Plus implant overlap of Poly2 resistor. : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.6</name>
+   <description>PRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction. : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.7</name>
+   <description>PRES.7 : Space from salicide block to contact on Poly2 resistor.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.9a</name>
+   <description>PRES.9a : Pplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.9b</name>
+   <description>PRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.1</name>
+   <description>LRES.1 : Minimum width of Poly2 resistor. : 0.8µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.2</name>
+   <description>LRES.2 : Minimum space between Poly2 resistors. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.3</name>
+   <description>LRES.3 : Minimum space from Poly2 resistor to COMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.4</name>
+   <description>LRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.5</name>
+   <description>LRES.5 : Minimum Nplus implant overlap of Poly2 resistor. : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.6</name>
+   <description>LRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction. : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.7</name>
+   <description>LRES.7 : Space from salicide block to contact on Poly2 resistor.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.9a</name>
+   <description>LRES.9a : Nplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2. </description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.9b</name>
+   <description>LRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.1</name>
+   <description>HRES.1 : Minimum space. Note : Merge if the spacing is less than 0.4 um. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.2</name>
+   <description>HRES.2 : Minimum width of Poly2 resistor. : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.3</name>
+   <description>HRES.3 : Minimum space between Poly2 resistors. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.4</name>
+   <description>HRES.4 : Minimum RESISTOR overlap of Poly2 resistor. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.5</name>
+   <description>HRES.5 : Minimum RESISTOR space to unrelated Poly2. : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.6</name>
+   <description>HRES.6 : Minimum RESISTOR space to COMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.7</name>
+   <description>HRES.7 : Minimum Pplus overlap of contact on Poly2 resistor. : 0.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.8</name>
+   <description>HRES.8 : Space from salicide block to contact on Poly2 resistor.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.9</name>
+   <description>HRES.9 : Minimum salicide block overlap of Poly2 resistor in width direction.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.10</name>
+   <description>HRES.10 : Minimum &amp; maximum Pplus overlap of SAB.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.12a</name>
+   <description>HRES.12a : P type Poly2 resistor (high sheet rho) shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by Pplus space) and width covering the width of Poly2. </description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.12b</name>
+   <description>HRES.12b : If the size of single RES_MK mark layer is greater than 15000 um2 and both side (X and Y) are greater than 80 um. Then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.1</name>
+   <description>MIMTM.1 : Minimum MiM bottom plate spacing to the bottom plate metal (whether adjacent MiM or routing metal). : 1.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.2</name>
+   <description>MIMTM.2 : Minimum MiM bottom plate overlap of Vian-1 layer. [This is applicable for Vian-1 within 1.06um oversize of FuseTop layer (referenced to virtual bottom plate)]. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.3</name>
+   <description>MIMTM.3 : Minimum MiM bottom plate overlap of Top plate.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.4</name>
+   <description>MIMTM.4 : Minimum MiM top plate (FuseTop) overlap of Vian-1. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.5</name>
+   <description>MIMTM.5 : Minimum spacing between top plate and the Vian-1 connecting to the bottom plate. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.6</name>
+   <description>MIMTM.6 : Minimum spacing between unrelated top plates. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.7</name>
+   <description>MIMTM.7 : Min FuseTop enclosure by CAP_MK.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.8a</name>
+   <description>MIMTM.8a : Minimum MIM cap area (defined by FuseTop area) (um2). : 25µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.8b</name>
+   <description>MIMTM.8b : Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required) (um2). : 10000µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.9</name>
+   <description>MIMTM.9 : Min. Via (Vian-1) spacing for sea of Via on MIM top plate. : 0.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.10</name>
+   <description>MIMTM.10 : (a) There cannot be any Vian-2 touching MIM bottom plate Metaln-1. (b) MIM bottom plate Metaln-1 can only be connected through the higher Via (Vian-1).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.11</name>
+   <description>MIMTM.11 : Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed MIMTM.8b rule. : -µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.1</name>
+   <description>NAT.1 : Min. NAT Overlap of COMP of Native Vt NMOS. : 2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.2</name>
+   <description>NAT.2 : Space to unrelated COMP (outside NAT). : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.3</name>
+   <description>NAT.3 : Space to NWell edge. : 0.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.4</name>
+   <description>NAT.4 : Minimum channel length for 3.3V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.5</name>
+   <description>NAT.5 : Minimum channel length for 6.0V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.6</name>
+   <description>NAT.6 : Two or more COMPs if connected to different potential are not allowed under same NAT layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.7</name>
+   <description>NAT.7 : Minimum NAT to NAT spacing. : 0.74µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.8</name>
+   <description>NAT.8 : Min. Dualgate overlap of NAT (for 5V/6V) native VT NMOS only.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.9</name>
+   <description>NAT.9 : Poly interconnect under NAT layer is not allowed, minimum spacing of un-related poly from the NAT layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.10</name>
+   <description>NAT.10 : Nwell, inside NAT layer are not allowed.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.11</name>
+   <description>NAT.11 : NCOMP not intersecting to Poly2, is not allowed inside NAT layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.12</name>
+   <description>NAT.12 : Poly2 not intersecting with COMP is not allowed inside NAT (Poly2 resistor is not allowed inside NAT).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>BJT.1</name>
+   <description>BJT.1 : Min. DRC_BJT overlap of DNWELL for NPN BJT.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>BJT.2</name>
+   <description>BJT.2 : Min. DRC_BJT overlap of PCOM in Psub.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>BJT.3</name>
+   <description>BJT.3 : Minimum space of DRC_BJT layer to unrelated COMP. : 0.1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DE.2</name>
+   <description>DE.2 : Minimum NDMY or PMNDMY size (x or y dimension in um). : 0.8µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DE.3</name>
+   <description>DE.3 : If size greater than 15000 um2 then two sides should not be greater than (um).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DE.4</name>
+   <description>DE.4 : Minimum NDMY to NDMY space (Merge if space is less). : 20µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LVS_BJT.1</name>
+   <description>LVS_BJT.1 : Minimum LVS_BJT enclosure of NPN or PNP Emitter COMP layers</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.DF.3a</name>
+   <description>O.DF.3a : Min. COMP Space. P-substrate tap (PCOMP outside NWELL) can be butted for different voltage devices as the potential is same. : 0.24µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.DF.6</name>
+   <description>O.DF.6 : Min. COMP extend beyond poly2 (it also means source/drain overhang). : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.DF.9</name>
+   <description>O.DF.9 : Min. COMP area (um2). : 0.1444µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.PL.2</name>
+   <description>O.PL.2 : Min. poly2 width. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.PL.3a</name>
+   <description>O.PL.3a : Min. poly2 Space on COMP. : 0.18µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.PL.4</name>
+   <description>O.PL.4 : Min. extension beyond COMP to form Poly2 end cap. : 0.14µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.2</name>
+   <description>O.SB.2 : Min. salicide Block Space. : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.3</name>
+   <description>O.SB.3 : Min. space from salicide block to unrelated COMP. : 0.09µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.4</name>
+   <description>O.SB.4 : Min. space from salicide block to contact.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.5b_3.3V</name>
+   <description>O.SB.5b_3.3V : Min. space from salicide block to unrelated Poly2 on COMP. : 0.1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.9</name>
+   <description>O.SB.9 : Min. salicide block extension beyond unsalicided Poly2. : 0.1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.11</name>
+   <description>O.SB.11 : Min. salicide block overlap with COMP. : 0.04µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.13_3.3V</name>
+   <description>O.SB.13_3.3V : Min. area of silicide block (um2). : 1.488µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.13_5V</name>
+   <description>O.SB.13_5V : Min. area of silicide block (um2). : 2µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.CO.7</name>
+   <description>O.CO.7 : Min. space from COMP contact to Poly2 on COMP. : 0.13µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.PL.ORT</name>
+   <description>O.PL.ORT : Orientation-restricted gates must have the gate width aligned along the X-axis (poly line running horizontally) in reference to wafer notch down. : 0µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.01</name>
+   <description>EF.01 : Min. (Poly2 butt PLFUSE) within EFUSE_MK and Pplus.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.02</name>
+   <description>EF.02 : Min. Max. PLFUSE width. : 0.18µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.03</name>
+   <description>EF.03 : Min. Max. PLFUSE length. : 1.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.04a</name>
+   <description>EF.04a : Min. Max. PLFUSE overlap Poly2 (coinciding permitted) and touch cathode and anode.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.04b</name>
+   <description>EF.04b : PLFUSE must be rectangular. : -µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.04c</name>
+   <description>EF.04c : Cathode Poly2 must be rectangular. : -µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.04d</name>
+   <description>EF.04d : Anode Poly2 must be rectangular. : -µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.05</name>
+   <description>EF.05 : Min./Max. LVS_Source overlap Poly2 (at Anode).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.06</name>
+   <description>EF.06 : Min./Max. Cathode Poly2 width. : 2.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.07</name>
+   <description>EF.07 : Min./Max. Cathode Poly2 length. : 1.84µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.08</name>
+   <description>EF.08 : Min./Max. Anode Poly2 width. : 1.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.09</name>
+   <description>EF.09 : Min./Max. Anode Poly2 length. : 2.43µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.10</name>
+   <description>EF.10 : Min. Cathode Poly2 to Poly2 space. : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.11</name>
+   <description>EF.11 : Min. Anode Poly2 to Poly2 space. : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.12</name>
+   <description>EF.12 : Min. Space of Cathode Contact to PLFUSE end.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.13</name>
+   <description>EF.13 : Min. Space of Anode Contact to PLFUSE end.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.14</name>
+   <description>EF.14 : Min. EFUSE_MK enclose LVS_Source.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.15</name>
+   <description>EF.15 : NO Contact is allowed to touch PLFUSE.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.16a</name>
+   <description>EF.16a : Cathode must contain exact number of Contacts at each ends. : 4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.16b</name>
+   <description>EF.16b : Anode must contain exact number of Contacts at each ends. : 4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.17</name>
+   <description>EF.17 : Min. Space of EFUSE_MK to EFUSE_MK. : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.18</name>
+   <description>EF.18 : PLFUSE must sit on field oxide (NOT COMP), no cross with any COMP, Nplus, Pplus, ESD, SAB, Resistor, Metal1, Metal2.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.19</name>
+   <description>EF.19 : Min. PLFUSE space to Metal1, Metal2.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.20</name>
+   <description>EF.20 : Min. PLFUSE space to COMP, Nplus, Pplus, Resistor, ESD, SAB. : 2.73µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.21</name>
+   <description>EF.21 : Min./Max. eFUSE Poly2 length. : 5.53µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.22a</name>
+   <description>EF.22a : Min./Max. Cathode Poly2 overlap with PLFUSE in width direction. : 1.04µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.22b</name>
+   <description>EF.22b : Min./Max. Anode Poly2 overlap with PLFUSE in width direction. : 0.44µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.1</name>
+   <description>MDN.1 : Min MVSD width (for litho purpose). : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.2a</name>
+   <description>MDN.2a : Min MVSD space [Same Potential]. : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.2b</name>
+   <description>MDN.2b : Min MVSD space [Diff Potential]. : 2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.3a</name>
+   <description>MDN.3a : Min transistor channel length. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.3b</name>
+   <description>MDN.3b : Max transistor channel length: 20 um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.4a</name>
+   <description>MDN.4a : Min transistor channel width. : 4 µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.4b</name>
+   <description>MDN.4b : Max transistor channel width. : 50 um </description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.5ai</name>
+   <description>MDN.5ai : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap non-butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.5aii</name>
+   <description>MDN.5aii : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed. : 0.92µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.5b</name>
+   <description>MDN.5b : Min PCOMP (Pplus AND COMP) space to LDNMOS Source (Nplus AND COMP). Use butted source and p-substrate tab otherwise and that is good for Latch-up immunity as well.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.5c</name>
+   <description>MDN.5c : Maximum distance of the nearest edge of the substrate tab from NCOMP edge. : 15µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.6</name>
+   <description>MDN.6 : ALL LDNMOS shall be covered by Dualgate layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.6a</name>
+   <description>MDN.6a : Min Dualgate enclose NCOMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.7</name>
+   <description>MDN.7 : Each LDNMOS shall be covered by LDMOS_XTOR (GDS#226) mark layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.7a</name>
+   <description>MDN.7a : Min LDMOS_XTOR enclose Dualgate.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.8a</name>
+   <description>MDN.8a : Min LDNMOS drain MVSD space to any other equal potential Nwell space.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.8b</name>
+   <description>MDN.8b : Min LDNMOS drain MVSD space to any other different potential Nwell space.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.9</name>
+   <description>MDN.9 : Min LDNMOS drain MVSD space to NCOMP (Nplus AND COMP) outside LDNMOS drain MVSD. : 4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10a</name>
+   <description>MDN.10a : Min LDNMOS POLY2 width. : 1.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10b</name>
+   <description>MDN.10b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDNMOS drain direction). : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10c</name>
+   <description>MDN.10c : Min/Max POLY2 extension beyond COMP on the field towards LDNMOS drain COMP direction.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10d</name>
+   <description>MDN.10d : Min/Max POLY2 on field space to LDNMOS drain COMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10ei</name>
+   <description>MDN.10ei : Min POLY2 space to Psub tap (source and body tap non-butted).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10eii</name>
+   <description>MDN.10eii : Min POLY2 space to Psub tap (source and body tap butted). : 0.32µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10f</name>
+   <description>MDN.10f : Poly2 interconnect in HV region (LDMOS_XTOR marked region) not allowed. Also, any Poly2 interconnect with poly2 to substrate potential greater than 6V is not allowed.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.11</name>
+   <description>MDN.11 : Min/Max MVSD overlap channel COMP ((((LDMOS_XTOR AND MVSD) AND COMP) AND POLY2) AND NPlus).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.12</name>
+   <description>MDN.12 : Min MVSD enclose NCOMP in the LDNMOS drain and in the direction along the transistor width.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.13a</name>
+   <description>MDN.13a : Max single finger width. : 50µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.13b</name>
+   <description>MDN.13b : Layout shall have alternative source &amp; drain.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.13c</name>
+   <description>MDN.13c : Both sides of the transistor shall be terminated by source.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.13d</name>
+   <description>MDN.13d : Every two poly fingers shall be surrounded by a P-sub guard ring. (Exclude the case when each LDNMOS transistor have full width butting to well tap).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.14</name>
+   <description>MDN.14 : Min MVSD space to any DNWELL.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.15a</name>
+   <description>MDN.15a : Min LDNMOS drain COMP width. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.15b</name>
+   <description>MDN.15b : Min LDNMOS drain COMP enclose contact. : 0µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.17</name>
+   <description>MDN.17 : It is recommended to surround the LDNMOS transistor with non-broken Psub guard ring to improve the latch up immunity. Guideline to improve the latch up immunity.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.1</name>
+   <description>MDP.1 : Minimum transistor channel length. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.1a</name>
+   <description>MDP.1a : Max transistor channel length.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.2</name>
+   <description>MDP.2 : Minimum transistor channel width. : 4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.3</name>
+   <description>MDP.3 : Each LDPMOS shall be surrounded by non-broken Nplus guard ring inside DNWELL</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.3ai</name>
+   <description>MDP.3ai : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap non-butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.3aii</name>
+   <description>MDP.3aii : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.3b</name>
+   <description>MDP.3b : Min NCOMP (Nplus AND COMP) space to PCOMP in DNWELL (Pplus AND COMP AND DNWELL). Use butted source and DNWELL contacts otherwise and that is best for Latch-up immunity as well. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.3c</name>
+   <description>MDP.3c : Maximum distance of the nearest edge of the DNWELL tab (NCOMP inside DNWELL) from PCOMP edge (PCOMP inside DNWELL). : 15µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.3d</name>
+   <description>MDP.3d : The metal connection for the Nplus guard ring recommended to be continuous. The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability. : 10µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.4</name>
+   <description>MDP.4 : DNWELL covering LDPMOS shall be surrounded by non broken Pplus guard. The metal connection for the Pplus guard ring recommended to be continuous, The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.4a</name>
+   <description>MDP.4a : Min PCOMP (Pplus AND COMP) space to DNWELL. : 2.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.4b</name>
+   <description>MDP.4b : Maximum distance of the nearest edge of the DNWELL from the PCOMP Guard ring outside DNWELL. : 15µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.5</name>
+   <description>MDP.5 : Each LDPMOS shall be covered by Dualgate layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.5a</name>
+   <description>MDP.5a : Minimum Dualgate enclose Plus guarding ring PCOMP (Pplus AND COMP). : 0.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.6</name>
+   <description>MDP.6 : Each LDPMOS shall be covered by LDMOS_XTOR (GDS#226) layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.6a</name>
+   <description>MDP.6a : Minimum LDMOS_XTOR enclose Dualgate.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.7</name>
+   <description>MDP.7 : Minimum LDMOS_XTOR layer space to Nwell outside LDMOS_XTOR. : 2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.8</name>
+   <description>MDP.8 : Minimum LDMOS_XTOR layer space to NCOMP outside LDMOS_XTOR. : 1.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9a</name>
+   <description>MDP.9a : Min LDPMOS POLY2 width. : 1.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9b</name>
+   <description>MDP.9b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDMOS drain direction). : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9c</name>
+   <description>MDP.9c : Min/Max POLY2 extension beyond COMP on the field towards LDPMOS drain (MVPSD AND COMP AND Pplus NOT POLY2) direction.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9d</name>
+   <description>MDP.9d : Min/Max POLY2 on field to LDPMOS drain COMP (MVPSD AND COMP AND Pplus NOT POLY2) space.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9ei</name>
+   <description>MDP.9ei : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap non-butted).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9eii</name>
+   <description>MDP.9eii : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap butted).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9f</name>
+   <description>MDP.9f : Poly2 interconnect is not allowed in LDPMOS region (LDMOS_XTOR marked region). : -µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.10</name>
+   <description>MDP.10 : Min/Max MVPSD overlap onto the channel (LDMOS_XTOR AND COMP AND POLY2 AND Pplus).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.10a</name>
+   <description>MDP.10a : Min MVPSD space within LDMOS_XTOR marking [diff potential]. : 2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.10b</name>
+   <description>MDP.10b : Min MVPSD space [same potential]. Merge if space less than 1um. : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.11</name>
+   <description>MDP.11 : Min MVPSD enclosing PCOMP in the drain (MVPSD AND COMP NOT POLY2) direction and in the direction along the transistor width.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.12</name>
+   <description>MDP.12 : Min DNWELL enclose Nplus guard ring (NCOMP). : 0.66µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.13a</name>
+   <description>MDP.13a : Max single finger width. : 50µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.13b</name>
+   <description>MDP.13b : Layout shall have alternative source &amp; drain.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.13c</name>
+   <description>MDP.13c : Both sides of the transistor shall be terminated by source.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.15</name>
+   <description>MDP.15 : Min DNWELL enclosing MVPSD to any DNWELL spacing. : 6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.16a</name>
+   <description>MDP.16a : Min LDPMOS drain COMP width. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.16b</name>
+   <description>MDP.16b : Min LDPMOS drain COMP enclose contact. : 0µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.17a</name>
+   <description>MDP.17a : For better latch up immunity, it is necessary to put DNWELL guard ring between MVPSD Inside DNWELL covered by LDMOS_XTOR and NCOMP (outside DNWELL and outside Nwell) when spacing between them is less than 40um.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.17c</name>
+   <description>MDP.17c : DNWELL guard ring shall have NCOMP tab to be connected to highest potential</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.NW.2b_3.3V</name>
+   <description>Y.NW.2b_3.3V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.NW.2b_5V</name>
+   <description>Y.NW.2b_5V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.DF.6_5V</name>
+   <description>Y.DF.6_5V : Min. COMP extend beyond gate (it also means source/drain overhang) inside YMTP_MK. : 0.15µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.DF.16_3.3V</name>
+   <description>Y.DF.16_3.3V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.27µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.DF.16_5V</name>
+   <description>Y.DF.16_5V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.23µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.1_3.3V</name>
+   <description>Y.PL.1_3.3V : Interconnect Width (inside YMTP_MK). : 0.13µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.1_5V</name>
+   <description>Y.PL.1_5V : Interconnect Width (inside YMTP_MK). This rule is currently not applicable for 5V.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.2_3.3V</name>
+   <description>Y.PL.2_3.3V : Gate Width (Channel Length) (inside YMTP_MK). : 0.13µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.2_5V</name>
+   <description>Y.PL.2_5V : Gate Width (Channel Length) (inside YMTP_MK). : 0.47µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.4_5V</name>
+   <description>Y.PL.4_5V : Poly2 extension beyond COMP to form Poly2 end cap (inside YMTP_MK). : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.5a_3.3V</name>
+   <description>Y.PL.5a_3.3V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.04µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.5a_5V</name>
+   <description>Y.PL.5a_5V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.5b_3.3V</name>
+   <description>Y.PL.5b_3.3V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.04µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.5b_5V</name>
+   <description>Y.PL.5b_5V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.4c_MV</name>
+   <description>S.DF.4c_MV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.45µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.6_MV</name>
+   <description>S.DF.6_MV : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.32µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.7_MV</name>
+   <description>S.DF.7_MV : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.45µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.8_MV</name>
+   <description>S.DF.8_MV : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.45µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.16_MV</name>
+   <description>S.DF.16_MV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.45µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.PL.5a_MV</name>
+   <description>S.PL.5a_MV : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.12µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.PL.5b_MV</name>
+   <description>S.PL.5b_MV : Space from field Poly2 to related COMP. : 0.12µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.CO.4_MV</name>
+   <description>S.CO.4_MV : COMP overlap of contact. : 0.04µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.4c_LV</name>
+   <description>S.DF.4c_LV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.16_LV</name>
+   <description>S.DF.16_LV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.CO.3_LV</name>
+   <description>S.CO.3_LV : Poly2 overlap of contact. : 0.04µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.CO.4_LV</name>
+   <description>S.CO.4_LV : COMP overlap of contact. : 0.03µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.CO.6_ii_LV</name>
+   <description>S.CO.6_ii_LV : (ii) If Metal1 overlaps contact by &lt; 0.04um on one side, adjacent metal1 edges overlap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.M1.1_LV</name>
+   <description>S.M1.1_LV : min. metal1 width : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>comp_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on comp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>comp_angle</name>
+   <description>ACUTE : non 45 degree angle comp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_angle</name>
+   <description>ACUTE : non 45 degree angle dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_angle</name>
+   <description>ACUTE : non 45 degree angle nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvpwell_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on lvpwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvpwell_angle</name>
+   <description>ACUTE : non 45 degree angle lvpwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dualgate_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on dualgate</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dualgate_angle</name>
+   <description>ACUTE : non 45 degree angle dualgate</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly2_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on poly2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly2_angle</name>
+   <description>ACUTE : non 45 degree angle poly2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nplus_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on nplus</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nplus_angle</name>
+   <description>ACUTE : non 45 degree angle nplus</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pplus_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on pplus</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pplus_angle</name>
+   <description>ACUTE : non 45 degree angle pplus</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>sab_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on sab</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>sab_angle</name>
+   <description>ACUTE : non 45 degree angle sab</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>esd_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on esd</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>esd_angle</name>
+   <description>ACUTE : non 45 degree angle esd</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>contact_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on contact</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>contact_angle</name>
+   <description>ACUTE : non 45 degree angle contact</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_angle</name>
+   <description>ACUTE : non 45 degree angle metal1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via1_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on via1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via1_angle</name>
+   <description>ACUTE : non 45 degree angle via1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_angle</name>
+   <description>ACUTE : non 45 degree angle metal2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_angle</name>
+   <description>ACUTE : non 45 degree angle via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_angle</name>
+   <description>ACUTE : non 45 degree angle metal3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_angle</name>
+   <description>ACUTE : non 45 degree angle via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_angle</name>
+   <description>ACUTE : non 45 degree angle metal4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_angle</name>
+   <description>ACUTE : non 45 degree angle via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_angle</name>
+   <description>ACUTE : non 45 degree angle metal5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via5_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on via5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via5_angle</name>
+   <description>ACUTE : non 45 degree angle via5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metaltop</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_angle</name>
+   <description>ACUTE : non 45 degree angle metaltop</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_angle</name>
+   <description>ACUTE : non 45 degree angle pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>resistor_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on resistor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>resistor_angle</name>
+   <description>ACUTE : non 45 degree angle resistor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>fhres_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on fhres</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>fhres_angle</name>
+   <description>ACUTE : non 45 degree angle fhres</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>fusetop_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on fusetop</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>fusetop_angle</name>
+   <description>ACUTE : non 45 degree angle fusetop</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>fusewindow_d_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on fusewindow_d</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>fusewindow_d_angle</name>
+   <description>ACUTE : non 45 degree angle fusewindow_d</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>polyfuse_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on polyfuse</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>polyfuse_angle</name>
+   <description>ACUTE : non 45 degree angle polyfuse</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mvsd_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mvsd</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mvsd_angle</name>
+   <description>ACUTE : non 45 degree angle mvsd</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mvpsd_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mvpsd</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mvpsd_angle</name>
+   <description>ACUTE : non 45 degree angle mvpsd</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nat_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on nat</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nat_angle</name>
+   <description>ACUTE : non 45 degree angle nat</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>comp_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on comp_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>comp_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle comp_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly2_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on poly2_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly2_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle poly2_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal1_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle metal1_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal2_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle metal2_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal3_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle metal3_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal4_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle metal4_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal5_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle metal5_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metaltop_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle metaltop_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>comp_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on comp_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>comp_label_angle</name>
+   <description>ACUTE : non 45 degree angle comp_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly2_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on poly2_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly2_label_angle</name>
+   <description>ACUTE : non 45 degree angle poly2_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal1_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_label_angle</name>
+   <description>ACUTE : non 45 degree angle metal1_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal2_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_label_angle</name>
+   <description>ACUTE : non 45 degree angle metal2_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal3_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_label_angle</name>
+   <description>ACUTE : non 45 degree angle metal3_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal4_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_label_angle</name>
+   <description>ACUTE : non 45 degree angle metal4_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal5_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_label_angle</name>
+   <description>ACUTE : non 45 degree angle metal5_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metaltop_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_label_angle</name>
+   <description>ACUTE : non 45 degree angle metaltop_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_slot_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal1_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_slot_angle</name>
+   <description>ACUTE : non 45 degree angle metal1_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_slot_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal2_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_slot_angle</name>
+   <description>ACUTE : non 45 degree angle metal2_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_slot_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal3_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_slot_angle</name>
+   <description>ACUTE : non 45 degree angle metal3_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_slot_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal4_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_slot_angle</name>
+   <description>ACUTE : non 45 degree angle metal4_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_slot_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal5_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_slot_angle</name>
+   <description>ACUTE : non 45 degree angle metal5_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_slot_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metaltop_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_slot_angle</name>
+   <description>ACUTE : non 45 degree angle metaltop_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ubmpperi_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ubmpperi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ubmpperi_angle</name>
+   <description>ACUTE : non 45 degree angle ubmpperi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ubmparray_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ubmparray</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ubmparray_angle</name>
+   <description>ACUTE : non 45 degree angle ubmparray</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ubmeplate_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ubmeplate</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ubmeplate_angle</name>
+   <description>ACUTE : non 45 degree angle ubmeplate</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>schottky_diode_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on schottky_diode</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>schottky_diode_angle</name>
+   <description>ACUTE : non 45 degree angle schottky_diode</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>zener_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on zener</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>zener_angle</name>
+   <description>ACUTE : non 45 degree angle zener</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>res_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on res_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>res_mk_angle</name>
+   <description>ACUTE : non 45 degree angle res_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>opc_drc_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on opc_drc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>opc_drc_angle</name>
+   <description>ACUTE : non 45 degree angle opc_drc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ndmy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ndmy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ndmy_angle</name>
+   <description>ACUTE : non 45 degree angle ndmy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pmndmy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on pmndmy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pmndmy_angle</name>
+   <description>ACUTE : non 45 degree angle pmndmy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>v5_xtor_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on v5_xtor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>v5_xtor_angle</name>
+   <description>ACUTE : non 45 degree angle v5_xtor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on cap_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap_mk_angle</name>
+   <description>ACUTE : non 45 degree angle cap_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mos_cap_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mos_cap_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mos_cap_mk_angle</name>
+   <description>ACUTE : non 45 degree angle mos_cap_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ind_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ind_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ind_mk_angle</name>
+   <description>ACUTE : non 45 degree angle ind_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diode_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on diode_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diode_mk_angle</name>
+   <description>ACUTE : non 45 degree angle diode_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>drc_bjt_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on drc_bjt</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>drc_bjt_angle</name>
+   <description>ACUTE : non 45 degree angle drc_bjt</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_bjt_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on lvs_bjt</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_bjt_angle</name>
+   <description>ACUTE : non 45 degree angle lvs_bjt</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mim_l_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mim_l_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mim_l_mk_angle</name>
+   <description>ACUTE : non 45 degree angle mim_l_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>latchup_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on latchup_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>latchup_mk_angle</name>
+   <description>ACUTE : non 45 degree angle latchup_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>guard_ring_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on guard_ring_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>guard_ring_mk_angle</name>
+   <description>ACUTE : non 45 degree angle guard_ring_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>otp_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on otp_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>otp_mk_angle</name>
+   <description>ACUTE : non 45 degree angle otp_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mtpmark_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mtpmark</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mtpmark_angle</name>
+   <description>ACUTE : non 45 degree angle mtpmark</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>neo_ee_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on neo_ee_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>neo_ee_mk_angle</name>
+   <description>ACUTE : non 45 degree angle neo_ee_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>sramcore_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on sramcore</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>sramcore_angle</name>
+   <description>ACUTE : non 45 degree angle sramcore</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_rf_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on lvs_rf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_rf_angle</name>
+   <description>ACUTE : non 45 degree angle lvs_rf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_drain_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on lvs_drain</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_drain_angle</name>
+   <description>ACUTE : non 45 degree angle lvs_drain</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvpolyrs_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on hvpolyrs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvpolyrs_angle</name>
+   <description>ACUTE : non 45 degree angle hvpolyrs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_io_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on lvs_io</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_io_angle</name>
+   <description>ACUTE : non 45 degree angle lvs_io</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>probe_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on probe_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>probe_mk_angle</name>
+   <description>ACUTE : non 45 degree angle probe_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>esd_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on esd_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>esd_mk_angle</name>
+   <description>ACUTE : non 45 degree angle esd_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_source_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on lvs_source</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_source_angle</name>
+   <description>ACUTE : non 45 degree angle lvs_source</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>well_diode_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on well_diode_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>well_diode_mk_angle</name>
+   <description>ACUTE : non 45 degree angle well_diode_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ldmos_xtor_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ldmos_xtor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ldmos_xtor_angle</name>
+   <description>ACUTE : non 45 degree angle ldmos_xtor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>plfuse_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on plfuse</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>plfuse_angle</name>
+   <description>ACUTE : non 45 degree angle plfuse</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>efuse_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on efuse_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>efuse_mk_angle</name>
+   <description>ACUTE : non 45 degree angle efuse_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mcell_feol_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mcell_feol_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mcell_feol_mk_angle</name>
+   <description>ACUTE : non 45 degree angle mcell_feol_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ymtp_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ymtp_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ymtp_mk_angle</name>
+   <description>ACUTE : non 45 degree angle ymtp_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dev_wf_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on dev_wf_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dev_wf_mk_angle</name>
+   <description>ACUTE : non 45 degree angle dev_wf_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_blk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal1_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_blk_angle</name>
+   <description>ACUTE : non 45 degree angle metal1_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_blk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal2_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_blk_angle</name>
+   <description>ACUTE : non 45 degree angle metal2_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_blk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal3_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_blk_angle</name>
+   <description>ACUTE : non 45 degree angle metal3_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_blk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal4_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_blk_angle</name>
+   <description>ACUTE : non 45 degree angle metal4_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_blk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal5_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_blk_angle</name>
+   <description>ACUTE : non 45 degree angle metal5_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metalt_blk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metalt_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metalt_blk_angle</name>
+   <description>ACUTE : non 45 degree angle metalt_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pr_bndry_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on pr_bndry</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pr_bndry_angle</name>
+   <description>ACUTE : non 45 degree angle pr_bndry</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mdiode_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mdiode</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mdiode_angle</name>
+   <description>ACUTE : non 45 degree angle mdiode</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_res_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal1_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_res_angle</name>
+   <description>ACUTE : non 45 degree angle metal1_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_res_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal2_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_res_angle</name>
+   <description>ACUTE : non 45 degree angle metal2_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_res_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal3_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_res_angle</name>
+   <description>ACUTE : non 45 degree angle metal3_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_res_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal4_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_res_angle</name>
+   <description>ACUTE : non 45 degree angle metal4_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_res_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal5_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_res_angle</name>
+   <description>ACUTE : non 45 degree angle metal5_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal6_res_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal6_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal6_res_angle</name>
+   <description>ACUTE : non 45 degree angle metal6_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>border_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on border</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>border_angle</name>
+   <description>ACUTE : non 45 degree angle border</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>

diff --git a/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..b3fc698
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml

@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/gf180mcu_density.lydrc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>comp.density</name>
+   <description>0.7 max comp density</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>

diff --git a/mpw_precheck/outputs/reports/klayout_offgrid_check.xml b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..b73ff41
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml

@@ -0,0 +1,2535 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>DRC Run Report at</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/gf180mcuC_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>MC.1</name>
+   <description>MC.1 : min. mcell width : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MC.2</name>
+   <description>MC.2 : min. mcell spacing : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MC.3</name>
+   <description>MC.3 : Minimum Mcell area : 0.35µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MC.4</name>
+   <description>MC.4 : Minimum area enclosed by Mcell : 0.35µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.1</name>
+   <description>PRES.1 : Minimum width of Poly2 resistor. : 0.8µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.2</name>
+   <description>PRES.2 : Minimum space between Poly2 resistors. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.3</name>
+   <description>PRES.3 : Minimum space from Poly2 resistor to COMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.4</name>
+   <description>PRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.5</name>
+   <description>PRES.5 : Minimum Plus implant overlap of Poly2 resistor. : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.6</name>
+   <description>PRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction. : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.7</name>
+   <description>PRES.7 : Space from salicide block to contact on Poly2 resistor.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.9a</name>
+   <description>PRES.9a : Pplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>PRES.9b</name>
+   <description>PRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.1</name>
+   <description>LRES.1 : Minimum width of Poly2 resistor. : 0.8µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.2</name>
+   <description>LRES.2 : Minimum space between Poly2 resistors. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.3</name>
+   <description>LRES.3 : Minimum space from Poly2 resistor to COMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.4</name>
+   <description>LRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.5</name>
+   <description>LRES.5 : Minimum Nplus implant overlap of Poly2 resistor. : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.6</name>
+   <description>LRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction. : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.7</name>
+   <description>LRES.7 : Space from salicide block to contact on Poly2 resistor.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.9a</name>
+   <description>LRES.9a : Nplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2. </description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LRES.9b</name>
+   <description>LRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.1</name>
+   <description>HRES.1 : Minimum space. Note : Merge if the spacing is less than 0.4 um. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.2</name>
+   <description>HRES.2 : Minimum width of Poly2 resistor. : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.3</name>
+   <description>HRES.3 : Minimum space between Poly2 resistors. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.4</name>
+   <description>HRES.4 : Minimum RESISTOR overlap of Poly2 resistor. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.5</name>
+   <description>HRES.5 : Minimum RESISTOR space to unrelated Poly2. : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.6</name>
+   <description>HRES.6 : Minimum RESISTOR space to COMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.7</name>
+   <description>HRES.7 : Minimum Pplus overlap of contact on Poly2 resistor. : 0.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.8</name>
+   <description>HRES.8 : Space from salicide block to contact on Poly2 resistor.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.9</name>
+   <description>HRES.9 : Minimum salicide block overlap of Poly2 resistor in width direction.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.10</name>
+   <description>HRES.10 : Minimum &amp; maximum Pplus overlap of SAB.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.12a</name>
+   <description>HRES.12a : P type Poly2 resistor (high sheet rho) shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by Pplus space) and width covering the width of Poly2. </description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>HRES.12b</name>
+   <description>HRES.12b : If the size of single RES_MK mark layer is greater than 15000 um2 and both side (X and Y) are greater than 80 um. Then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.1</name>
+   <description>MIMTM.1 : Minimum MiM bottom plate spacing to the bottom plate metal (whether adjacent MiM or routing metal). : 1.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.2</name>
+   <description>MIMTM.2 : Minimum MiM bottom plate overlap of Vian-1 layer. [This is applicable for Vian-1 within 1.06um oversize of FuseTop layer (referenced to virtual bottom plate)]. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.3</name>
+   <description>MIMTM.3 : Minimum MiM bottom plate overlap of Top plate.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.4</name>
+   <description>MIMTM.4 : Minimum MiM top plate (FuseTop) overlap of Vian-1. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.5</name>
+   <description>MIMTM.5 : Minimum spacing between top plate and the Vian-1 connecting to the bottom plate. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.6</name>
+   <description>MIMTM.6 : Minimum spacing between unrelated top plates. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.7</name>
+   <description>MIMTM.7 : Min FuseTop enclosure by CAP_MK.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.8a</name>
+   <description>MIMTM.8a : Minimum MIM cap area (defined by FuseTop area) (um2). : 25µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.8b</name>
+   <description>MIMTM.8b : Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required) (um2). : 10000µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.9</name>
+   <description>MIMTM.9 : Min. Via (Vian-1) spacing for sea of Via on MIM top plate. : 0.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.10</name>
+   <description>MIMTM.10 : (a) There cannot be any Vian-2 touching MIM bottom plate Metaln-1. (b) MIM bottom plate Metaln-1 can only be connected through the higher Via (Vian-1).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MIMTM.11</name>
+   <description>MIMTM.11 : Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed MIMTM.8b rule. : -µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.1</name>
+   <description>NAT.1 : Min. NAT Overlap of COMP of Native Vt NMOS. : 2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.2</name>
+   <description>NAT.2 : Space to unrelated COMP (outside NAT). : 0.3µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.3</name>
+   <description>NAT.3 : Space to NWell edge. : 0.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.4</name>
+   <description>NAT.4 : Minimum channel length for 3.3V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.5</name>
+   <description>NAT.5 : Minimum channel length for 6.0V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.6</name>
+   <description>NAT.6 : Two or more COMPs if connected to different potential are not allowed under same NAT layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.7</name>
+   <description>NAT.7 : Minimum NAT to NAT spacing. : 0.74µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.8</name>
+   <description>NAT.8 : Min. Dualgate overlap of NAT (for 5V/6V) native VT NMOS only.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.9</name>
+   <description>NAT.9 : Poly interconnect under NAT layer is not allowed, minimum spacing of un-related poly from the NAT layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.10</name>
+   <description>NAT.10 : Nwell, inside NAT layer are not allowed.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.11</name>
+   <description>NAT.11 : NCOMP not intersecting to Poly2, is not allowed inside NAT layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>NAT.12</name>
+   <description>NAT.12 : Poly2 not intersecting with COMP is not allowed inside NAT (Poly2 resistor is not allowed inside NAT).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>BJT.1</name>
+   <description>BJT.1 : Min. DRC_BJT overlap of DNWELL for NPN BJT.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>BJT.2</name>
+   <description>BJT.2 : Min. DRC_BJT overlap of PCOM in Psub.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>BJT.3</name>
+   <description>BJT.3 : Minimum space of DRC_BJT layer to unrelated COMP. : 0.1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DE.2</name>
+   <description>DE.2 : Minimum NDMY or PMNDMY size (x or y dimension in um). : 0.8µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DE.3</name>
+   <description>DE.3 : If size greater than 15000 um2 then two sides should not be greater than (um).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>DE.4</name>
+   <description>DE.4 : Minimum NDMY to NDMY space (Merge if space is less). : 20µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>LVS_BJT.1</name>
+   <description>LVS_BJT.1 : Minimum LVS_BJT enclosure of NPN or PNP Emitter COMP layers</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.DF.3a</name>
+   <description>O.DF.3a : Min. COMP Space. P-substrate tap (PCOMP outside NWELL) can be butted for different voltage devices as the potential is same. : 0.24µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.DF.6</name>
+   <description>O.DF.6 : Min. COMP extend beyond poly2 (it also means source/drain overhang). : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.DF.9</name>
+   <description>O.DF.9 : Min. COMP area (um2). : 0.1444µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.PL.2</name>
+   <description>O.PL.2 : Min. poly2 width. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.PL.3a</name>
+   <description>O.PL.3a : Min. poly2 Space on COMP. : 0.18µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.PL.4</name>
+   <description>O.PL.4 : Min. extension beyond COMP to form Poly2 end cap. : 0.14µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.2</name>
+   <description>O.SB.2 : Min. salicide Block Space. : 0.28µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.3</name>
+   <description>O.SB.3 : Min. space from salicide block to unrelated COMP. : 0.09µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.4</name>
+   <description>O.SB.4 : Min. space from salicide block to contact.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.5b_3.3V</name>
+   <description>O.SB.5b_3.3V : Min. space from salicide block to unrelated Poly2 on COMP. : 0.1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.9</name>
+   <description>O.SB.9 : Min. salicide block extension beyond unsalicided Poly2. : 0.1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.11</name>
+   <description>O.SB.11 : Min. salicide block overlap with COMP. : 0.04µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.13_3.3V</name>
+   <description>O.SB.13_3.3V : Min. area of silicide block (um2). : 1.488µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.SB.13_5V</name>
+   <description>O.SB.13_5V : Min. area of silicide block (um2). : 2µm²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.CO.7</name>
+   <description>O.CO.7 : Min. space from COMP contact to Poly2 on COMP. : 0.13µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>O.PL.ORT</name>
+   <description>O.PL.ORT : Orientation-restricted gates must have the gate width aligned along the X-axis (poly line running horizontally) in reference to wafer notch down. : 0µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.01</name>
+   <description>EF.01 : Min. (Poly2 butt PLFUSE) within EFUSE_MK and Pplus.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.02</name>
+   <description>EF.02 : Min. Max. PLFUSE width. : 0.18µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.03</name>
+   <description>EF.03 : Min. Max. PLFUSE length. : 1.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.04a</name>
+   <description>EF.04a : Min. Max. PLFUSE overlap Poly2 (coinciding permitted) and touch cathode and anode.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.04b</name>
+   <description>EF.04b : PLFUSE must be rectangular. : -µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.04c</name>
+   <description>EF.04c : Cathode Poly2 must be rectangular. : -µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.04d</name>
+   <description>EF.04d : Anode Poly2 must be rectangular. : -µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.05</name>
+   <description>EF.05 : Min./Max. LVS_Source overlap Poly2 (at Anode).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.06</name>
+   <description>EF.06 : Min./Max. Cathode Poly2 width. : 2.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.07</name>
+   <description>EF.07 : Min./Max. Cathode Poly2 length. : 1.84µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.08</name>
+   <description>EF.08 : Min./Max. Anode Poly2 width. : 1.06µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.09</name>
+   <description>EF.09 : Min./Max. Anode Poly2 length. : 2.43µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.10</name>
+   <description>EF.10 : Min. Cathode Poly2 to Poly2 space. : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.11</name>
+   <description>EF.11 : Min. Anode Poly2 to Poly2 space. : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.12</name>
+   <description>EF.12 : Min. Space of Cathode Contact to PLFUSE end.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.13</name>
+   <description>EF.13 : Min. Space of Anode Contact to PLFUSE end.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.14</name>
+   <description>EF.14 : Min. EFUSE_MK enclose LVS_Source.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.15</name>
+   <description>EF.15 : NO Contact is allowed to touch PLFUSE.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.16a</name>
+   <description>EF.16a : Cathode must contain exact number of Contacts at each ends. : 4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.16b</name>
+   <description>EF.16b : Anode must contain exact number of Contacts at each ends. : 4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.17</name>
+   <description>EF.17 : Min. Space of EFUSE_MK to EFUSE_MK. : 0.26µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.18</name>
+   <description>EF.18 : PLFUSE must sit on field oxide (NOT COMP), no cross with any COMP, Nplus, Pplus, ESD, SAB, Resistor, Metal1, Metal2.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.19</name>
+   <description>EF.19 : Min. PLFUSE space to Metal1, Metal2.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.20</name>
+   <description>EF.20 : Min. PLFUSE space to COMP, Nplus, Pplus, Resistor, ESD, SAB. : 2.73µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.21</name>
+   <description>EF.21 : Min./Max. eFUSE Poly2 length. : 5.53µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.22a</name>
+   <description>EF.22a : Min./Max. Cathode Poly2 overlap with PLFUSE in width direction. : 1.04µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>EF.22b</name>
+   <description>EF.22b : Min./Max. Anode Poly2 overlap with PLFUSE in width direction. : 0.44µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.1</name>
+   <description>MDN.1 : Min MVSD width (for litho purpose). : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.2a</name>
+   <description>MDN.2a : Min MVSD space [Same Potential]. : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.2b</name>
+   <description>MDN.2b : Min MVSD space [Diff Potential]. : 2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.3a</name>
+   <description>MDN.3a : Min transistor channel length. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.3b</name>
+   <description>MDN.3b : Max transistor channel length: 20 um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.4a</name>
+   <description>MDN.4a : Min transistor channel width. : 4 µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.4b</name>
+   <description>MDN.4b : Max transistor channel width. : 50 um </description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.5ai</name>
+   <description>MDN.5ai : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap non-butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.5aii</name>
+   <description>MDN.5aii : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed. : 0.92µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.5b</name>
+   <description>MDN.5b : Min PCOMP (Pplus AND COMP) space to LDNMOS Source (Nplus AND COMP). Use butted source and p-substrate tab otherwise and that is good for Latch-up immunity as well.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.5c</name>
+   <description>MDN.5c : Maximum distance of the nearest edge of the substrate tab from NCOMP edge. : 15µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.6</name>
+   <description>MDN.6 : ALL LDNMOS shall be covered by Dualgate layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.6a</name>
+   <description>MDN.6a : Min Dualgate enclose NCOMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.7</name>
+   <description>MDN.7 : Each LDNMOS shall be covered by LDMOS_XTOR (GDS#226) mark layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.7a</name>
+   <description>MDN.7a : Min LDMOS_XTOR enclose Dualgate.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.8a</name>
+   <description>MDN.8a : Min LDNMOS drain MVSD space to any other equal potential Nwell space.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.8b</name>
+   <description>MDN.8b : Min LDNMOS drain MVSD space to any other different potential Nwell space.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.9</name>
+   <description>MDN.9 : Min LDNMOS drain MVSD space to NCOMP (Nplus AND COMP) outside LDNMOS drain MVSD. : 4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10a</name>
+   <description>MDN.10a : Min LDNMOS POLY2 width. : 1.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10b</name>
+   <description>MDN.10b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDNMOS drain direction). : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10c</name>
+   <description>MDN.10c : Min/Max POLY2 extension beyond COMP on the field towards LDNMOS drain COMP direction.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10d</name>
+   <description>MDN.10d : Min/Max POLY2 on field space to LDNMOS drain COMP.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10ei</name>
+   <description>MDN.10ei : Min POLY2 space to Psub tap (source and body tap non-butted).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10eii</name>
+   <description>MDN.10eii : Min POLY2 space to Psub tap (source and body tap butted). : 0.32µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.10f</name>
+   <description>MDN.10f : Poly2 interconnect in HV region (LDMOS_XTOR marked region) not allowed. Also, any Poly2 interconnect with poly2 to substrate potential greater than 6V is not allowed.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.11</name>
+   <description>MDN.11 : Min/Max MVSD overlap channel COMP ((((LDMOS_XTOR AND MVSD) AND COMP) AND POLY2) AND NPlus).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.12</name>
+   <description>MDN.12 : Min MVSD enclose NCOMP in the LDNMOS drain and in the direction along the transistor width.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.13a</name>
+   <description>MDN.13a : Max single finger width. : 50µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.13b</name>
+   <description>MDN.13b : Layout shall have alternative source &amp; drain.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.13c</name>
+   <description>MDN.13c : Both sides of the transistor shall be terminated by source.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.13d</name>
+   <description>MDN.13d : Every two poly fingers shall be surrounded by a P-sub guard ring. (Exclude the case when each LDNMOS transistor have full width butting to well tap).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.14</name>
+   <description>MDN.14 : Min MVSD space to any DNWELL.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.15a</name>
+   <description>MDN.15a : Min LDNMOS drain COMP width. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.15b</name>
+   <description>MDN.15b : Min LDNMOS drain COMP enclose contact. : 0µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDN.17</name>
+   <description>MDN.17 : It is recommended to surround the LDNMOS transistor with non-broken Psub guard ring to improve the latch up immunity. Guideline to improve the latch up immunity.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.1</name>
+   <description>MDP.1 : Minimum transistor channel length. : 0.6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.1a</name>
+   <description>MDP.1a : Max transistor channel length.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.2</name>
+   <description>MDP.2 : Minimum transistor channel width. : 4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.3</name>
+   <description>MDP.3 : Each LDPMOS shall be surrounded by non-broken Nplus guard ring inside DNWELL</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.3ai</name>
+   <description>MDP.3ai : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap non-butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.3aii</name>
+   <description>MDP.3aii : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.3b</name>
+   <description>MDP.3b : Min NCOMP (Nplus AND COMP) space to PCOMP in DNWELL (Pplus AND COMP AND DNWELL). Use butted source and DNWELL contacts otherwise and that is best for Latch-up immunity as well. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.3c</name>
+   <description>MDP.3c : Maximum distance of the nearest edge of the DNWELL tab (NCOMP inside DNWELL) from PCOMP edge (PCOMP inside DNWELL). : 15µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.3d</name>
+   <description>MDP.3d : The metal connection for the Nplus guard ring recommended to be continuous. The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability. : 10µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.4</name>
+   <description>MDP.4 : DNWELL covering LDPMOS shall be surrounded by non broken Pplus guard. The metal connection for the Pplus guard ring recommended to be continuous, The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.4a</name>
+   <description>MDP.4a : Min PCOMP (Pplus AND COMP) space to DNWELL. : 2.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.4b</name>
+   <description>MDP.4b : Maximum distance of the nearest edge of the DNWELL from the PCOMP Guard ring outside DNWELL. : 15µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.5</name>
+   <description>MDP.5 : Each LDPMOS shall be covered by Dualgate layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.5a</name>
+   <description>MDP.5a : Minimum Dualgate enclose Plus guarding ring PCOMP (Pplus AND COMP). : 0.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.6</name>
+   <description>MDP.6 : Each LDPMOS shall be covered by LDMOS_XTOR (GDS#226) layer.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.6a</name>
+   <description>MDP.6a : Minimum LDMOS_XTOR enclose Dualgate.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.7</name>
+   <description>MDP.7 : Minimum LDMOS_XTOR layer space to Nwell outside LDMOS_XTOR. : 2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.8</name>
+   <description>MDP.8 : Minimum LDMOS_XTOR layer space to NCOMP outside LDMOS_XTOR. : 1.5µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9a</name>
+   <description>MDP.9a : Min LDPMOS POLY2 width. : 1.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9b</name>
+   <description>MDP.9b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDMOS drain direction). : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9c</name>
+   <description>MDP.9c : Min/Max POLY2 extension beyond COMP on the field towards LDPMOS drain (MVPSD AND COMP AND Pplus NOT POLY2) direction.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9d</name>
+   <description>MDP.9d : Min/Max POLY2 on field to LDPMOS drain COMP (MVPSD AND COMP AND Pplus NOT POLY2) space.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9ei</name>
+   <description>MDP.9ei : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap non-butted).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9eii</name>
+   <description>MDP.9eii : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap butted).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.9f</name>
+   <description>MDP.9f : Poly2 interconnect is not allowed in LDPMOS region (LDMOS_XTOR marked region). : -µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.10</name>
+   <description>MDP.10 : Min/Max MVPSD overlap onto the channel (LDMOS_XTOR AND COMP AND POLY2 AND Pplus).</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.10a</name>
+   <description>MDP.10a : Min MVPSD space within LDMOS_XTOR marking [diff potential]. : 2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.10b</name>
+   <description>MDP.10b : Min MVPSD space [same potential]. Merge if space less than 1um. : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.11</name>
+   <description>MDP.11 : Min MVPSD enclosing PCOMP in the drain (MVPSD AND COMP NOT POLY2) direction and in the direction along the transistor width.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.12</name>
+   <description>MDP.12 : Min DNWELL enclose Nplus guard ring (NCOMP). : 0.66µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.13a</name>
+   <description>MDP.13a : Max single finger width. : 50µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.13b</name>
+   <description>MDP.13b : Layout shall have alternative source &amp; drain.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.13c</name>
+   <description>MDP.13c : Both sides of the transistor shall be terminated by source.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.15</name>
+   <description>MDP.15 : Min DNWELL enclosing MVPSD to any DNWELL spacing. : 6µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.16a</name>
+   <description>MDP.16a : Min LDPMOS drain COMP width. : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.16b</name>
+   <description>MDP.16b : Min LDPMOS drain COMP enclose contact. : 0µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.17a</name>
+   <description>MDP.17a : For better latch up immunity, it is necessary to put DNWELL guard ring between MVPSD Inside DNWELL covered by LDMOS_XTOR and NCOMP (outside DNWELL and outside Nwell) when spacing between them is less than 40um.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>MDP.17c</name>
+   <description>MDP.17c : DNWELL guard ring shall have NCOMP tab to be connected to highest potential</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.NW.2b_3.3V</name>
+   <description>Y.NW.2b_3.3V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.NW.2b_5V</name>
+   <description>Y.NW.2b_5V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.DF.6_5V</name>
+   <description>Y.DF.6_5V : Min. COMP extend beyond gate (it also means source/drain overhang) inside YMTP_MK. : 0.15µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.DF.16_3.3V</name>
+   <description>Y.DF.16_3.3V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.27µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.DF.16_5V</name>
+   <description>Y.DF.16_5V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.23µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.1_3.3V</name>
+   <description>Y.PL.1_3.3V : Interconnect Width (inside YMTP_MK). : 0.13µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.1_5V</name>
+   <description>Y.PL.1_5V : Interconnect Width (inside YMTP_MK). This rule is currently not applicable for 5V.</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.2_3.3V</name>
+   <description>Y.PL.2_3.3V : Gate Width (Channel Length) (inside YMTP_MK). : 0.13µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.2_5V</name>
+   <description>Y.PL.2_5V : Gate Width (Channel Length) (inside YMTP_MK). : 0.47µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.4_5V</name>
+   <description>Y.PL.4_5V : Poly2 extension beyond COMP to form Poly2 end cap (inside YMTP_MK). : 0.16µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.5a_3.3V</name>
+   <description>Y.PL.5a_3.3V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.04µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.5a_5V</name>
+   <description>Y.PL.5a_5V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.5b_3.3V</name>
+   <description>Y.PL.5b_3.3V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.04µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>Y.PL.5b_5V</name>
+   <description>Y.PL.5b_5V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.2µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.4c_MV</name>
+   <description>S.DF.4c_MV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.45µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.6_MV</name>
+   <description>S.DF.6_MV : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.32µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.7_MV</name>
+   <description>S.DF.7_MV : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.45µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.8_MV</name>
+   <description>S.DF.8_MV : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.45µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.16_MV</name>
+   <description>S.DF.16_MV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.45µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.PL.5a_MV</name>
+   <description>S.PL.5a_MV : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.12µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.PL.5b_MV</name>
+   <description>S.PL.5b_MV : Space from field Poly2 to related COMP. : 0.12µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.CO.4_MV</name>
+   <description>S.CO.4_MV : COMP overlap of contact. : 0.04µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.4c_LV</name>
+   <description>S.DF.4c_LV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.DF.16_LV</name>
+   <description>S.DF.16_LV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.4µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.CO.3_LV</name>
+   <description>S.CO.3_LV : Poly2 overlap of contact. : 0.04µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.CO.4_LV</name>
+   <description>S.CO.4_LV : COMP overlap of contact. : 0.03µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.CO.6_ii_LV</name>
+   <description>S.CO.6_ii_LV : (ii) If Metal1 overlaps contact by &lt; 0.04um on one side, adjacent metal1 edges overlap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>S.M1.1_LV</name>
+   <description>S.M1.1_LV : min. metal1 width : 0.22µm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>comp_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on comp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>comp_angle</name>
+   <description>ACUTE : non 45 degree angle comp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_angle</name>
+   <description>ACUTE : non 45 degree angle dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_angle</name>
+   <description>ACUTE : non 45 degree angle nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvpwell_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on lvpwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvpwell_angle</name>
+   <description>ACUTE : non 45 degree angle lvpwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dualgate_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on dualgate</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dualgate_angle</name>
+   <description>ACUTE : non 45 degree angle dualgate</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly2_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on poly2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly2_angle</name>
+   <description>ACUTE : non 45 degree angle poly2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nplus_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on nplus</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nplus_angle</name>
+   <description>ACUTE : non 45 degree angle nplus</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pplus_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on pplus</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pplus_angle</name>
+   <description>ACUTE : non 45 degree angle pplus</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>sab_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on sab</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>sab_angle</name>
+   <description>ACUTE : non 45 degree angle sab</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>esd_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on esd</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>esd_angle</name>
+   <description>ACUTE : non 45 degree angle esd</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>contact_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on contact</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>contact_angle</name>
+   <description>ACUTE : non 45 degree angle contact</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_angle</name>
+   <description>ACUTE : non 45 degree angle metal1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via1_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on via1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via1_angle</name>
+   <description>ACUTE : non 45 degree angle via1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_angle</name>
+   <description>ACUTE : non 45 degree angle metal2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_angle</name>
+   <description>ACUTE : non 45 degree angle via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_angle</name>
+   <description>ACUTE : non 45 degree angle metal3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_angle</name>
+   <description>ACUTE : non 45 degree angle via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_angle</name>
+   <description>ACUTE : non 45 degree angle metal4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_angle</name>
+   <description>ACUTE : non 45 degree angle via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_angle</name>
+   <description>ACUTE : non 45 degree angle metal5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via5_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on via5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via5_angle</name>
+   <description>ACUTE : non 45 degree angle via5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metaltop</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_angle</name>
+   <description>ACUTE : non 45 degree angle metaltop</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_angle</name>
+   <description>ACUTE : non 45 degree angle pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>resistor_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on resistor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>resistor_angle</name>
+   <description>ACUTE : non 45 degree angle resistor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>fhres_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on fhres</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>fhres_angle</name>
+   <description>ACUTE : non 45 degree angle fhres</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>fusetop_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on fusetop</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>fusetop_angle</name>
+   <description>ACUTE : non 45 degree angle fusetop</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>fusewindow_d_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on fusewindow_d</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>fusewindow_d_angle</name>
+   <description>ACUTE : non 45 degree angle fusewindow_d</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>polyfuse_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on polyfuse</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>polyfuse_angle</name>
+   <description>ACUTE : non 45 degree angle polyfuse</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mvsd_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mvsd</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mvsd_angle</name>
+   <description>ACUTE : non 45 degree angle mvsd</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mvpsd_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mvpsd</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mvpsd_angle</name>
+   <description>ACUTE : non 45 degree angle mvpsd</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nat_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on nat</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nat_angle</name>
+   <description>ACUTE : non 45 degree angle nat</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>comp_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on comp_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>comp_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle comp_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly2_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on poly2_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly2_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle poly2_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal1_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle metal1_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal2_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle metal2_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal3_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle metal3_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal4_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle metal4_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal5_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle metal5_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_dummy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metaltop_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_dummy_angle</name>
+   <description>ACUTE : non 45 degree angle metaltop_dummy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>comp_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on comp_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>comp_label_angle</name>
+   <description>ACUTE : non 45 degree angle comp_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly2_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on poly2_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly2_label_angle</name>
+   <description>ACUTE : non 45 degree angle poly2_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal1_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_label_angle</name>
+   <description>ACUTE : non 45 degree angle metal1_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal2_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_label_angle</name>
+   <description>ACUTE : non 45 degree angle metal2_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal3_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_label_angle</name>
+   <description>ACUTE : non 45 degree angle metal3_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal4_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_label_angle</name>
+   <description>ACUTE : non 45 degree angle metal4_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal5_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_label_angle</name>
+   <description>ACUTE : non 45 degree angle metal5_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_label_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metaltop_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_label_angle</name>
+   <description>ACUTE : non 45 degree angle metaltop_label</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_slot_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal1_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_slot_angle</name>
+   <description>ACUTE : non 45 degree angle metal1_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_slot_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal2_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_slot_angle</name>
+   <description>ACUTE : non 45 degree angle metal2_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_slot_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal3_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_slot_angle</name>
+   <description>ACUTE : non 45 degree angle metal3_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_slot_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal4_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_slot_angle</name>
+   <description>ACUTE : non 45 degree angle metal4_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_slot_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal5_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_slot_angle</name>
+   <description>ACUTE : non 45 degree angle metal5_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_slot_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metaltop_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metaltop_slot_angle</name>
+   <description>ACUTE : non 45 degree angle metaltop_slot</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ubmpperi_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ubmpperi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ubmpperi_angle</name>
+   <description>ACUTE : non 45 degree angle ubmpperi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ubmparray_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ubmparray</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ubmparray_angle</name>
+   <description>ACUTE : non 45 degree angle ubmparray</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ubmeplate_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ubmeplate</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ubmeplate_angle</name>
+   <description>ACUTE : non 45 degree angle ubmeplate</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>schottky_diode_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on schottky_diode</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>schottky_diode_angle</name>
+   <description>ACUTE : non 45 degree angle schottky_diode</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>zener_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on zener</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>zener_angle</name>
+   <description>ACUTE : non 45 degree angle zener</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>res_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on res_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>res_mk_angle</name>
+   <description>ACUTE : non 45 degree angle res_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>opc_drc_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on opc_drc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>opc_drc_angle</name>
+   <description>ACUTE : non 45 degree angle opc_drc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ndmy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ndmy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ndmy_angle</name>
+   <description>ACUTE : non 45 degree angle ndmy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pmndmy_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on pmndmy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pmndmy_angle</name>
+   <description>ACUTE : non 45 degree angle pmndmy</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>v5_xtor_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on v5_xtor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>v5_xtor_angle</name>
+   <description>ACUTE : non 45 degree angle v5_xtor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on cap_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap_mk_angle</name>
+   <description>ACUTE : non 45 degree angle cap_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mos_cap_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mos_cap_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mos_cap_mk_angle</name>
+   <description>ACUTE : non 45 degree angle mos_cap_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ind_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ind_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ind_mk_angle</name>
+   <description>ACUTE : non 45 degree angle ind_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diode_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on diode_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diode_mk_angle</name>
+   <description>ACUTE : non 45 degree angle diode_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>drc_bjt_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on drc_bjt</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>drc_bjt_angle</name>
+   <description>ACUTE : non 45 degree angle drc_bjt</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_bjt_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on lvs_bjt</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_bjt_angle</name>
+   <description>ACUTE : non 45 degree angle lvs_bjt</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mim_l_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mim_l_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mim_l_mk_angle</name>
+   <description>ACUTE : non 45 degree angle mim_l_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>latchup_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on latchup_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>latchup_mk_angle</name>
+   <description>ACUTE : non 45 degree angle latchup_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>guard_ring_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on guard_ring_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>guard_ring_mk_angle</name>
+   <description>ACUTE : non 45 degree angle guard_ring_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>otp_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on otp_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>otp_mk_angle</name>
+   <description>ACUTE : non 45 degree angle otp_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mtpmark_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mtpmark</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mtpmark_angle</name>
+   <description>ACUTE : non 45 degree angle mtpmark</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>neo_ee_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on neo_ee_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>neo_ee_mk_angle</name>
+   <description>ACUTE : non 45 degree angle neo_ee_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>sramcore_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on sramcore</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>sramcore_angle</name>
+   <description>ACUTE : non 45 degree angle sramcore</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_rf_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on lvs_rf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_rf_angle</name>
+   <description>ACUTE : non 45 degree angle lvs_rf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_drain_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on lvs_drain</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_drain_angle</name>
+   <description>ACUTE : non 45 degree angle lvs_drain</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvpolyrs_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on hvpolyrs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvpolyrs_angle</name>
+   <description>ACUTE : non 45 degree angle hvpolyrs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_io_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on lvs_io</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_io_angle</name>
+   <description>ACUTE : non 45 degree angle lvs_io</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>probe_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on probe_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>probe_mk_angle</name>
+   <description>ACUTE : non 45 degree angle probe_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>esd_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on esd_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>esd_mk_angle</name>
+   <description>ACUTE : non 45 degree angle esd_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_source_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on lvs_source</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvs_source_angle</name>
+   <description>ACUTE : non 45 degree angle lvs_source</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>well_diode_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on well_diode_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>well_diode_mk_angle</name>
+   <description>ACUTE : non 45 degree angle well_diode_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ldmos_xtor_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ldmos_xtor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ldmos_xtor_angle</name>
+   <description>ACUTE : non 45 degree angle ldmos_xtor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>plfuse_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on plfuse</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>plfuse_angle</name>
+   <description>ACUTE : non 45 degree angle plfuse</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>efuse_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on efuse_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>efuse_mk_angle</name>
+   <description>ACUTE : non 45 degree angle efuse_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mcell_feol_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mcell_feol_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mcell_feol_mk_angle</name>
+   <description>ACUTE : non 45 degree angle mcell_feol_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ymtp_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on ymtp_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ymtp_mk_angle</name>
+   <description>ACUTE : non 45 degree angle ymtp_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dev_wf_mk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on dev_wf_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dev_wf_mk_angle</name>
+   <description>ACUTE : non 45 degree angle dev_wf_mk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_blk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal1_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_blk_angle</name>
+   <description>ACUTE : non 45 degree angle metal1_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_blk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal2_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_blk_angle</name>
+   <description>ACUTE : non 45 degree angle metal2_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_blk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal3_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_blk_angle</name>
+   <description>ACUTE : non 45 degree angle metal3_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_blk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal4_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_blk_angle</name>
+   <description>ACUTE : non 45 degree angle metal4_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_blk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal5_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_blk_angle</name>
+   <description>ACUTE : non 45 degree angle metal5_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metalt_blk_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metalt_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metalt_blk_angle</name>
+   <description>ACUTE : non 45 degree angle metalt_blk</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pr_bndry_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on pr_bndry</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pr_bndry_angle</name>
+   <description>ACUTE : non 45 degree angle pr_bndry</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mdiode_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on mdiode</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mdiode_angle</name>
+   <description>ACUTE : non 45 degree angle mdiode</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_res_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal1_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal1_res_angle</name>
+   <description>ACUTE : non 45 degree angle metal1_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_res_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal2_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal2_res_angle</name>
+   <description>ACUTE : non 45 degree angle metal2_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_res_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal3_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal3_res_angle</name>
+   <description>ACUTE : non 45 degree angle metal3_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_res_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal4_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal4_res_angle</name>
+   <description>ACUTE : non 45 degree angle metal4_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_res_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal5_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal5_res_angle</name>
+   <description>ACUTE : non 45 degree angle metal5_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal6_res_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on metal6_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>metal6_res_angle</name>
+   <description>ACUTE : non 45 degree angle metal6_res</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>border_OFFGRID</name>
+   <description>OFFGRID : OFFGRID vertex on border</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>border_angle</name>
+   <description>ACUTE : non 45 degree angle border</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>

diff --git a/mpw_precheck/outputs/user_project_wrapper.xor.gds b/mpw_precheck/outputs/user_project_wrapper.xor.gds
new file mode 100644
index 0000000..ce014f0
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.xor.gds
Binary files differ

diff --git a/mpw_precheck/outputs/user_project_wrapper_empty_erased.gds b/mpw_precheck/outputs/user_project_wrapper_empty_erased.gds
new file mode 100644
index 0000000..bc6136f
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper_empty_erased.gds
Binary files differ

diff --git a/mpw_precheck/outputs/user_project_wrapper_erased.gds b/mpw_precheck/outputs/user_project_wrapper_erased.gds
new file mode 100644
index 0000000..3028bfd
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper_erased.gds
Binary files differ

diff --git a/signoff/.gitignore b/signoff/.gitignore
new file mode 100644
index 0000000..6407046
--- /dev/null
+++ b/signoff/.gitignore

@@ -0,0 +1 @@
+cdrcpost/*

diff --git a/signoff/assigned_slot b/signoff/assigned_slot
new file mode 100644
index 0000000..a1d829f
--- /dev/null
+++ b/signoff/assigned_slot

@@ -0,0 +1 @@
+026

diff --git a/signoff/cdrc.log b/signoff/cdrc.log
new file mode 100644
index 0000000..b8e3742
--- /dev/null
+++ b/signoff/cdrc.log

@@ -0,0 +1,2 @@
+caldrc-put: caravel_1800b22e.oas f98fa9553e10951dd16eb6a8434bef53d6274ded 2022-12-13.00:51:26.UTC md5=1f7952a61a7afd21e32e742979a058b1 /mnt/shuttles/gfmpw-0/u9715_ashabar/testasynctrimux/tapeout/outputs/oas/caravel_1800b22e.oas [no-git-push]
+caldrc-post: caravel_1800b22e.gds put=f98fa955 2022-12-13.02:03:30.UTC md5=(no-gds-file) output3321_pdk100-ga2322ad13_drc3221-gf98fa955_prj3221-gf98fa955_caravel_1800b22e

diff --git a/tapeout/logs/gds.info b/tapeout/logs/gds.info
new file mode 100644
index 0000000..1fad91d
--- /dev/null
+++ b/tapeout/logs/gds.info

@@ -0,0 +1 @@
+user_project_wrapper.gds: c6954de5738af2f4c9ef9f64fdbd49d9a0dcbdad
\ No newline at end of file

diff --git a/tapeout/logs/gen_gpio_defaults.log b/tapeout/logs/gen_gpio_defaults.log
new file mode 100644
index 0000000..0106ab6
--- /dev/null
+++ b/tapeout/logs/gen_gpio_defaults.log

@@ -0,0 +1,79 @@
+Step 1:  Create new cells for new GPIO default vectors.
+Creating new layout file /root/project/mag/gpio_defaults_block_009.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_009.v
+Layout file /root/project/mag/gpio_defaults_block_009.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_009.v already exists and does not need to be generated.
+Creating new layout file /root/project/mag/gpio_defaults_block_007.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_007.v
+Creating new layout file /root/project/mag/gpio_defaults_block_087.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_087.v
+Layout file /root/project/mag/gpio_defaults_block_007.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_007.v already exists and does not need to be generated.
+Creating new layout file /root/project/mag/gpio_defaults_block_046.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_046.v
+Layout file /root/project/mag/gpio_defaults_block_046.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_046.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_046.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_046.v already exists and does not need to be generated.
+Creating new layout file /root/project/mag/gpio_defaults_block_006.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v
+Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_006.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_006.v already exists and does not need to be generated.
+Creating new layout file /root/project/mag/gpio_defaults_block_00a.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v
+Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_00a.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_00a.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_046.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_046.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_046.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_046.v already exists and does not need to be generated.
+Step 2:  Modify top-level layouts to use the specified defaults.
+Done.

diff --git a/tapeout/logs/git.info b/tapeout/logs/git.info
new file mode 100644
index 0000000..f1821be
--- /dev/null
+++ b/tapeout/logs/git.info

@@ -0,0 +1,3 @@
+Repository: https://github.com/shaos/tiny_silicon_2.git
+Branch: HEAD
+Commit: c356d427af79874f974a745d18ec667a83fbbdeb
\ No newline at end of file

diff --git a/tapeout/logs/git_clone.log b/tapeout/logs/git_clone.log
new file mode 100644
index 0000000..c54e882
--- /dev/null
+++ b/tapeout/logs/git_clone.log

@@ -0,0 +1,20 @@
+https://github.com/shaos/tiny_silicon_2.git
+Cloning into '/root/project'...
+Note: switching to 'c356d427af79874f974a745d18ec667a83fbbdeb'.
+
+You are in 'detached HEAD' state. You can look around, make experimental
+changes and commit them, and you can discard any commits you make in this
+state without impacting any branches by switching back to a branch.
+
+If you want to create a new branch to retain commits you create, you may
+do so (now or later) by using -c with the switch command. Example:
+
+  git switch -c <new-branch-name>
+
+Or undo this operation with:
+
+  git switch -
+
+Turn off this advice by setting config variable advice.detachedHead to false
+
+HEAD is now at c356d42 harden project [skip ci]

diff --git a/tapeout/logs/klayout_gds2oas.log b/tapeout/logs/klayout_gds2oas.log
new file mode 100644
index 0000000..c726385
--- /dev/null
+++ b/tapeout/logs/klayout_gds2oas.log

@@ -0,0 +1 @@
+[INFO] Changing from /mnt/uffs/user/u9715_ashabar/design/testasynctrimux/jobs/tapeout/47f39457-7de7-4d74-8858-7f273d1fa49c/outputs/caravel_1800b22e.gds to /mnt/uffs/user/u9715_ashabar/design/testasynctrimux/jobs/tapeout/47f39457-7de7-4d74-8858-7f273d1fa49c/outputs/caravel_1800b22e.oas

diff --git a/tapeout/logs/oasis.info b/tapeout/logs/oasis.info
new file mode 100644
index 0000000..7e64466
--- /dev/null
+++ b/tapeout/logs/oasis.info

@@ -0,0 +1 @@
+caravel_1800b22e.oas: 024120ca41e660345034be4630d0e1e7be249df9
\ No newline at end of file

diff --git a/tapeout/logs/pdks.info b/tapeout/logs/pdks.info
new file mode 100644
index 0000000..daefa55
--- /dev/null
+++ b/tapeout/logs/pdks.info

@@ -0,0 +1,2 @@
+Open PDKs: b8c6129fb60851c452a3136c2b8c603bb92cb180
+gf180mcuC PDK: a897aa30369d3bcec87d9d50ce9b01f320f854ef
\ No newline at end of file

diff --git a/tapeout/logs/set_user_id.log b/tapeout/logs/set_user_id.log
new file mode 100644
index 0000000..e710fc5
--- /dev/null
+++ b/tapeout/logs/set_user_id.log

@@ -0,0 +1,10 @@
+Project Chip ID is: 402698798
+Setting Project Chip ID to: 1800b22e
+Step 1: Modify Layout of the user_id_programming subcell
+Done!
+Step 2: Add user project ID parameter to source verilog.
+Done!
+Step 3: Add user project ID parameter to gate-level verilog.
+Done!
+Step 4: Add user project ID text to top level layout.
+Done!

diff --git a/tapeout/logs/ship_truck.log b/tapeout/logs/ship_truck.log
new file mode 100644
index 0000000..04dab1d
--- /dev/null
+++ b/tapeout/logs/ship_truck.log

@@ -0,0 +1,3787 @@
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology gf180mcuC ...
+10 Magic internal units = 1 Lambda
+Input style import: scaleFactor=10, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    obsactive mvobsactive filldiff fillpoly m1hole obsm1 fillm1 obsv1 m2hole obsm2 fillm2 obsv2 m3hole obsm3 fillm3 m4hole obsm4 fillm4 m5hole obsm5 fillm5 glass fillblock lvstext obscomment 
+Scaled tech values by 10 / 1 to match internal grid scaling
+Loading gf180mcuC Device Generator Menu ...
+Loading "/opt/scripts/mag2gds_gf180.tcl" from command line.
+Scaled magic input cell user_project_wrapper geometry by factor of 2
+user_project_wrapper: 10000 rects
+user_project_wrapper: 20000 rects
+user_project_wrapper: 30000 rects
+user_project_wrapper: 40000 rects
+user_project_wrapper: 50000 rects
+user_project_wrapper: 60000 rects
+user_project_wrapper: 70000 rects
+user_project_wrapper: 80000 rects
+user_project_wrapper: 90000 rects
+user_project_wrapper: 100000 rects
+user_project_wrapper: 110000 rects
+user_project_wrapper: 120000 rects
+user_project_wrapper: 130000 rects
+caravel_core: 10000 rects
+caravel_core: 20000 rects
+caravel_core: 30000 rects
+caravel_core: 40000 rects
+caravel_core: 50000 rects
+caravel_core: 60000 rects
+caravel_core: 70000 rects
+caravel_core: 80000 rects
+caravel_core: 90000 rects
+caravel_core: 100000 rects
+caravel_core: 110000 rects
+caravel_core: 120000 rects
+caravel_core: 130000 rects
+caravel_core: 140000 rects
+caravel_core: 150000 rects
+caravel_core: 160000 rects
+caravel_core: 170000 rects
+caravel_core: 180000 rects
+caravel_core: 190000 rects
+caravel_core: 200000 rects
+caravel_core: 210000 rects
+caravel_core: 220000 rects
+caravel_core: 230000 rects
+caravel_core: 240000 rects
+caravel_core: 250000 rects
+caravel_core: 260000 rects
+caravel_core: 270000 rects
+caravel_core: 280000 rects
+caravel_core: 290000 rects
+caravel_core: 300000 rects
+caravel_core: 310000 rects
+caravel_core: 320000 rects
+caravel_core: 330000 rects
+caravel_core: 340000 rects
+caravel_core: 350000 rects
+caravel_core: 360000 rects
+caravel_core: 370000 rects
+caravel_core: 380000 rects
+caravel_core: 390000 rects
+caravel_core: 400000 rects
+caravel_core: 410000 rects
+caravel_core: 420000 rects
+caravel_core: 430000 rects
+caravel_core: 440000 rects
+caravel_core: 450000 rects
+caravel_core: 460000 rects
+caravel_core: 470000 rects
+caravel_core: 480000 rects
+caravel_core: 490000 rects
+caravel_core: 500000 rects
+caravel_core: 510000 rects
+caravel_core: 520000 rects
+caravel_core: 530000 rects
+caravel_core: 540000 rects
+caravel_core: 550000 rects
+caravel_core: 560000 rects
+caravel_core: 570000 rects
+caravel_core: 580000 rects
+caravel_core: 590000 rects
+caravel_core: 600000 rects
+caravel_core: 610000 rects
+caravel_core: 620000 rects
+caravel_core: 630000 rects
+caravel_core: 640000 rects
+caravel_core: 650000 rects
+caravel_core: 660000 rects
+caravel_core: 670000 rects
+caravel_core: 680000 rects
+caravel_core: 690000 rects
+caravel_core: 700000 rects
+caravel_core: 710000 rects
+caravel_core: 720000 rects
+caravel_core: 730000 rects
+caravel_core: 740000 rects
+caravel_core: 750000 rects
+caravel_core: 760000 rects
+caravel_core: 770000 rects
+caravel_core: 780000 rects
+caravel_core: 790000 rects
+caravel_core: 800000 rects
+caravel_core: 810000 rects
+caravel_core: 820000 rects
+caravel_core: 830000 rects
+caravel_core: 840000 rects
+caravel_core: 850000 rects
+caravel_core: 860000 rects
+caravel_core: 870000 rects
+caravel_core: 880000 rects
+caravel_core: 890000 rects
+caravel_core: 900000 rects
+caravel_core: 910000 rects
+caravel_core: 920000 rects
+caravel_core: 930000 rects
+caravel_core: 940000 rects
+caravel_core: 950000 rects
+caravel_core: 960000 rects
+caravel_core: 970000 rects
+caravel_core: 980000 rects
+caravel_core: 990000 rects
+caravel_core: 1000000 rects
+caravel_core: 1010000 rects
+caravel_core: 1020000 rects
+caravel_core: 1030000 rects
+caravel_core: 1040000 rects
+caravel_core: 1050000 rects
+caravel_core: 1060000 rects
+caravel_core: 1070000 rects
+caravel_core: 1080000 rects
+caravel_core: 1090000 rects
+caravel_core: 1100000 rects
+caravel_core: 1110000 rects
+caravel_core: 1120000 rects
+caravel_core: 1130000 rects
+caravel_core: 1140000 rects
+caravel_core: 1150000 rects
+caravel_core: 1160000 rects
+caravel_core: 1170000 rects
+caravel_core: 1180000 rects
+caravel_core: 1190000 rects
+caravel_core: 1200000 rects
+caravel_core: 1210000 rects
+caravel_core: 1220000 rects
+caravel_core: 1230000 rects
+caravel_core: 1240000 rects
+caravel_core: 1250000 rects
+caravel_core: 1260000 rects
+caravel_core: 1270000 rects
+caravel_core: 1280000 rects
+caravel_core: 1290000 rects
+caravel_core: 1300000 rects
+caravel_core: 1310000 rects
+caravel_core: 1320000 rects
+caravel_core: 1330000 rects
+caravel_core: 1340000 rects
+caravel_core: 1350000 rects
+caravel_core: 1360000 rects
+caravel_core: 1370000 rects
+caravel_core: 1380000 rects
+caravel_core: 1390000 rects
+caravel_core: 1400000 rects
+caravel_core: 1410000 rects
+caravel_core: 1420000 rects
+caravel_core: 1430000 rects
+caravel_core: 1440000 rects
+caravel_core: 1450000 rects
+caravel_core: 1460000 rects
+caravel_core: 1470000 rects
+caravel_core: 1480000 rects
+caravel_core: 1490000 rects
+caravel_core: 1500000 rects
+caravel_core: 1510000 rects
+caravel_core: 1520000 rects
+caravel_core: 1530000 rects
+caravel_core: 1540000 rects
+caravel_core: 1550000 rects
+caravel_core: 1560000 rects
+caravel_core: 1570000 rects
+caravel_core: 1580000 rects
+caravel_core: 1590000 rects
+caravel_core: 1600000 rects
+caravel_core: 1610000 rects
+caravel_core: 1620000 rects
+caravel_core: 1630000 rects
+caravel_core: 1640000 rects
+caravel_core: 1650000 rects
+caravel_core: 1660000 rects
+caravel_core: 1670000 rects
+caravel_core: 1680000 rects
+caravel_core: 1690000 rects
+caravel_core: 1700000 rects
+caravel_core: 1710000 rects
+caravel_core: 1720000 rects
+caravel_core: 1730000 rects
+caravel_core: 1740000 rects
+caravel_core: 1750000 rects
+caravel_core: 1760000 rects
+caravel_core: 1770000 rects
+caravel_core: 1780000 rects
+caravel_core: 1790000 rects
+caravel_core: 1800000 rects
+caravel_core: 1810000 rects
+caravel_core: 1820000 rects
+caravel_core: 1830000 rects
+caravel_core: 1840000 rects
+caravel_core: 1850000 rects
+caravel_core: 1860000 rects
+caravel_core: 1870000 rects
+caravel_core: 1880000 rects
+caravel_core: 1890000 rects
+caravel_core: 1900000 rects
+caravel_core: 1910000 rects
+caravel_core: 1920000 rects
+caravel_core: 1930000 rects
+caravel_core: 1940000 rects
+caravel_core: 1950000 rects
+caravel_core: 1960000 rects
+caravel_core: 1970000 rects
+caravel_core: 1980000 rects
+caravel_core: 1990000 rects
+caravel_core: 2000000 rects
+caravel_core: 2010000 rects
+caravel_core: 2020000 rects
+caravel_core: 2030000 rects
+caravel_core: 2040000 rects
+caravel_core: 2050000 rects
+caravel_core: 2060000 rects
+caravel_core: 2070000 rects
+caravel_core: 2080000 rects
+caravel_core: 2090000 rects
+caravel_core: 2100000 rects
+caravel_core: 2110000 rects
+caravel_core: 2120000 rects
+caravel_core: 2130000 rects
+caravel_core: 2140000 rects
+caravel_core: 2150000 rects
+caravel_core: 2160000 rects
+caravel_core: 2170000 rects
+caravel_core: 2180000 rects
+caravel_core: 2190000 rects
+caravel_core: 2200000 rects
+caravel_core: 2210000 rects
+caravel_core: 2220000 rects
+caravel_core: 2230000 rects
+caravel_core: 2240000 rects
+caravel_core: 2250000 rects
+caravel_core: 2260000 rects
+Duplicate cell in caravel_core:  Instance of cell user_project_wrapper is from path /root/project/mag but cell was previously read from the current directory.
+Cell name conflict:  Renaming original cell to user_project_wrapper#0.
+Warning:  Renaming read-only cell "user_project_wrapper"
+Read-only status will be revoked and GDS file pointer removed.
+Duplicate cell in caravel_core:  Instance of cell simple_por is from path /root/project/mag but cell was previously read from /opt/caravel/macros/simple_por/maglef.
+New path does not exist and will be ignored.
+Processing timestamp mismatches: user_id_programmingWarning:  Parent cell lists instance of "spare_logic_block" at bad file path /root/project/mag/spare_logic_block.mag.
+The cell exists in the search paths at spare_logic_block.mag.
+The discovered version will be used.
+, spare_logic_blockWarning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__tiel" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__tiel.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__tiel.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__tielWarning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__tieh" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__tieh.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__tieh.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__tiehWarning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__filltie" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__filltie.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__filltie.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__filltieWarning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__endcap" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__endcap.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__endcap.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__endcapWarning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__fillcap_4Warning:  Parent cell lists instance of "gf180_ram_512x8_wrapper" at bad file path /root/project/mag/gf180_ram_512x8_wrapper.mag.
+The cell exists in the search paths at /opt/caravel/mgmt_core_wrapper/mag/gf180_ram_512x8_wrapper.mag.
+The discovered version will be used.
+gf180_ram_512x8_wrapper: 10000 rects
+, gf180_ram_512x8_wrapper, simple_poruser_project_wrapper: 10000 rects
+user_project_wrapper: 20000 rects
+user_project_wrapper: 30000 rects
+user_project_wrapper: 40000 rects
+user_project_wrapper: 50000 rects
+user_project_wrapper: 60000 rects
+user_project_wrapper: 70000 rects
+user_project_wrapper: 80000 rects
+user_project_wrapper: 90000 rects
+user_project_wrapper: 100000 rects
+user_project_wrapper: 110000 rects
+user_project_wrapper: 120000 rects
+user_project_wrapper: 130000 rects
+user_project_wrapper: 140000 rects
+user_project_wrapper: 150000 rects
+, user_project_wrappertiny_user_project: 10000 rects
+tiny_user_project: 20000 rects
+tiny_user_project: 30000 rects
+Duplicate cell in tiny_user_project:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__antenna.mag is from path /root/project/mag/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in tiny_user_project:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 is from path /root/project/mag/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in tiny_user_project:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fill_1.mag is from path /root/project/mag/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in tiny_user_project:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.mag is from path /root/project/mag/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in tiny_user_project:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.mag is from path /root/project/mag/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in tiny_user_project:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fill_2.mag is from path /root/project/mag/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in tiny_user_project:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.mag is from path /root/project/mag/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in tiny_user_project:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.mag is from path /root/project/mag/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in tiny_user_project:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__endcap is from path /root/project/mag/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in tiny_user_project:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__filltie is from path /root/project/mag/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in tiny_user_project:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1.mag is from path /root/project/mag/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in tiny_user_project:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.mag is from path /root/project/mag/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in tiny_user_project:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.mag is from path /root/project/mag/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in tiny_user_project:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__tiel is from path /root/project/mag/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+, tiny_user_projectWarning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_3" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkbuf_3Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkbuf_1Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkinv_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkinv_1Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fill_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fill_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fill_1.mag.
+The discovered version will be used.
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_1 geometry by factor of 2
+, gf180mcu_fd_sc_mcu7t5v0__fill_1Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fill_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fill_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fill_2.mag.
+The discovered version will be used.
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_2 geometry by factor of 2
+, gf180mcu_fd_sc_mcu7t5v0__fill_2Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_8" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_8.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_8.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__fillcap_8Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_16" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__fillcap_16Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_32" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_32.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_32.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__fillcap_32Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_64" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_64.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_64.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__fillcap_64Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__antenna" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__antenna.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__antenna.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__antennaWarning:  Parent cell lists instance of "housekeeping" at bad file path /root/project/mag/housekeeping.mag.
+The cell exists in the search paths at housekeeping.mag.
+The discovered version will be used.
+housekeeping: 10000 rects
+housekeeping: 20000 rects
+housekeeping: 30000 rects
+housekeeping: 40000 rects
+housekeeping: 50000 rects
+housekeeping: 60000 rects
+housekeeping: 70000 rects
+housekeeping: 80000 rects
+housekeeping: 90000 rects
+housekeeping: 100000 rects
+housekeeping: 110000 rects
+housekeeping: 120000 rects
+housekeeping: 130000 rects
+housekeeping: 140000 rects
+housekeeping: 150000 rects
+housekeeping: 160000 rects
+housekeeping: 170000 rects
+housekeeping: 180000 rects
+housekeeping: 190000 rects
+housekeeping: 200000 rects
+housekeeping: 210000 rects
+housekeeping: 220000 rects
+housekeeping: 230000 rects
+housekeeping: 240000 rects
+housekeeping: 250000 rects
+housekeeping: 260000 rects
+housekeeping: 270000 rects
+housekeeping: 280000 rects
+housekeeping: 290000 rects
+housekeeping: 300000 rects
+housekeeping: 310000 rects
+housekeeping: 320000 rects
+housekeeping: 330000 rects
+housekeeping: 340000 rects
+housekeeping: 350000 rects
+Duplicate cell in housekeeping:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__antenna is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in housekeeping:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fill_2 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in housekeeping:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fill_1 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in housekeeping:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in housekeeping:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in housekeeping:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in housekeeping:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in housekeeping:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in housekeeping:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__endcap is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in housekeeping:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__filltie is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in housekeeping:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in housekeeping:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__tieh is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in housekeeping:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in housekeeping:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+, housekeepingWarning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__buf_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__buf_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__buf_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__buf_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkbuf_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkbuf_2Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dlyb_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dlyb_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dlyb_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dlyb_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_8" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkbuf_8Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__buf_8" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__buf_8.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__buf_8.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__buf_8Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_12" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_12.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_12.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkbuf_12Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffrnq_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffrnq_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffrnq_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dffrnq_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffrnq_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffrnq_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffrnq_2.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dffrnq_2Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffrnq_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffrnq_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffrnq_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dffrnq_1Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffq_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffq_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffq_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dffq_1Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffsnq_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffsnq_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffsnq_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dffsnq_1Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffsnq_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffsnq_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffsnq_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dffsnq_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffsnq_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffsnq_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffsnq_2.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dffsnq_2Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__and2_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__and2_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__and2_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__and2_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__mux2_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__mux2_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__mux2_2.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__mux2_2Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nor2_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__nor2_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__nor2_2.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__nor2_2Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai21_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai21_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai21_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__oai21_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__aoi222_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi222_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi222_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__aoi222_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nand2_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__nand2_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__nand2_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__nand2_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__aoi221_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi221_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi221_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__aoi221_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__aoi22_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi22_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi22_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__aoi22_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__aoi21_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi21_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi21_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__aoi21_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__and3_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__and3_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__and3_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__and3_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai32_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai32_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai32_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__oai32_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nand3_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__nand3_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__nand3_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__nand3_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nor2_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__nor2_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__nor2_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__nor2_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai211_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai211_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai211_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__oai211_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai31_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai31_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai31_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__oai31_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__or2_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__or2_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__or2_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__or2_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai22_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai22_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai22_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__oai22_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__xor2_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xor2_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xor2_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__xor2_1Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__aoi211_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi211_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi211_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__aoi211_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai221_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai221_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai221_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__oai221_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkinv_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_2.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkinv_2Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__inv_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__inv_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__inv_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__inv_1Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai222_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai222_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai222_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__oai222_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__mux2_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__mux2_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__mux2_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__mux2_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__inv_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__inv_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__inv_2.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__inv_2Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__xor2_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xor2_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xor2_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__xor2_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__xor2_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xor2_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xor2_2.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__xor2_2Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__xnor2_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xnor2_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xnor2_2.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__xnor2_2Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__inv_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__inv_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__inv_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__inv_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__xnor2_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xnor2_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xnor2_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__xnor2_1Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkinv_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkinv_4Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkinv_3" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_3.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_3.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkinv_3Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkinv_8" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_8.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_8.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkinv_8Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__inv_3" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__inv_3.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__inv_3.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__inv_3Duplicate cell in gpio_defaults_block_046:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__endcap is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_046:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_046:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__filltie is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_046:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__tieh is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_046:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__tiel is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+, gpio_defaults_block_046Duplicate cell in gpio_defaults_block_00a:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__endcap is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_00a:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_00a:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__filltie is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_00a:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__tieh is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_00a:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__tiel is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+, gpio_defaults_block_00aDuplicate cell in gpio_defaults_block_006:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__endcap is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_006:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_006:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__filltie is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_006:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__tieh is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_006:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__tiel is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+, gpio_defaults_block_006Duplicate cell in gpio_defaults_block_007:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__endcap is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_007:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_007:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__filltie is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_007:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__tieh is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_007:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__tiel is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+, gpio_defaults_block_007Duplicate cell in gpio_defaults_block_087:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__endcap is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_087:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_087:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__filltie is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_087:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__tieh is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_087:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__tiel is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+, gpio_defaults_block_087Duplicate cell in gpio_defaults_block_009:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__endcap is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_009:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_009:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__filltie is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_009:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__tieh is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_009:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__tiel is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+, gpio_defaults_block_009Warning:  Parent cell lists instance of "mprj_io_buffer" at bad file path /root/project/mag/mprj_io_buffer.mag.
+The cell exists in the search paths at mprj_io_buffer.mag.
+The discovered version will be used.
+Duplicate cell in mprj_io_buffer:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__antenna is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in mprj_io_buffer:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in mprj_io_buffer:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fill_2 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in mprj_io_buffer:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fill_1 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in mprj_io_buffer:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in mprj_io_buffer:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in mprj_io_buffer:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in mprj_io_buffer:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in mprj_io_buffer:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__endcap is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in mprj_io_buffer:  Instance of cell gf180mcu_fd_sc_mcu7t5v0__filltie is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+, mprj_io_buffer.
+Processing timestamp mismatches: user_id_textblock, chip_io, open_source, copyright_block, caravel_corecaravel_power_routing: 10000 rects
+caravel_power_routing: 20000 rects
+caravel_power_routing: 30000 rects
+caravel_power_routing: 40000 rects
+caravel_power_routing: 50000 rects
+caravel_power_routing: 60000 rects
+caravel_power_routing: 70000 rects
+caravel_power_routing: 80000 rects
+caravel_power_routing: 90000 rects
+caravel_power_routing: 100000 rects
+caravel_power_routing: 110000 rects
+, caravel_power_routingScaled magic input cell caravel_motto geometry by factor of 2
+, caravel_motto, caravel_logo.
+Scaled magic input cell font_73 geometry by factor of 2
+Scaled magic input cell font_69 geometry by factor of 2
+Scaled magic input cell font_68 geometry by factor of 2
+Scaled magic input cell font_67 geometry by factor of 2
+Scaled magic input cell font_65 geometry by factor of 2
+Scaled magic input cell font_61 geometry by factor of 2
+Scaled magic input cell font_54 geometry by factor of 2
+Scaled magic input cell font_53 geometry by factor of 2
+Scaled magic input cell font_49 geometry by factor of 2
+Scaled magic input cell font_43 geometry by factor of 2
+Scaled magic input cell font_22 geometry by factor of 2
+Scaled magic input cell font_6E geometry by factor of 2
+Scaled magic input cell font_6C geometry by factor of 2
+gf180mcu_fd_ip_sram__sram512x8m8wm1: 10000 rects
+gf180mcu_fd_ip_sram__sram512x8m8wm1: 20000 rects
+Scaled magic input cell pmos_5p043105913020110_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p043105913020105_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p043105913020103_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p043105913020104_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p043105913020108_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p043105913020109_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p043105913020107_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p043105913020106_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302044_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$204401708_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$204400684_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$204399660_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$204398636_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$204147756_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$201252908_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$201251884_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$02_R270_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204408876_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204407852_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204406828_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204405804_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204404780_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204403756_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204402732_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$202406956_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$202394668_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$201262124_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$46894124_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$45004844_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PSUB_05_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PSUB$$45111340_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_POLY243105913020105_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_POLY24310591302033_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_POLY24310591302031_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_POLY24310591302019_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE43105913020106_51_0 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE03_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NWELL4310591302032_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NWELL07_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$01_R270_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$04_R270_512x8m81 geometry by factor of 10
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commit	b2c7723f77f9270e6b4059027b05613a4651f320	[log] [tgz]
author	Jeff DiCorpo <jeffdi@efabless.com>	Mon Dec 12 23:48:36 2022 -0800
committer	Jeff DiCorpo <jeffdi@efabless.com>	Mon Dec 12 23:48:36 2022 -0800
tree	499b4825617756b39ecc9809c8dab96f4f76a52a
parent	c356d427af79874f974a745d18ec667a83fbbdeb [diff]