)]}'
{
  "commit": "9fe4c812dacdcda14f8383ec24327cd9a4e3eef2",
  "tree": "bb06b3aaf00ce9790ff8122b349a05954539406f",
  "parents": [
    "775c034fae5512a618d245c13cb6522547785e6c"
  ],
  "author": {
    "name": "Thorsten Knoll",
    "email": "thorsten_knoll@yahoo.de",
    "time": "Sun Dec 04 23:24:09 2022 +0100"
  },
  "committer": {
    "name": "Thorsten Knoll",
    "email": "thorsten_knoll@yahoo.de",
    "time": "Sun Dec 04 23:24:09 2022 +0100"
  },
  "message": "added 74181 verilog sources\n",
  "tree_diff": [
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      "new_path": "info.yaml"
    },
    {
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      "old_mode": 0,
      "old_path": "/dev/null",
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      "new_path": "verilog/rtl/alu74181.v"
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}