harden project [skip ci]
diff --git a/gds/tiny_user_project.gds b/gds/tiny_user_project.gds
index 16499b0..a69d65d 100644
--- a/gds/tiny_user_project.gds
+++ b/gds/tiny_user_project.gds
Binary files differ
diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds
index fa16443..2a713aa 100644
--- a/gds/user_project_wrapper.gds
+++ b/gds/user_project_wrapper.gds
Binary files differ
diff --git a/mag/tiny_user_project.mag b/mag/tiny_user_project.mag
index 0dd4b37..6f8cba0 100644
--- a/mag/tiny_user_project.mag
+++ b/mag/tiny_user_project.mag
@@ -1,7 +1,7 @@
magic
tech gf180mcuC
magscale 1 10
-timestamp 1670258131
+timestamp 1670258809
<< metal1 >>
rect 102834 132638 102846 132690
rect 102898 132687 102910 132690
diff --git a/mag/user_project_wrapper.mag b/mag/user_project_wrapper.mag
index 2eba9bc..6a9a1f5 100644
--- a/mag/user_project_wrapper.mag
+++ b/mag/user_project_wrapper.mag
@@ -1,7 +1,7 @@
magic
tech gf180mcuC
magscale 1 10
-timestamp 1670258231
+timestamp 1670258909
<< metal1 >>
rect 337698 368286 337710 368338
rect 337762 368335 337774 368338
diff --git a/maglef/tiny_user_project.mag b/maglef/tiny_user_project.mag
index abc22b8..58fcf4a 100644
--- a/maglef/tiny_user_project.mag
+++ b/maglef/tiny_user_project.mag
@@ -1,7 +1,7 @@
magic
tech gf180mcuC
magscale 1 5
-timestamp 1670258133
+timestamp 1670258811
<< obsm1 >>
rect 672 855 59855 66345
<< metal2 >>
@@ -1994,7 +1994,7 @@
string LEFclass BLOCK
string LEFview TRUE
string GDS_END 1703556
-string GDS_FILE /home/runner/work/reversible_programmable_logic_ic/reversible_programmable_logic_ic/openlane/tiny_user_project/runs/22_12_05_16_34/results/signoff/tiny_user_project.magic.gds
+string GDS_FILE /home/runner/work/reversible_programmable_logic_ic/reversible_programmable_logic_ic/openlane/tiny_user_project/runs/22_12_05_16_45/results/signoff/tiny_user_project.magic.gds
string GDS_START 72230
<< end >>
diff --git a/maglef/user_project_wrapper.mag b/maglef/user_project_wrapper.mag
index c098381..b95abb2 100644
--- a/maglef/user_project_wrapper.mag
+++ b/maglef/user_project_wrapper.mag
@@ -1,7 +1,7 @@
magic
tech gf180mcuC
magscale 1 5
-timestamp 1670258236
+timestamp 1670258914
<< obsm1 >>
rect 120353 115879 179855 184169
<< metal2 >>
@@ -2210,7 +2210,7 @@
string LEFclass BLOCK
string LEFview TRUE
string GDS_END 4788644
-string GDS_FILE /home/runner/work/reversible_programmable_logic_ic/reversible_programmable_logic_ic/openlane/user_project_wrapper/runs/22_12_05_16_36/results/signoff/user_project_wrapper.magic.gds
+string GDS_FILE /home/runner/work/reversible_programmable_logic_ic/reversible_programmable_logic_ic/openlane/user_project_wrapper/runs/22_12_05_16_47/results/signoff/user_project_wrapper.magic.gds
string GDS_START 1703610
<< end >>
diff --git a/sdc/tiny_user_project.sdc b/sdc/tiny_user_project.sdc
index 85fc3bc..bf790cf 100644
--- a/sdc/tiny_user_project.sdc
+++ b/sdc/tiny_user_project.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Mon Dec 5 16:35:07 2022
+# Mon Dec 5 16:46:26 2022
###############################################################################
current_design tiny_user_project
###############################################################################
diff --git a/sdc/user_project_wrapper.sdc b/sdc/user_project_wrapper.sdc
index 278fd99..f49904a 100644
--- a/sdc/user_project_wrapper.sdc
+++ b/sdc/user_project_wrapper.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Mon Dec 5 16:36:36 2022
+# Mon Dec 5 16:47:54 2022
###############################################################################
current_design user_project_wrapper
###############################################################################
diff --git a/sdf/multicorner/nom/user_project_wrapper.ff.sdf b/sdf/multicorner/nom/user_project_wrapper.ff.sdf
index cf9a935..fc0ee28 100644
--- a/sdf/multicorner/nom/user_project_wrapper.ff.sdf
+++ b/sdf/multicorner/nom/user_project_wrapper.ff.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "user_project_wrapper")
- (DATE "Mon Dec 5 16:37:08 2022")
+ (DATE "Mon Dec 5 16:48:26 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.2")
diff --git a/sdf/multicorner/nom/user_project_wrapper.ss.sdf b/sdf/multicorner/nom/user_project_wrapper.ss.sdf
index 90cc3e2..1a47f58 100644
--- a/sdf/multicorner/nom/user_project_wrapper.ss.sdf
+++ b/sdf/multicorner/nom/user_project_wrapper.ss.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "user_project_wrapper")
- (DATE "Mon Dec 5 16:37:08 2022")
+ (DATE "Mon Dec 5 16:48:26 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.2")
diff --git a/sdf/multicorner/nom/user_project_wrapper.tt.sdf b/sdf/multicorner/nom/user_project_wrapper.tt.sdf
index 33d5be2..2234f38 100644
--- a/sdf/multicorner/nom/user_project_wrapper.tt.sdf
+++ b/sdf/multicorner/nom/user_project_wrapper.tt.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "user_project_wrapper")
- (DATE "Mon Dec 5 16:37:08 2022")
+ (DATE "Mon Dec 5 16:48:26 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.2")
diff --git a/sdf/tiny_user_project.sdf b/sdf/tiny_user_project.sdf
index fad522e..6a2c47d 100644
--- a/sdf/tiny_user_project.sdf
+++ b/sdf/tiny_user_project.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "tiny_user_project")
- (DATE "Mon Dec 5 16:35:29 2022")
+ (DATE "Mon Dec 5 16:46:47 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.2")
diff --git a/sdf/user_project_wrapper.sdf b/sdf/user_project_wrapper.sdf
index 1cd17c8..0245725 100644
--- a/sdf/user_project_wrapper.sdf
+++ b/sdf/user_project_wrapper.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "user_project_wrapper")
- (DATE "Mon Dec 5 16:37:10 2022")
+ (DATE "Mon Dec 5 16:48:28 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.2")
diff --git a/signoff/tiny_user_project/metrics.csv b/signoff/tiny_user_project/metrics.csv
index 692de2b..d9a470c 100644
--- a/signoff/tiny_user_project/metrics.csv
+++ b/signoff/tiny_user_project/metrics.csv
@@ -1,2 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
-/home/runner/work/reversible_programmable_logic_ic/reversible_programmable_logic_ic/openlane/tiny_user_project,tiny_user_project,22_12_05_16_34,flow completed,0h2m6s0ms,0h1m7s0ms,225.49019607843138,1.632,112.74509803921569,0.51,578.21,184,0,0,0,0,0,0,0,-1,0,-1,-1,10564,537,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,22316895.0,0.0,1.23,1.01,0.0,-1,0.75,76,496,76,496,0,0,0,8,0,0,0,0,0,0,0,8,12,8,2,330,2421,0,2751,379231.776,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,24.0,41.666666666666664,24,AREA 0,4,50,1,153.6,153.18,0.7,0.3,gf180mcu_fd_sc_mcu7t5v0,4
+/home/runner/work/reversible_programmable_logic_ic/reversible_programmable_logic_ic/openlane/tiny_user_project,tiny_user_project,22_12_05_16_45,flow completed,0h2m6s0ms,0h1m6s0ms,225.49019607843138,1.632,112.74509803921569,0.51,586.2,184,0,0,0,0,0,0,0,-1,0,-1,-1,10564,537,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,22316895.0,0.0,1.23,1.01,0.0,-1,0.75,88,508,88,508,0,0,0,8,0,0,0,0,0,0,0,8,12,8,2,330,2421,0,2751,379231.776,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,24.0,41.666666666666664,24,AREA 0,4,50,1,153.6,153.18,0.7,0.3,gf180mcu_fd_sc_mcu7t5v0,4
diff --git a/signoff/user_project_wrapper/metrics.csv b/signoff/user_project_wrapper/metrics.csv
index dee7a97..f5e48fc 100644
--- a/signoff/user_project_wrapper/metrics.csv
+++ b/signoff/user_project_wrapper/metrics.csv
@@ -1,2 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
-/home/runner/work/reversible_programmable_logic_ic/reversible_programmable_logic_ic/openlane/user_project_wrapper,user_project_wrapper,22_12_05_16_36,flow completed,0h1m45s0ms,0h0m41s0ms,-2.0,-1,-1,-1,561.25,1,0,0,0,0,0,0,0,-1,0,-1,-1,964514,1911,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,0.0,-1,0.0,6.08,4.32,0.1,-1,3.51,18,416,18,416,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,8724457.9968,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,24.0,41.666666666666664,24,AREA 0,10,50,1,90,90,0.55,0.3,gf180mcu_fd_sc_mcu7t5v0,0
+/home/runner/work/reversible_programmable_logic_ic/reversible_programmable_logic_ic/openlane/user_project_wrapper,user_project_wrapper,22_12_05_16_47,flow completed,0h1m44s0ms,0h0m41s0ms,-2.0,-1,-1,-1,561.11,1,0,0,0,0,0,0,0,-1,0,-1,-1,964514,1911,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,0.0,-1,0.0,6.08,4.32,0.1,-1,3.51,18,416,18,416,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,8724457.9968,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,24.0,41.666666666666664,24,AREA 0,10,50,1,90,90,0.55,0.3,gf180mcu_fd_sc_mcu7t5v0,0
diff --git a/verilog/rtl/user_module.v b/verilog/rtl/user_module.v
index 5081694..ba08ccf 100644
--- a/verilog/rtl/user_module.v
+++ b/verilog/rtl/user_module.v
@@ -46,154 +46,194 @@
wire net38;
wire net39;
wire net40;
+ wire net41;
+ wire net42;
+ wire net43;
+ wire net44;
+ wire net45;
+ wire net46;
+ wire net47;
+ wire net48;
- assign io_out[0] = net1;
- assign io_out[1] = net13;
- assign io_out[2] = net14;
- assign io_out[3] = net4;
- assign io_out[4] = net15;
- assign io_out[5] = net16;
- assign io_out[6] = net7;
- assign io_out[7] = net17;
- assign io_out[8] = net18;
- assign io_out[9] = net10;
- assign io_out[10] = net19;
- assign io_out[11] = net20;
+ assign io_out[0] = net13;
+ assign io_out[1] = net14;
+ assign io_out[2] = net15;
+ assign io_out[3] = net16;
+ assign io_out[4] = net17;
+ assign io_out[5] = net18;
+ assign io_out[6] = net19;
+ assign io_out[7] = net20;
+ assign io_out[8] = net21;
+ assign io_out[9] = net22;
+ assign io_out[10] = net23;
+ assign io_out[11] = net24;
not_cell not3 (
.in (net10),
- .out (net21)
+ .out (net25)
);
and_cell and9 (
- .a (net21),
+ .a (net25),
.b (net11),
- .out (net22)
+ .out (net26)
);
xor_cell xor5 (
- .a (net22),
- .b (net23),
- .out (net19)
+ .a (net26),
+ .b (net27),
+ .out (net23)
);
and_cell and10 (
.a (net10),
.b (net12),
- .out (net23)
+ .out (net27)
);
and_cell and11 (
- .a (net21),
+ .a (net25),
.b (net12),
- .out (net24)
+ .out (net28)
);
xor_cell xor6 (
- .a (net24),
- .b (net25),
- .out (net20)
+ .a (net28),
+ .b (net29),
+ .out (net24)
);
and_cell and12 (
.a (net10),
.b (net11),
- .out (net25)
+ .out (net29)
);
not_cell not1 (
.in (net7),
- .out (net26)
+ .out (net30)
);
and_cell and1 (
- .a (net26),
+ .a (net30),
.b (net8),
- .out (net27)
+ .out (net31)
);
xor_cell xor1 (
- .a (net27),
- .b (net28),
- .out (net17)
+ .a (net31),
+ .b (net32),
+ .out (net20)
);
and_cell and2 (
.a (net7),
.b (net9),
- .out (net28)
+ .out (net32)
);
and_cell and3 (
- .a (net26),
+ .a (net30),
.b (net9),
- .out (net29)
+ .out (net33)
);
xor_cell xor2 (
- .a (net29),
- .b (net30),
- .out (net18)
+ .a (net33),
+ .b (net34),
+ .out (net21)
);
and_cell and4 (
.a (net7),
.b (net8),
- .out (net30)
+ .out (net34)
);
not_cell not2 (
.in (net4),
- .out (net31)
+ .out (net35)
);
and_cell and5 (
- .a (net31),
+ .a (net35),
.b (net5),
- .out (net32)
+ .out (net36)
);
xor_cell xor3 (
- .a (net32),
- .b (net33),
- .out (net15)
+ .a (net36),
+ .b (net37),
+ .out (net17)
);
and_cell and6 (
.a (net4),
.b (net6),
- .out (net33)
+ .out (net37)
);
and_cell and7 (
- .a (net31),
+ .a (net35),
.b (net6),
- .out (net34)
+ .out (net38)
);
xor_cell xor4 (
- .a (net34),
- .b (net35),
- .out (net16)
+ .a (net38),
+ .b (net39),
+ .out (net18)
);
and_cell and8 (
.a (net4),
.b (net5),
- .out (net35)
+ .out (net39)
);
not_cell not4 (
.in (net1),
- .out (net36)
+ .out (net40)
);
and_cell and13 (
- .a (net36),
+ .a (net40),
.b (net2),
- .out (net37)
+ .out (net41)
);
xor_cell xor7 (
- .a (net37),
- .b (net38),
- .out (net13)
+ .a (net41),
+ .b (net42),
+ .out (net14)
);
and_cell and14 (
.a (net1),
.b (net3),
- .out (net38)
+ .out (net42)
);
and_cell and15 (
- .a (net36),
+ .a (net40),
.b (net3),
- .out (net39)
+ .out (net43)
);
xor_cell xor8 (
- .a (net39),
- .b (net40),
- .out (net14)
+ .a (net43),
+ .b (net44),
+ .out (net15)
);
and_cell and16 (
.a (net1),
.b (net2),
- .out (net40)
+ .out (net44)
+ );
+ not_cell not5 (
+ .in (net1),
+ .out (net45)
+ );
+ not_cell not6 (
+ .in (net45),
+ .out (net13)
+ );
+ not_cell not7 (
+ .in (net4),
+ .out (net46)
+ );
+ not_cell not8 (
+ .in (net46),
+ .out (net16)
+ );
+ not_cell not9 (
+ .in (net7),
+ .out (net47)
+ );
+ not_cell not10 (
+ .in (net47),
+ .out (net19)
+ );
+ not_cell not11 (
+ .in (net10),
+ .out (net48)
+ );
+ not_cell not12 (
+ .in (net48),
+ .out (net22)
);
endmodule
diff --git a/verilog/rtl/wokwi_diagram.json b/verilog/rtl/wokwi_diagram.json
index ad71bc1..75f5a57 100644
--- a/verilog/rtl/wokwi_diagram.json
+++ b/verilog/rtl/wokwi_diagram.json
@@ -44,7 +44,15 @@
{ "type": "wokwi-gate-and-2", "id": "and14", "top": -515.27, "left": 262.45, "attrs": {} },
{ "type": "wokwi-gate-and-2", "id": "and15", "top": -459.7, "left": 263.91, "attrs": {} },
{ "type": "wokwi-gate-xor-2", "id": "xor8", "top": -431.03, "left": 374.03, "attrs": {} },
- { "type": "wokwi-gate-and-2", "id": "and16", "top": -395.79, "left": 265.97, "attrs": {} }
+ { "type": "wokwi-gate-and-2", "id": "and16", "top": -395.79, "left": 265.97, "attrs": {} },
+ { "type": "wokwi-gate-not", "id": "not5", "top": -642.8, "left": 143.84, "attrs": {} },
+ { "type": "wokwi-gate-not", "id": "not6", "top": -641.99, "left": 255.61, "attrs": {} },
+ { "type": "wokwi-gate-not", "id": "not7", "top": -349.19, "left": 153.44, "attrs": {} },
+ { "type": "wokwi-gate-not", "id": "not8", "top": -348.38, "left": 265.21, "attrs": {} },
+ { "type": "wokwi-gate-not", "id": "not9", "top": -61.31, "left": 131.71, "attrs": {} },
+ { "type": "wokwi-gate-not", "id": "not10", "top": -60.5, "left": 243.48, "attrs": {} },
+ { "type": "wokwi-gate-not", "id": "not11", "top": 239.29, "left": 131.64, "attrs": {} },
+ { "type": "wokwi-gate-not", "id": "not12", "top": 240.1, "left": 243.41, "attrs": {} }
],
"connections": [
[ "not3:OUT", "and9:A", "green", [ "v0" ] ],
@@ -62,7 +70,6 @@
[ "chip1:IN10", "and12:B", "blue", [ "h44.33", "v505.05" ] ],
[ "xor6:OUT", "chip2:OUT11", "green", [ "h97.94", "v-363.55" ] ],
[ "xor5:OUT", "chip2:OUT10", "green", [ "h86.21", "v-253.1" ] ],
- [ "chip1:IN9", "chip2:OUT9", "red", [ "h81.31", "v205.15", "h564.88", "v-197.12" ] ],
[ "not1:OUT", "and1:A", "green", [ "v0" ] ],
[ "and1:OUT", "xor1:A", "green", [ "v0" ] ],
[ "and2:OUT", "xor1:B", "green", [ "v-26.49", "h15.92" ] ],
@@ -78,7 +85,6 @@
[ "chip1:IN7", "and4:B", "blue", [ "h295.9", "v143.39" ] ],
[ "xor2:OUT", "chip2:OUT8", "green", [ "v0" ] ],
[ "xor1:OUT", "chip2:OUT7", "green", [ "v0" ] ],
- [ "chip1:IN6", "chip2:OUT6", "red", [ "h73.16", "v-74.68", "h547.57", "v82.71" ] ],
[ "not2:OUT", "and5:A", "green", [ "v0" ] ],
[ "and5:OUT", "xor3:A", "green", [ "v0" ] ],
[ "and6:OUT", "xor3:B", "green", [ "v-26.49", "h15.92" ] ],
@@ -94,7 +100,6 @@
[ "chip1:IN4", "and8:B", "blue", [ "v0.01", "h105.19", "v-110.24" ] ],
[ "xor4:OUT", "chip2:OUT5", "green", [ "h30.68", "v172.7" ] ],
[ "xor3:OUT", "chip2:OUT4", "green", [ "h45.9", "v283.15" ] ],
- [ "chip1:IN3", "chip2:OUT3", "red", [ "h66.57", "v-338.1", "h585.88", "v342.5" ] ],
[ "not4:OUT", "and13:A", "green", [ "v0" ] ],
[ "and13:OUT", "xor7:A", "green", [ "v0" ] ],
[ "and14:OUT", "xor7:B", "green", [ "v-26.49", "h15.92" ] ],
@@ -110,6 +115,17 @@
[ "and16:B", "chip1:IN1", "blue", [ "h-363.61", "v370.87" ] ],
[ "xor8:OUT", "chip2:OUT2", "green", [ "h65.68", "v433.34" ] ],
[ "xor7:OUT", "chip2:OUT1", "green", [ "h85.5", "v543.79" ] ],
- [ "chip1:IN0", "chip2:OUT0", "red", [ "h13.7", "v-589.11", "h675.44", "v597.14" ] ]
+ [ "chip1:IN0", "not5:IN", "red", [ "h16.96", "v-621.94" ] ],
+ [ "not5:OUT", "not6:IN", "green", [ "v0" ] ],
+ [ "not6:OUT", "chip2:OUT0", "red", [ "v1.12", "h212.35", "v623.99" ] ],
+ [ "not7:OUT", "not8:IN", "green", [ "v0" ] ],
+ [ "not7:IN", "chip1:IN3", "red", [ "v0.14", "h-264.99", "v343.07" ] ],
+ [ "not8:OUT", "chip2:OUT3", "red", [ "v-4.14", "h162.13", "v364.78" ] ],
+ [ "not9:OUT", "not10:IN", "green", [ "v0" ] ],
+ [ "not9:IN", "chip1:IN6", "red", [ "v-1.19", "h-212.14", "v91.18" ] ],
+ [ "not10:OUT", "chip2:OUT6", "red", [ "v-0.19", "h152.43", "v100.2" ] ],
+ [ "not11:OUT", "not12:IN", "green", [ "v0" ] ],
+ [ "chip1:IN9", "not11:IN", "red", [ "h89.09", "v170.08" ] ],
+ [ "not12:OUT", "chip2:OUT9", "red", [ "v2.72", "h174.43", "v-169.28" ] ]
]
}
\ No newline at end of file
