Delete config.json
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
deleted file mode 100644
index 22a00ee..0000000
--- a/openlane/user_project_wrapper/config.json
+++ /dev/null
@@ -1,85 +0,0 @@
-{
- "DESIGN_NAME": "user_project_wrapper",
- "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_project_wrapper.v"],
- "CLOCK_PERIOD": 10,
- "CLOCK_PORT": "user_clock2",
- "CLOCK_NET": "mprj.clk",
- "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
- "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
- "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
- "EXTRA_LEFS": "dir::../../lef/user_proj_example.lef",
- "EXTRA_GDS_FILES": "dir::../../gds/user_proj_example.gds",
- "FP_PDN_CHECK_NODES": 0,
- "SYNTH_ELABORATE_ONLY": 1,
- "PL_RANDOM_GLB_PLACEMENT": 1,
- "PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
- "PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
- "PL_RESIZER_BUFFER_INPUT_PORTS": 0,
- "FP_PDN_ENABLE_RAILS": 0,
- "DIODE_INSERTION_STRATEGY": 0,
- "RUN_FILL_INSERTION": 0,
- "RUN_TAP_DECAP_INSERTION": 0,
- "FP_PDN_VPITCH": 180,
- "FP_PDN_HPITCH": 180,
- "CLOCK_TREE_SYNTH": 0,
- "FP_PDN_VOFFSET": 5,
- "FP_PDN_HOFFSET": 5,
- "MAGIC_ZEROIZE_ORIGIN": 0,
- "FP_SIZING": "absolute",
- "RUN_CVC": 0,
- "UNIT": "2.4",
- "FP_IO_VEXTEND": "expr::2 * $UNIT",
- "FP_IO_HEXTEND": "expr::2 * $UNIT",
- "FP_IO_VLENGTH": "ref::$UNIT",
- "FP_IO_HLENGTH": "ref::$UNIT",
- "FP_IO_VTHICKNESS_MULT": 4,
- "FP_IO_HTHICKNESS_MULT": 4,
- "FP_PDN_CORE_RING": 1,
- "FP_PDN_CORE_RING_VWIDTH": 3.1,
- "FP_PDN_CORE_RING_HWIDTH": 3.1,
- "FP_PDN_CORE_RING_VOFFSET": 12.45,
- "FP_PDN_CORE_RING_HOFFSET": 12.45,
- "FP_PDN_CORE_RING_VSPACING": 1.7,
- "FP_PDN_CORE_RING_HSPACING": 1.7,
- "FP_PDN_VWIDTH": 3.1,
- "FP_PDN_HWIDTH": 3.1,
- "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
- "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
- "VDD_NETS": ["vccd1", "vccd2","vdda1","vdda2"],
- "GND_NETS": ["vssd1", "vssd2","vssa1","vssa2"],
- "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
- "pdk::sky130*": {
- "RT_MAX_LAYER": "met4",
- "DIE_AREA": "0 0 2920 3520",
- "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
- "scl::sky130_fd_sc_hd": {
- "CLOCK_PERIOD": 10
- },
- "scl::sky130_fd_sc_hdll": {
- "CLOCK_PERIOD": 10
- },
- "scl::sky130_fd_sc_hs": {
- "CLOCK_PERIOD": 8
- },
- "scl::sky130_fd_sc_ls": {
- "CLOCK_PERIOD": 10,
- "SYNTH_MAX_FANOUT": 5
- },
- "scl::sky130_fd_sc_ms": {
- "CLOCK_PERIOD": 10
- }
- },
- "pdk::gf180mcuC": {
- "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
- "FP_PDN_CHECK_NODES": 0,
- "FP_PDN_ENABLE_RAILS": 0,
- "RT_MAX_LAYER": "Metal4",
- "DIE_AREA": "0 0 3000 3000",
- "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
- "PL_OPENPHYSYN_OPTIMIZATIONS": 0,
- "DIODE_INSERTION_STRATEGY": 0,
- "FP_PDN_CHECK_NODES": 0,
- "MAGIC_WRITE_FULL_LEF": 0,
- "FP_PDN_ENABLE_RAILS": 0
- }
-}
