diff --git a/openlane/cntr_example/runs/cntr_example/reports/manufacturability.rpt b/openlane/cntr_example/runs/cntr_example/reports/manufacturability.rpt
index 5bf264e..286b38b 100644
--- a/openlane/cntr_example/runs/cntr_example/reports/manufacturability.rpt
+++ b/openlane/cntr_example/runs/cntr_example/reports/manufacturability.rpt
@@ -1,14 +1,14 @@
 Design Name: cntr_example
-Run Directory: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29
+Run Directory: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36
 ----------------------------------------
 
 Magic DRC Summary:
-Source: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.rpt
+Source: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff/drc.rpt
 Total Magic DRC violations is 0
 ----------------------------------------
 
 LVS Summary:
-Source: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/cntr_example.lvs.lef.log
+Source: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/cntr_example.lvs.lef.log
 Source not found.
 ----------------------------------------
 
diff --git a/openlane/cntr_example/runs/cntr_example/reports/metrics.csv b/openlane/cntr_example/runs/cntr_example/reports/metrics.csv
index 6e9a62b..04d05d5 100644
--- a/openlane/cntr_example/runs/cntr_example/reports/metrics.csv
+++ b/openlane/cntr_example/runs/cntr_example/reports/metrics.csv
@@ -1,2 +1,2 @@
 design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
-/home/htf6ry/gf180-demo/openlane/cntr_example,cntr_example,22_12_03_16_29,flow completed,0h4m55s0ms,0h1m40s0ms,47.22222222222222,9.0,9.444444444444445,0.1,1476.13,85,0,0,0,0,0,0,0,-1,0,-1,-1,64292,963,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,121739074.0,0.0,1.21,1.47,0.02,-1,0.91,40,362,20,152,0,0,0,50,0,0,5,0,0,10,5,20,21,20,3,748,13914,0,14662,2178946.7391999997,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,65.0,15.384615384615385,65,AREA 0,10,20,1,153.6,153.18,0.25,0.3,gf180mcu_fd_sc_mcu7t5v0,4
+/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example,cntr_example,22_12_03_21_36,flow completed,0h5m19s0ms,0h1m55s0ms,47.22222222222222,9.0,9.444444444444445,0.1,1545.43,85,0,0,0,0,0,0,0,-1,0,-1,-1,64292,963,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,121739074.0,0.0,1.21,1.47,0.02,-1,0.91,40,362,20,152,0,0,0,50,0,0,5,0,0,10,5,20,21,20,3,748,13914,0,14662,2178946.7391999997,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,65.0,15.384615384615385,65,AREA 0,10,20,1,153.6,153.18,0.25,0.3,gf180mcu_fd_sc_mcu7t5v0,4