commit d50a0e3c07e85d85ac5280e147cbf81072f07d2d
author Cocogoat <70917894+AyaseErii@users.noreply.github.com> Sat Dec 03 22:14:57 2022 -0500
committer GitHub <noreply@github.com> Sat Dec 03 22:14:57 2022 -0500
tree 7a205348a9384717b250ef964c8ee411e39b1205
parent 11968d44ab389cbb0caecd4daa26c7e9a15112e4

Add files via upload

openlane/cntr_example/config.tcl

diff --git a/openlane/cntr_example/config.tcl b/openlane/cntr_example/config.tcl
index 7a88c06..624b731 100644
--- a/openlane/cntr_example/config.tcl
+++ b/openlane/cntr_example/config.tcl
@@ -13,11 +13,13 @@
 set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/../../verilog/rtl/cntr_example.v]
 
 # set absolute size of the die to 300 x 300 um
-#set ::env(DIE_AREA) "0 0 900 900" for two 4-bit counter
+#for two 4-bit counter
+#set ::env(DIE_AREA) "0 0 400 400" 
 set ::env(DIE_AREA) "0 0 1500 1500"
 set ::env(FP_SIZING) absolute
 
-#set ::env(FP_CORE_UTIL) 40 for two 4-bit counter
+#for two 4-bit counter
+#set ::env(FP_CORE_UTIL) 40 
 set ::env(FP_CORE_UTIL) 20
 set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
 
@@ -27,7 +29,8 @@
 # clock period is ns
 # need 40MHz for VGA out = 25ns
 # copied from VGA example
-#set ::env(CLOCK_PERIOD) "35" for two 4-bit counter
+# for two 4-bit counter
+#set ::env(CLOCK_PERIOD) "30" 
 set ::env(CLOCK_PERIOD) "65"
 set ::env(CLOCK_PORT) "wb_clk_i"
 #set ::env(CLOCK_PORT) "clk"