
===========================================================================
report_checks -unconstrained
============================================================================
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (propagated)
                         13.00   13.00 ^ input external delay
                  0.19    0.07   13.07 ^ wb_rst_i (in)
     2    0.00                           wb_rst_i (net)
                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
     4    0.12                           net1 (net)
                  2.79    0.03   15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
                  1.62    1.40   16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
    20    0.18                           _020_ (net)
                  1.63    0.02   16.44 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
                 18.95   11.96   28.41 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
     2    0.43                           _012_ (net)
                 18.95    0.12   28.52 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
                                 28.52   data arrival time

                         65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock source latency
                  0.22    0.10   65.10 ^ wb_clk_i (in)
     2    0.03                           wb_clk_i (net)
                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.15    0.00   65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.19    0.34   65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
                  0.19    0.00   65.77 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
                         -0.25   65.52   clock uncertainty
                          0.00   65.52   clock reconvergence pessimism
                          1.23   66.75   library setup time
                                 66.75   data required time
-----------------------------------------------------------------------------
                                 66.75   data required time
                                -28.52   data arrival time
-----------------------------------------------------------------------------
                                 38.23   slack (MET)


===========================================================================
report_checks --slack_max -0.01
============================================================================
No paths found.