diff --git a/openlane/cntr_example/config.tcl b/openlane/cntr_example/config.tcl
index 624b731..974b3f9 100644
--- a/openlane/cntr_example/config.tcl
+++ b/openlane/cntr_example/config.tcl
@@ -1,51 +1,57 @@
-# User config
-set script_dir [file dirname [file normalize [info script]]]
 
-# name of your project, should also match the name of the top module
-set ::env(DESIGN_NAME) cntr_example
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
 
+set ::env(PDK) "gf180mcuC"
 set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0"
 
-# add your source files here
-#set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/../../verilog/rtl/wrapped_multiplier.v \
-#set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/../../verilog/rtl/wrapped_multiplier.v \
-#    $::env(DESIGN_DIR)/../../verilog/rtl/multilib.v"
-set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/../../verilog/rtl/cntr_example.v]
+set ::env(DESIGN_NAME) cntr_example
 
-# set absolute size of the die to 300 x 300 um
-#for two 4-bit counter
-#set ::env(DIE_AREA) "0 0 400 400" 
-set ::env(DIE_AREA) "0 0 1500 1500"
-set ::env(FP_SIZING) absolute
+set ::env(VERILOG_FILES) "\
+	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+	$::env(DESIGN_DIR)/../../verilog/rtl/cntr_example.v"
 
-#for two 4-bit counter
-#set ::env(FP_CORE_UTIL) 40 
-set ::env(FP_CORE_UTIL) 20
-set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
-
-# define number of IO pads
-set ::env(SYNTH_DEFINES) "MPRJ_IO_PADS=38"
-
-# clock period is ns
-# need 40MHz for VGA out = 25ns
-# copied from VGA example
-# for two 4-bit counter
-#set ::env(CLOCK_PERIOD) "30" 
-set ::env(CLOCK_PERIOD) "65"
-set ::env(CLOCK_PORT) "wb_clk_i"
-#set ::env(CLOCK_PORT) "clk"
-
-# macro needs to work inside Caravel, so can't be core and can't use metal 5
 set ::env(DESIGN_IS_CORE) 0
+
+set ::env(CLOCK_PORT) "wb_clk_i"
+#set ::env(CLOCK_NET) "counter.clk"
+set ::env(CLOCK_PERIOD) "65"
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 1500 1500"
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(PL_BASIC_PLACEMENT) 0
+set ::env(PL_TARGET_DENSITY) 0.45
+
+set ::env(FP_CORE_UTIL) 40
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+# Maximum layer used for routing is metal 4.
+# This is because this macro will be inserted in a top level (user_project_wrapper) 
+# where the PDN is planned on metal 5. So, to avoid having shorts between routes
+# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4.  
+# 
 set ::env(RT_MAX_LAYER) {Metal4}
 
-# define power straps so the macro works inside Caravel's PDN
+# You can draw more power domains if you need to 
 set ::env(VDD_NETS) [list {vdd}]
 set ::env(GND_NETS) [list {vss}]
 
-# regular pin order seems to help with aggregating all the macros for the group project
-#set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-
-set ::env(FP_IO_VTHICKNESS_MULT) 4
-set ::env(FP_IO_HTHICKNESS_MULT) 4
-
+set ::env(DIODE_INSERTION_STRATEGY) 4 
+# If you're going to use multiple power domains, then disable cvc run.
+set ::env(RUN_CVC) 1
\ No newline at end of file
diff --git a/openlane/cntr_example/pin_order.cfg b/openlane/cntr_example/pin_order.cfg
new file mode 100644
index 0000000..2fda806
--- /dev/null
+++ b/openlane/cntr_example/pin_order.cfg
@@ -0,0 +1,10 @@
+#BUS_SORT
+
+#S
+wb_.*
+wbs_.*
+la_.*
+irq.*
+
+#N
+io_.*