diff --git a/openlane/cntr_example/runs/cntr_example/OPENLANE_VERSION b/openlane/cntr_example/runs/cntr_example/OPENLANE_VERSION
new file mode 100644
index 0000000..fabca1a
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/OPENLANE_VERSION
@@ -0,0 +1 @@
+OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/openlane/cntr_example/runs/cntr_example/PDK_SOURCES b/openlane/cntr_example/runs/cntr_example/PDK_SOURCES
new file mode 100644
index 0000000..59f6ae6
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/PDK_SOURCES
@@ -0,0 +1 @@
+open_pdks 0059588eebfc704681dc2368bd1d33d96281d10f
diff --git a/openlane/cntr_example/runs/cntr_example/cmds.log b/openlane/cntr_example/runs/cntr_example/cmds.log
new file mode 100644
index 0000000..4d1ac2f
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/cmds.log
@@ -0,0 +1,122 @@
+Sat Dec 03 21:29:36 UTC 2022 - Executing "/openlane/scripts/mergeLef.py -o /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef -i /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/lef/gf180mcu_fd_sc_mcu7t5v0.lef |& tee /dev/null"
+
+Sat Dec 03 21:29:36 UTC 2022 - Executing "python3 /openlane/scripts/mergeLib.py --output /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/merged.lib --name gf180mcuC_merged /home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib"
+
+Sat Dec 03 21:29:36 UTC 2022 - Executing "python3 /openlane/scripts/libtrim.py --cell-file /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/trimmed.lib.exclude.list --output /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/trimmed.lib /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/merged.lib"
+
+Sat Dec 03 21:29:37 UTC 2022 - Executing "python3 /openlane/scripts/libtrim.py --cell-file /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/cts.lib.exclude.list --output /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/cts.lib /home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib"
+
+Sat Dec 03 21:29:37 UTC 2022 - Executing "python3 /openlane/scripts/new_tracks.py -i /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info -o /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/config.tracks"
+
+Sat Dec 03 21:29:37 UTC 2022 - Executing "echo {OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988} > /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/OPENLANE_VERSION"
+
+Sat Dec 03 21:29:38 UTC 2022 - Executing "sed -E {s/^([[:space:]]+)pg_pin(.*)/\1pin\2\n\1    direction : "inout";/g} /home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib > /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/1-gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.no_pg.lib"
+
+Sat Dec 03 21:29:38 UTC 2022 - Executing "sed -E {s/^([[:space:]]+)pg_pin(.*)/\1pin\2\n\1    direction : "inout";/g} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/trimmed.lib > /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/1-trimmed.no_pg.lib"
+
+Sat Dec 03 21:29:38 UTC 2022 - Executing "yosys -c /openlane/scripts/yosys/synth.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/synthesis/1-synthesis.log"
+
+Sat Dec 03 21:29:40 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/results\/synthesis\/cntr_example.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+
+Sat Dec 03 21:29:40 UTC 2022 - Executing "sed -i /defparam/d /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/synthesis/cntr_example.v"
+
+Sat Dec 03 21:29:40 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/sta.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/synthesis/2-sta.log"
+
+Sat Dec 03 21:29:41 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/floorplan.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan/3-initial_fp.log"
+
+Sat Dec 03 21:29:42 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/floorplan.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan/3-initial_fp.log"
+
+Sat Dec 03 21:29:42 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/defutil.py extract_core_dims --output-data /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/dimensions.txt --input-lef /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/floorplan/3-initial_fp.def"
+
+Sat Dec 03 21:29:43 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/ioplacer.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan/4-io.log"
+
+Sat Dec 03 21:29:43 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/tapcell.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan/5-tap.log"
+
+Sat Dec 03 21:29:44 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/pdn.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan/6-pdn.log"
+
+Sat Dec 03 21:29:46 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/gpl.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/placement/7-global.log"
+
+Sat Dec 03 21:30:02 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/resizer.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/placement/8-resizer.log"
+
+Sat Dec 03 21:30:03 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/tmp\/placement\/8-resizer.nl.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+
+Sat Dec 03 21:30:03 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/dpl.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/placement/9-detailed.log"
+
+Sat Dec 03 21:30:04 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/results\/placement\/cntr_example.nl.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+
+Sat Dec 03 21:30:04 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/cts.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/cts/10-cts.log"
+
+Sat Dec 03 21:30:35 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/resizer_timing.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/cts/11-resizer.log"
+
+Sat Dec 03 21:30:36 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/tmp\/cts\/11-cntr_example.resized.nl.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+
+Sat Dec 03 21:30:36 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/resizer_routing_timing.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/12-resizer.log"
+
+Sat Dec 03 21:30:38 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/tmp\/12-cntr_example.nl.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+
+Sat Dec 03 21:30:38 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/diodes.py place --diode-cell gf180mcu_fd_sc_mcu7t5v0__antenna --diode-pin I --fake-diode-cell gf180mcu_fd_sc_mcu7t5v0__antenna --input-lef /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef --output-def /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/13-diodes.def --output /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/13-diodes.odb /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.odb |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/13-diodes.log"
+
+Sat Dec 03 21:30:38 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/dpl.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/14-diode_legalization.log"
+
+Sat Dec 03 21:30:39 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/tmp\/routing\/diodes.nl.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+
+Sat Dec 03 21:30:39 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/fill.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/15-fill.log"
+
+Sat Dec 03 21:30:41 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/tmp\/routing\/15-fill.nl.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+
+Sat Dec 03 21:30:41 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/groute.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/16-global.log"
+
+Sat Dec 03 21:30:43 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/write_views.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/16-global_write_netlist.log"
+
+Sat Dec 03 21:30:44 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/tmp\/routing\/global.nl.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+
+Sat Dec 03 21:30:44 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/droute.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/18-detailed.log"
+
+Sat Dec 03 21:31:15 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/results\/routing\/cntr_example.nl.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+
+Sat Dec 03 21:31:15 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py tr to_klayout -o /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/routing/drt.klayout.xml --design-name cntr_example /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/routing/drt.drc"
+
+Sat Dec 03 21:31:15 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/wire_lengths.py --report-out /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/routing/19-wire_lengths.csv --input-lef /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef --output-def /dev/null --output /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.odb /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.odb |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/19-wire_lengths.log"
+
+Sat Dec 03 21:31:16 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/rcx.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/20-parasitics_extraction.nom.log"
+
+Sat Dec 03 21:31:18 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/sta_multi_corner.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/21-rcx_mcsta.nom.log"
+
+Sat Dec 03 21:31:21 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/sta.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/22-rcx_sta.log"
+
+Sat Dec 03 21:31:22 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/def/mag_gds.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/23-gdsii.log"
+
+Sat Dec 03 21:31:23 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/gds/mag_with_pointers.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/23-gds_ptrs.log"
+
+Sat Dec 03 21:31:26 UTC 2022 - Executing "sed -i -n {/^<< properties >>/,/^<< end >>/p} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/gds_ptrs.mag"
+
+Sat Dec 03 21:31:26 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/mag/lef.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/23-lef.log"
+
+Sat Dec 03 21:31:30 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/lef/maglef.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/23-maglef.log"
+
+Sat Dec 03 21:31:31 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/extract_spice.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/24-spice.log"
+
+Sat Dec 03 21:31:46 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/power_utils.py write_powered_def --output /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.p.def --input-lef /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef --power-port vdd --ground-port vss --powered-netlist {} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/25-write_powered_def.log"
+
+Sat Dec 03 21:31:47 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/write_views.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/25-write_powered_verilog.log"
+
+Sat Dec 03 21:31:49 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/tmp\/signoff\/24-cntr_example.nl.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+
+Sat Dec 03 21:31:49 UTC 2022 - Executing "netgen -batch source /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/27-setup_file.lef.lvs |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/27-lvs.lef.log"
+
+Sat Dec 03 21:31:50 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/drc.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/28-drc.log"
+
+Sat Dec 03 21:34:30 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py magic to_tcl -o /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.tcl /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.rpt"
+
+Sat Dec 03 21:34:30 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py magic to_tr -o /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.tr /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.rpt"
+
+Sat Dec 03 21:34:30 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py tr to_klayout -o /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.klayout.xml --design-name cntr_example /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.tr"
+
+Sat Dec 03 21:34:30 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py magic to_rdb -o /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.rdb /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.rpt"
+
+Sat Dec 03 21:34:30 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/antenna_check.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/29-antenna.log"
+
+Sat Dec 03 21:34:31 UTC 2022 - Executing "python3 /openlane/scripts/extract_antenna_violators.py --output /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/29-antenna_violators.rpt /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/29-antenna.log"
+
+Sat Dec 03 21:34:31 UTC 2022 - Executing "python3 /openlane/scripts/generate_reports.py -d /home/htf6ry/gf180-demo/openlane/cntr_example --design_name cntr_example --tag 22_12_03_16_29 --output_file /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/metrics.csv --man_report /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/manufacturability.rpt --run_path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29"
+
diff --git a/openlane/cntr_example/runs/cntr_example/config.tcl b/openlane/cntr_example/runs/cntr_example/config.tcl
new file mode 100644
index 0000000..d9d5f76
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/config.tcl
@@ -0,0 +1,722 @@
+# Run configs
+set ::env(PDK_ROOT) {/home/htf6ry/GF180PDK/}
+set ::env(BASE_SDC_FILE) {/openlane/scripts/base.sdc}
+set ::env(BOTTOM_MARGIN_MULT) {4}
+set ::env(CARRY_SELECT_ADDER_MAP) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/csa_map.v}
+set ::env(CELLS_LEF) {/home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/lef/gf180mcu_fd_sc_mcu7t5v0.lef}
+set ::env(CELL_PAD_EXCLUDE) {gf180mcu_fd_sc_mcu7t5v0__filltie_* gf180mcu_fd_sc_mcu7t5v0__filldecap_* gf180mcu_fd_sc_mcu7t5v0__fill_* gf180mcu_fd_sc_mcu7t5v0__endcap_*}
+set ::env(CHECK_ASSIGN_STATEMENTS) {0}
+set ::env(CHECK_UNMAPPED_CELLS) {1}
+set ::env(CLOCK_BUFFER_FANOUT) {16}
+set ::env(CLOCK_PERIOD) {65}
+set ::env(CLOCK_PORT) {wb_clk_i}
+set ::env(CLOCK_TREE_SYNTH) {1}
+set ::env(CLOCK_WIRE_RC_LAYER) {Metal4}
+set ::env(CONFIGS) {general.tcl checkers.tcl synthesis.tcl floorplan.tcl cts.tcl placement.tcl routing.tcl extraction.tcl}
+set ::env(CTS_CLK_BUFFER_LIST) {gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 gf180mcu_fd_sc_mcu7t5v0__clkbuf_8}
+set ::env(CTS_CLK_MAX_WIRE_LENGTH) {0}
+set ::env(CTS_DISABLE_POST_PROCESSING) {0}
+set ::env(CTS_DISTANCE_BETWEEN_BUFFERS) {0}
+set ::env(CTS_MAX_CAP) {0.5}
+set ::env(CTS_REPORT_TIMING) {1}
+set ::env(CTS_ROOT_BUFFER) {gf180mcu_fd_sc_mcu7t5v0__clkbuf_16}
+set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) {50}
+set ::env(CTS_SINK_CLUSTERING_SIZE) {25}
+set ::env(CTS_TARGET_SKEW) {200}
+set ::env(CTS_TOLERANCE) {100}
+set ::env(DATA_WIRE_RC_LAYER) {Metal2}
+set ::env(DECAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__fillcap_*}
+set ::env(DEFAULT_MAX_TRAN) {3}
+set ::env(DEF_UNITS_PER_MICRON) {2000}
+set ::env(DESIGN_CONFIG) {/home/htf6ry/gf180-demo/openlane/cntr_example/config.tcl}
+set ::env(DESIGN_IS_CORE) {0}
+set ::env(DESIGN_NAME) {cntr_example}
+set ::env(DETAILED_ROUTER) {tritonroute}
+set ::env(DIE_AREA) {0 0 1500 1500}
+set ::env(DIODE_CELL) {gf180mcu_fd_sc_mcu7t5v0__antenna}
+set ::env(DIODE_CELL_PIN) {I}
+set ::env(DIODE_INSERTION_STRATEGY) {4}
+set ::env(DIODE_PADDING) {2}
+set ::env(DPL_CELL_PADDING) {2}
+set ::env(DRC_EXCLUDE_CELL_LIST) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells}
+set ::env(DRC_EXCLUDE_CELL_LIST_OPT) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells}
+set ::env(DRT_MIN_LAYER) {Metal1}
+set ::env(DRT_OPT_ITERS) {64}
+set ::env(ECO_ENABLE) {0}
+set ::env(ECO_FINISH) {0}
+set ::env(ECO_ITER) {0}
+set ::env(ECO_SKIP_PIN) {1}
+set ::env(FILL_CELL) {gf180mcu_fd_sc_mcu7t5v0__fill_*}
+set ::env(FP_ASPECT_RATIO) {1}
+set ::env(FP_CORE_UTIL) {20}
+set ::env(FP_ENDCAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__endcap}
+set ::env(FP_IO_HEXTEND) {-1}
+set ::env(FP_IO_HLAYER) {Metal3}
+set ::env(FP_IO_HLENGTH) {4}
+set ::env(FP_IO_HTHICKNESS_MULT) {4}
+set ::env(FP_IO_MIN_DISTANCE) {3}
+set ::env(FP_IO_MODE) {1}
+set ::env(FP_IO_UNMATCHED_ERROR) {1}
+set ::env(FP_IO_VEXTEND) {-1}
+set ::env(FP_IO_VLAYER) {Metal2}
+set ::env(FP_IO_VLENGTH) {4}
+set ::env(FP_IO_VTHICKNESS_MULT) {4}
+set ::env(FP_PDN_AUTO_ADJUST) {1}
+set ::env(FP_PDN_CHECK_NODES) {1}
+set ::env(FP_PDN_CORE_RING) {0}
+set ::env(FP_PDN_CORE_RING_HOFFSET) {6}
+set ::env(FP_PDN_CORE_RING_HSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_HWIDTH) {1.6}
+set ::env(FP_PDN_CORE_RING_VOFFSET) {6}
+set ::env(FP_PDN_CORE_RING_VSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_VWIDTH) {1.6}
+set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) {1}
+set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
+set ::env(FP_PDN_ENABLE_RAILS) {1}
+set ::env(FP_PDN_HOFFSET) {16.65}
+set ::env(FP_PDN_HORIZONTAL_HALO) {10}
+set ::env(FP_PDN_HPITCH) {153.18}
+set ::env(FP_PDN_HSPACING) {1.7}
+set ::env(FP_PDN_HWIDTH) {1.6}
+set ::env(FP_PDN_IRDROP) {1}
+set ::env(FP_PDN_LOWER_LAYER) {Metal4}
+set ::env(FP_PDN_RAILS_LAYER) {Metal1}
+set ::env(FP_PDN_RAIL_OFFSET) {0}
+set ::env(FP_PDN_RAIL_WIDTH) {0.6}
+set ::env(FP_PDN_SKIPTRIM) {0}
+set ::env(FP_PDN_UPPER_LAYER) {Metal5}
+set ::env(FP_PDN_VERTICAL_HALO) {10}
+set ::env(FP_PDN_VOFFSET) {16.32}
+set ::env(FP_PDN_VPITCH) {153.6}
+set ::env(FP_PDN_VSPACING) {1.7}
+set ::env(FP_PDN_VWIDTH) {1.6}
+set ::env(FP_SIZING) {absolute}
+set ::env(FP_TAPCELL_DIST) {20}
+set ::env(FP_TAP_HORIZONTAL_HALO) {10}
+set ::env(FP_TAP_VERTICAL_HALO) {10}
+set ::env(FP_WELLTAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__filltie}
+set ::env(FULL_ADDER_MAP) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/fa_map.v}
+set ::env(GDS_FILES) {/home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/gds/gf180mcu_fd_sc_mcu7t5v0.gds}
+set ::env(GENERATE_FINAL_SUMMARY_REPORT) {1}
+set ::env(GLB_CFG_FILE) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl}
+set ::env(GLB_OPTIMIZE_MIRRORING) {1}
+set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) {0}
+set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
+set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) {0.05}
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {10}
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {10}
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {0}
+set ::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
+set ::env(GLB_RESIZER_SETUP_SLACK_MARGIN) {0.025}
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
+set ::env(GLOBAL_ROUTER) {fastroute}
+set ::env(GND_NETS) {vss}
+set ::env(GND_PIN) {VSS}
+set ::env(GPIO_PADS_LEF) { /home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_io/lef/GF018green_ipio_5p0c_75_5lm.lef
+}
+set ::env(GPIO_PADS_VERILOG) { /home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_io/verilog/GF018green_ipio_5p0c_75_5lm.v
+}
+set ::env(GPL_CELL_PADDING) {0}
+set ::env(GRT_ADJUSTMENT) {0.3}
+set ::env(GRT_ALLOW_CONGESTION) {0}
+set ::env(GRT_ANT_ITERS) {3}
+set ::env(GRT_ESTIMATE_PARASITICS) {1}
+set ::env(GRT_LAYER_ADJUSTMENTS) {0,0,0,0,0}
+set ::env(GRT_MACRO_EXTENSION) {0}
+set ::env(GRT_MAX_DIODE_INS_ITERS) {1}
+set ::env(GRT_OVERFLOW_ITERS) {50}
+set ::env(IO_PCT) {0.2}
+set ::env(KLAYOUT_DRC_KLAYOUT_GDS) {0}
+set ::env(KLAYOUT_DRC_TECH_SCRIPT) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/klayout/gf180mcuC_mr.drc}
+set ::env(KLAYOUT_PROPERTIES) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/klayout/gf180mcuC.lyp}
+set ::env(KLAYOUT_TECH) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/klayout/gf180mcuC.lyt}
+set ::env(KLAYOUT_XOR_GDS) {1}
+set ::env(KLAYOUT_XOR_XML) {1}
+set ::env(LEC_ENABLE) {0}
+set ::env(LEFT_MARGIN_MULT) {12}
+set ::env(LIB_FASTEST) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ff_n40C_5v50.lib}
+set ::env(LIB_SLOWEST) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ss_125C_1v62.lib}
+set ::env(LIB_SYNTH) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib}
+set ::env(LIB_TYPICAL) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib}
+set ::env(LOGS_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs}
+set ::env(LVS_CONNECT_BY_LABEL) {0}
+set ::env(LVS_INSERT_POWER_PINS) {1}
+set ::env(MACRO_BLOCKAGES_LAYER) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(MAGIC_CONVERT_DRC_TO_RDB) {1}
+set ::env(MAGIC_DEF_LABELS) {1}
+set ::env(MAGIC_DEF_NO_BLOCKAGES) {1}
+set ::env(MAGIC_DISABLE_HIER_GDS) {1}
+set ::env(MAGIC_DRC_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
+set ::env(MAGIC_GENERATE_GDS) {1}
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_GENERATE_MAGLEF) {1}
+set ::env(MAGIC_INCLUDE_GDS_POINTERS) {0}
+set ::env(MAGIC_MAGICRC) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc}
+set ::env(MAGIC_PAD) {0}
+set ::env(MAGIC_TECH_FILE) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.tech}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+set ::env(MAGIC_ZEROIZE_ORIGIN) {0}
+set ::env(METAL_LAYER_NAMES) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(NETGEN_SETUP_FILE) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/netgen/gf180mcuC_setup.tcl}
+set ::env(NO_SYNTH_CELL_LIST) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells}
+set ::env(OPENLANE_VERBOSE) {0}
+set ::env(PDKPATH) {/home/htf6ry/GF180PDK//gf180mcuC}
+set ::env(PDN_CFG) {/openlane/scripts/openroad/common/pdn_cfg.tcl}
+set ::env(PLACE_SITE) {GF018hv5v_mcu_sc7}
+set ::env(PLACE_SITE_HEIGHT) {3.92}
+set ::env(PLACE_SITE_WIDTH) {0.56}
+set ::env(PL_BASIC_PLACEMENT) {0}
+set ::env(PL_ESTIMATE_PARASITICS) {1}
+set ::env(PL_LIB) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib}
+set ::env(PL_MACRO_CHANNEL) {0 0}
+set ::env(PL_MACRO_HALO) {0 0}
+set ::env(PL_MAX_DISPLACEMENT_X) {500}
+set ::env(PL_MAX_DISPLACEMENT_Y) {100}
+set ::env(PL_OPTIMIZE_MIRRORING) {1}
+set ::env(PL_RANDOM_GLB_PLACEMENT) {0}
+set ::env(PL_RANDOM_INITIAL_PLACEMENT) {0}
+set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) {0}
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) {1}
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) {1}
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {1}
+set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) {0.1}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {20}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {20}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {0}
+set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) {1}
+set ::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
+set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) {0.05}
+set ::env(PL_RESIZER_TIE_SEPERATION) {0}
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1}
+set ::env(PL_ROUTABILITY_DRIVEN) {1}
+set ::env(PL_SKIP_INITIAL_PLACEMENT) {0}
+set ::env(PL_TARGET_DENSITY) {0.25}
+set ::env(PL_TIME_DRIVEN) {1}
+set ::env(PRIMARY_SIGNOFF_TOOL) {magic}
+set ::env(PROCESS) {180}
+set ::env(QUIT_ON_HOLD_VIOLATIONS) {1}
+set ::env(QUIT_ON_ILLEGAL_OVERLAPS) {1}
+set ::env(QUIT_ON_LONG_WIRE) {0}
+set ::env(QUIT_ON_LVS_ERROR) {1}
+set ::env(QUIT_ON_MAGIC_DRC) {1}
+set ::env(QUIT_ON_SETUP_VIOLATIONS) {1}
+set ::env(QUIT_ON_TIMING_VIOLATIONS) {1}
+set ::env(QUIT_ON_TR_DRC) {1}
+set ::env(RCX_CC_MODEL) {10}
+set ::env(RCX_CONTEXT_DEPTH) {5}
+set ::env(RCX_CORNER_COUNT) {1}
+set ::env(RCX_COUPLING_THRESHOLD) {0.1}
+set ::env(RCX_MAX_RESISTANCE) {50}
+set ::env(RCX_MERGE_VIA_WIRE_RES) {1}
+set ::env(RCX_RULES) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.nom.magic}
+set ::env(RCX_RULES_MAX) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.max.magic}
+set ::env(RCX_RULES_MIN) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.min.magic}
+set ::env(REPORTS_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports}
+set ::env(RESULTS_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results}
+set ::env(RIGHT_MARGIN_MULT) {12}
+set ::env(RIPPLE_CARRY_ADDER_MAP) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/rca_map.v}
+set ::env(ROUTING_CORES) {2}
+set ::env(RSZ_DONT_TOUCH_RX) {$^}
+set ::env(RSZ_USE_OLD_REMOVER) {0}
+set ::env(RT_MAX_LAYER) {Metal4}
+set ::env(RT_MIN_LAYER) {Metal2}
+set ::env(RUN_CVC) {1}
+set ::env(RUN_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29}
+set ::env(RUN_DRT) {1}
+set ::env(RUN_FILL_INSERTION) {1}
+set ::env(RUN_IRDROP_REPORT) {0}
+set ::env(RUN_KLAYOUT) {0}
+set ::env(RUN_KLAYOUT_DRC) {0}
+set ::env(RUN_KLAYOUT_XOR) {0}
+set ::env(RUN_LVS) {1}
+set ::env(RUN_MAGIC) {1}
+set ::env(RUN_MAGIC_DRC) {1}
+set ::env(RUN_SPEF_EXTRACTION) {1}
+set ::env(RUN_TAG) {22_12_03_16_29}
+set ::env(RUN_TAP_DECAP_INSERTION) {1}
+set ::env(SCLPATH) {/home/htf6ry/GF180PDK//gf180mcuC/gf180mcu_fd_sc_mcu7t5v0}
+set ::env(SPEF_EXTRACTOR) {openrcx}
+set ::env(START_TIME) {2022.12.03_21.29.36}
+set ::env(STA_REPORT_POWER) {1}
+set ::env(STA_WRITE_LIB) {1}
+set ::env(STD_CELL_GROUND_PINS) {VSS}
+set ::env(STD_CELL_LIBRARY) {gf180mcu_fd_sc_mcu7t5v0}
+set ::env(STD_CELL_LIBRARY_CDL) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/cdl/gf180mcu_fd_sc_mcu7t5v0.cdl}
+set ::env(STD_CELL_LIBRARY_OPT) {gf180mcu_fd_sc_mcu7t5v0}
+set ::env(STD_CELL_POWER_PINS) {VDD}
+set ::env(SYNTH_ADDER_TYPE) {YOSYS}
+set ::env(SYNTH_BIN) {yosys}
+set ::env(SYNTH_BUFFERING) {1}
+set ::env(SYNTH_CAP_LOAD) {72.91}
+set ::env(SYNTH_CLK_DRIVING_CELL) {gf180mcu_fd_sc_mcu7t5v0__inv_4}
+set ::env(SYNTH_CLK_DRIVING_CELL_PIN) {ZN}
+set ::env(SYNTH_CLOCK_TRANSITION) {0.15}
+set ::env(SYNTH_CLOCK_UNCERTAINTY) {0.25}
+set ::env(SYNTH_DEFINES) {MPRJ_IO_PADS=38}
+set ::env(SYNTH_DRIVING_CELL) {gf180mcu_fd_sc_mcu7t5v0__inv_1}
+set ::env(SYNTH_DRIVING_CELL_PIN) {ZN}
+set ::env(SYNTH_ELABORATE_ONLY) {0}
+set ::env(SYNTH_EXTRA_MAPPING_FILE) {}
+set ::env(SYNTH_FLAT_TOP) {0}
+set ::env(SYNTH_LATCH_MAP) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/latch_map.v}
+set ::env(SYNTH_MAX_FANOUT) {10}
+set ::env(SYNTH_MIN_BUF_PORT) {gf180mcu_fd_sc_mcu7t5v0__buf_1 I Z}
+set ::env(SYNTH_NO_FLAT) {0}
+set ::env(SYNTH_READ_BLACKBOX_LIB) {0}
+set ::env(SYNTH_SCRIPT) {/openlane/scripts/yosys/synth.tcl}
+set ::env(SYNTH_SHARE_RESOURCES) {1}
+set ::env(SYNTH_SIZING) {0}
+set ::env(SYNTH_STRATEGY) {AREA 0}
+set ::env(SYNTH_TIEHI_PORT) {gf180mcu_fd_sc_mcu7t5v0__tieh Z}
+set ::env(SYNTH_TIELO_PORT) {gf180mcu_fd_sc_mcu7t5v0__tiel ZN}
+set ::env(SYNTH_TIMING_DERATE) {0.05}
+set ::env(TAKE_LAYOUT_SCROT) {0}
+set ::env(TECH_LEF) {/home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef}
+set ::env(TERMINAL_OUTPUT) {/dev/null}
+set ::env(TMP_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp}
+set ::env(TOP_MARGIN_MULT) {4}
+set ::env(TRACKS_INFO_FILE) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info}
+set ::env(TRISTATE_BUFFER_MAP) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tribuff_map.v}
+set ::env(USE_ARC_ANTENNA_CHECK) {1}
+set ::env(USE_GPIO_PADS) {0}
+set ::env(VDD_NETS) {vdd}
+set ::env(VDD_PIN) {VDD}
+set ::env(VERILOG_FILES) {/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v}
+set ::env(WIRE_RC_LAYER) {Metal2}
+set ::env(YOSYS_REWRITE_VERILOG) {0}
+set ::env(cts_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/cts}
+set ::env(cts_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/cts}
+set ::env(cts_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts}
+set ::env(cts_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts}
+set ::env(eco_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/eco}
+set ::env(eco_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/eco}
+set ::env(eco_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/eco}
+set ::env(eco_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/eco}
+set ::env(floorplan_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan}
+set ::env(floorplan_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/floorplan}
+set ::env(floorplan_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/floorplan}
+set ::env(floorplan_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/floorplan}
+set ::env(placement_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/placement}
+set ::env(placement_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/placement}
+set ::env(placement_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/placement}
+set ::env(placement_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement}
+set ::env(routing_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing}
+set ::env(routing_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/routing}
+set ::env(routing_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing}
+set ::env(routing_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing}
+set ::env(signoff_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff}
+set ::env(signoff_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff}
+set ::env(signoff_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff}
+set ::env(signoff_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff}
+set ::env(synthesis_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/synthesis}
+set ::env(synthesis_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/synthesis}
+set ::env(synthesis_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/synthesis}
+set ::env(synthesis_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis}
+set ::env(SYNTH_MAX_TRAN) {3}
+set ::env(CURRENT_INDEX) 29
+set ::env(CURRENT_DEF) /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def
+set ::env(CURRENT_GUIDE) /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/16-global.guide
+set ::env(CURRENT_NETLIST) /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.nl.v
+set ::env(CURRENT_POWERED_NETLIST) {0}
+set ::env(CURRENT_ODB) /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.odb
+set ::env(PDK_ROOT) {/home/htf6ry/GF180PDK/}
+set ::env(ANTENNA_CHECK_CURRENT_DEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.p.def}
+set ::env(ANTENNA_VIOLATOR_LIST) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/29-antenna_violators.rpt}
+set ::env(BASE_SDC_FILE) {/openlane/scripts/base.sdc}
+set ::env(BASIC_PREP_COMPLETE) {1}
+set ::env(BOTTOM_MARGIN_MULT) {4}
+set ::env(CARAVEL_ROOT) {/home/htf6ry/gf180-demo/caravel}
+set ::env(CARRY_SELECT_ADDER_MAP) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/csa_map.v}
+set ::env(CELLS_LEF) {/home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/lef/gf180mcu_fd_sc_mcu7t5v0.lef}
+set ::env(CELL_PAD_EXCLUDE) {gf180mcu_fd_sc_mcu7t5v0__filltie_* gf180mcu_fd_sc_mcu7t5v0__filldecap_* gf180mcu_fd_sc_mcu7t5v0__fill_* gf180mcu_fd_sc_mcu7t5v0__endcap_*}
+set ::env(CHECK_ASSIGN_STATEMENTS) {0}
+set ::env(CHECK_UNMAPPED_CELLS) {1}
+set ::env(CLOCK_BUFFER_FANOUT) {16}
+set ::env(CLOCK_NET) {wb_clk_i}
+set ::env(CLOCK_PERIOD) {65}
+set ::env(CLOCK_PORT) {wb_clk_i}
+set ::env(CLOCK_TREE_SYNTH) {1}
+set ::env(CLOCK_WIRE_RC_LAYER) {Metal4}
+set ::env(CONFIGS) {general.tcl checkers.tcl synthesis.tcl floorplan.tcl cts.tcl placement.tcl routing.tcl extraction.tcl}
+set ::env(CORE_AREA) {6.72 15.68 1492.96 1481.76}
+set ::env(CORE_HEIGHT) {1466.08}
+set ::env(CORE_WIDTH) {1486.24}
+set ::env(CTS_CLK_BUFFER_LIST) {gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 gf180mcu_fd_sc_mcu7t5v0__clkbuf_8}
+set ::env(CTS_CLK_MAX_WIRE_LENGTH) {0}
+set ::env(CTS_CURRENT_DEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/placement/cntr_example.def}
+set ::env(CTS_DISABLE_POST_PROCESSING) {0}
+set ::env(CTS_DISTANCE_BETWEEN_BUFFERS) {0}
+set ::env(CTS_MAX_CAP) {0.5}
+set ::env(CTS_REPORT_TIMING) {1}
+set ::env(CTS_ROOT_BUFFER) {gf180mcu_fd_sc_mcu7t5v0__clkbuf_16}
+set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) {50}
+set ::env(CTS_SINK_CLUSTERING_SIZE) {25}
+set ::env(CTS_TARGET_SKEW) {200}
+set ::env(CTS_TOLERANCE) {100}
+set ::env(CURRENT_DEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.p.def}
+set ::env(CURRENT_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing}
+set ::env(CURRENT_GDS) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/cntr_example.gds}
+set ::env(CURRENT_GUIDE) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/16-global.guide}
+set ::env(CURRENT_INDEX) {29}
+set ::env(CURRENT_LIB) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.lib}
+set ::env(CURRENT_NETLIST) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.nl.v}
+set ::env(CURRENT_ODB) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.odb}
+set ::env(CURRENT_POWERED_NETLIST) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.pnl.v}
+set ::env(CURRENT_SDC) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.sdc}
+set ::env(CURRENT_SDF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.sdf}
+set ::env(CURRENT_SPEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.spef}
+set ::env(CURRENT_STEP) {}
+set ::env(DATA_WIRE_RC_LAYER) {Metal2}
+set ::env(DECAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__fillcap_*}
+set ::env(DEFAULT_MAX_TRAN) {3}
+set ::env(DEF_UNITS_PER_MICRON) {2000}
+set ::env(DESIGN_CONFIG) {/home/htf6ry/gf180-demo/openlane/cntr_example/config.tcl}
+set ::env(DESIGN_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example}
+set ::env(DESIGN_IS_CORE) {0}
+set ::env(DESIGN_NAME) {cntr_example}
+set ::env(DETAILED_ROUTER) {tritonroute}
+set ::env(DIE_AREA) {0.0 0.0 1500.0 1500.0}
+set ::env(DIODE_CELL) {gf180mcu_fd_sc_mcu7t5v0__antenna}
+set ::env(DIODE_CELL_PIN) {I}
+set ::env(DIODE_INSERTION_CURRENT_DEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def}
+set ::env(DIODE_INSERTION_STRATEGY) {4}
+set ::env(DIODE_PADDING) {2}
+set ::env(DONT_USE_CELLS) {gf180mcu_fd_sc_mcu7t5v0__mux2_1 gf180mcu_fd_sc_mcu7t5v0__oai33_2 }
+set ::env(DPL_CELL_PADDING) {2}
+set ::env(DRC_CURRENT_DEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.p.def}
+set ::env(DRC_EXCLUDE_CELL_LIST) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells}
+set ::env(DRC_EXCLUDE_CELL_LIST_OPT) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells}
+set ::env(DRT_MIN_LAYER) {Metal1}
+set ::env(DRT_OPT_ITERS) {64}
+set ::env(ECO_ENABLE) {0}
+set ::env(ECO_FINISH) {0}
+set ::env(ECO_ITER) {0}
+set ::env(ECO_SKIP_PIN) {1}
+set ::env(EXT_NETLIST) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/cntr_example.spice}
+set ::env(FILL_CELL) {gf180mcu_fd_sc_mcu7t5v0__fill_*}
+set ::env(FP_ASPECT_RATIO) {1}
+set ::env(FP_CORE_UTIL) {20}
+set ::env(FP_ENDCAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__endcap}
+set ::env(FP_IO_HEXTEND) {-1}
+set ::env(FP_IO_HLAYER) {Metal3}
+set ::env(FP_IO_HLENGTH) {4}
+set ::env(FP_IO_HTHICKNESS_MULT) {4}
+set ::env(FP_IO_MIN_DISTANCE) {3}
+set ::env(FP_IO_MODE) {1}
+set ::env(FP_IO_UNMATCHED_ERROR) {1}
+set ::env(FP_IO_VEXTEND) {-1}
+set ::env(FP_IO_VLAYER) {Metal2}
+set ::env(FP_IO_VLENGTH) {4}
+set ::env(FP_IO_VTHICKNESS_MULT) {4}
+set ::env(FP_PDN_AUTO_ADJUST) {1}
+set ::env(FP_PDN_CHECK_NODES) {1}
+set ::env(FP_PDN_CORE_RING) {0}
+set ::env(FP_PDN_CORE_RING_HOFFSET) {6}
+set ::env(FP_PDN_CORE_RING_HSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_HWIDTH) {1.6}
+set ::env(FP_PDN_CORE_RING_VOFFSET) {6}
+set ::env(FP_PDN_CORE_RING_VSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_VWIDTH) {1.6}
+set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) {1}
+set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
+set ::env(FP_PDN_ENABLE_RAILS) {1}
+set ::env(FP_PDN_HOFFSET) {16.65}
+set ::env(FP_PDN_HORIZONTAL_HALO) {10}
+set ::env(FP_PDN_HPITCH) {153.18}
+set ::env(FP_PDN_HSPACING) {1.7}
+set ::env(FP_PDN_HWIDTH) {1.6}
+set ::env(FP_PDN_IRDROP) {1}
+set ::env(FP_PDN_LOWER_LAYER) {Metal4}
+set ::env(FP_PDN_RAILS_LAYER) {Metal1}
+set ::env(FP_PDN_RAIL_OFFSET) {0}
+set ::env(FP_PDN_RAIL_WIDTH) {0.6}
+set ::env(FP_PDN_SKIPTRIM) {0}
+set ::env(FP_PDN_UPPER_LAYER) {Metal5}
+set ::env(FP_PDN_VERTICAL_HALO) {10}
+set ::env(FP_PDN_VOFFSET) {16.32}
+set ::env(FP_PDN_VPITCH) {153.6}
+set ::env(FP_PDN_VSPACING) {1.7}
+set ::env(FP_PDN_VWIDTH) {1.6}
+set ::env(FP_SIZING) {absolute}
+set ::env(FP_TAPCELL_DIST) {20}
+set ::env(FP_TAP_HORIZONTAL_HALO) {10}
+set ::env(FP_TAP_VERTICAL_HALO) {10}
+set ::env(FP_WELLTAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__filltie}
+set ::env(FULL_ADDER_MAP) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/fa_map.v}
+set ::env(GDS_FILES) {/home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/gds/gf180mcu_fd_sc_mcu7t5v0.gds}
+set ::env(GENERATE_FINAL_SUMMARY_REPORT) {1}
+set ::env(GLB_CFG_FILE) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl}
+set ::env(GLB_OPTIMIZE_MIRRORING) {1}
+set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) {0}
+set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
+set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) {0.05}
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {10}
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {10}
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {0}
+set ::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
+set ::env(GLB_RESIZER_SETUP_SLACK_MARGIN) {0.025}
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
+set ::env(GLOBAL_ROUTER) {fastroute}
+set ::env(GND_NET) {vss}
+set ::env(GND_NETS) {vss}
+set ::env(GND_PIN) {vss}
+set ::env(GPIO_PADS_LEF) { /home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_io/lef/GF018green_ipio_5p0c_75_5lm.lef
+}
+set ::env(GPIO_PADS_VERILOG) { /home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_io/verilog/GF018green_ipio_5p0c_75_5lm.v
+}
+set ::env(GPL_CELL_PADDING) {0}
+set ::env(GRT_ADJUSTMENT) {0.3}
+set ::env(GRT_ALLOW_CONGESTION) {0}
+set ::env(GRT_ANT_ITERS) {3}
+set ::env(GRT_ESTIMATE_PARASITICS) {1}
+set ::env(GRT_LAYER_ADJUSTMENTS) {0,0,0,0,0}
+set ::env(GRT_MACRO_EXTENSION) {0}
+set ::env(GRT_MAX_DIODE_INS_ITERS) {1}
+set ::env(GRT_OVERFLOW_ITERS) {50}
+set ::env(HOME) {/}
+set ::env(HOSTNAME) {8af15976aba8}
+set ::env(IO_PCT) {0.2}
+set ::env(KLAYOUT_DRC_KLAYOUT_GDS) {0}
+set ::env(KLAYOUT_DRC_TECH_SCRIPT) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/klayout/gf180mcuC_mr.drc}
+set ::env(KLAYOUT_PROPERTIES) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/klayout/gf180mcuC.lyp}
+set ::env(KLAYOUT_TECH) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/klayout/gf180mcuC.lyt}
+set ::env(KLAYOUT_XOR_GDS) {1}
+set ::env(KLAYOUT_XOR_XML) {1}
+set ::env(LANG) {en_US.UTF-8}
+set ::env(LAST_TIMING_REPORT_TAG) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/22-rcx_sta}
+set ::env(LC_ALL) {en_US.UTF-8}
+set ::env(LC_CTYPE) {en_US.UTF-8}
+set ::env(LD_LIBRARY_PATH) {/build//lib:/build//lib/Linux-x86_64:}
+set ::env(LEC_ENABLE) {0}
+set ::env(LEFT_MARGIN_MULT) {12}
+set ::env(LIB_CTS) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/cts.lib}
+set ::env(LIB_FASTEST) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ff_n40C_5v50.lib}
+set ::env(LIB_SLOWEST) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ss_125C_1v62.lib}
+set ::env(LIB_SYNTH) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/trimmed.lib}
+set ::env(LIB_SYNTH_COMPLETE) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib}
+set ::env(LIB_SYNTH_COMPLETE_NO_PG) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/1-gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.no_pg.lib}
+set ::env(LIB_SYNTH_MERGED) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/merged.lib}
+set ::env(LIB_SYNTH_NO_PG) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/1-trimmed.no_pg.lib}
+set ::env(LIB_TYPICAL) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib}
+set ::env(LOGS_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs}
+set ::env(LVS_CONNECT_BY_LABEL) {0}
+set ::env(LVS_CURRENT_DEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def}
+set ::env(LVS_INSERT_POWER_PINS) {1}
+set ::env(MACRO_BLOCKAGES_LAYER) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(MAGIC_CONVERT_DRC_TO_RDB) {1}
+set ::env(MAGIC_DEF_LABELS) {1}
+set ::env(MAGIC_DEF_NO_BLOCKAGES) {1}
+set ::env(MAGIC_DISABLE_HIER_GDS) {1}
+set ::env(MAGIC_DRC_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
+set ::env(MAGIC_GDS) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/cntr_example.magic.gds}
+set ::env(MAGIC_GENERATE_GDS) {1}
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_GENERATE_MAGLEF) {1}
+set ::env(MAGIC_INCLUDE_GDS_POINTERS) {0}
+set ::env(MAGIC_MAGICRC) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc}
+set ::env(MAGIC_PAD) {0}
+set ::env(MAGIC_TECH_FILE) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.tech}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+set ::env(MAGIC_ZEROIZE_ORIGIN) {0}
+set ::env(MAGTYPE) {maglef}
+set ::env(MANPATH) {/build//share/man:}
+set ::env(MAX_METAL_LAYER) {5}
+set ::env(MCW_ROOT) {/home/htf6ry/gf180-demo/mgmt_core_wrapper}
+set ::env(MC_SDF_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/sdf}
+set ::env(MC_SPEF_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/spef}
+set ::env(MERGED_LEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef}
+set ::env(METAL_LAYER_NAMES) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(MISMATCHES_OK) {1}
+set ::env(NETGEN_SETUP_FILE) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/netgen/gf180mcuC_setup.tcl}
+set ::env(NO_SYNTH_CELL_LIST) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells}
+set ::env(OPENLANE_ROOT) {/openlane}
+set ::env(OPENLANE_RUN_TAG) {22_12_03_16_29}
+set ::env(OPENLANE_VERBOSE) {0}
+set ::env(OPENLANE_VERSION) {cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988}
+set ::env(OPENROAD) {/build/}
+set ::env(OPENROAD_BIN) {openroad}
+set ::env(PARSITICS_CURRENT_DEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def}
+set ::env(PATH) {/openlane:/openlane/scripts:/build//bin:/build//bin/Linux-x86_64:/build//pdn/scripts:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin}
+set ::env(PDK) {gf180mcuC}
+set ::env(PDKPATH) {/home/htf6ry/GF180PDK//gf180mcuC}
+set ::env(PDK_ROOT) {/home/htf6ry/GF180PDK/}
+set ::env(PDN_CFG) {/openlane/scripts/openroad/common/pdn_cfg.tcl}
+set ::env(PLACEMENT_CURRENT_DEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/floorplan/6-pdn.def}
+set ::env(PLACE_SITE) {GF018hv5v_mcu_sc7}
+set ::env(PLACE_SITE_HEIGHT) {3.92}
+set ::env(PLACE_SITE_WIDTH) {0.56}
+set ::env(PL_BASIC_PLACEMENT) {0}
+set ::env(PL_ESTIMATE_PARASITICS) {1}
+set ::env(PL_INIT_COEFF) {0.00002}
+set ::env(PL_IO_ITER) {5}
+set ::env(PL_LIB) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib}
+set ::env(PL_MACRO_CHANNEL) {0 0}
+set ::env(PL_MACRO_HALO) {0 0}
+set ::env(PL_MAX_DISPLACEMENT_X) {500}
+set ::env(PL_MAX_DISPLACEMENT_Y) {100}
+set ::env(PL_OPTIMIZE_MIRRORING) {1}
+set ::env(PL_RANDOM_GLB_PLACEMENT) {0}
+set ::env(PL_RANDOM_INITIAL_PLACEMENT) {0}
+set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) {0}
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) {1}
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) {1}
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {1}
+set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) {0.1}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {20}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {20}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {0}
+set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) {1}
+set ::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
+set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) {0.05}
+set ::env(PL_RESIZER_TIE_SEPERATION) {0}
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1}
+set ::env(PL_ROUTABILITY_DRIVEN) {1}
+set ::env(PL_SKIP_INITIAL_PLACEMENT) {0}
+set ::env(PL_TARGET_DENSITY) {0.25}
+set ::env(PL_TIME_DRIVEN) {1}
+set ::env(PRIMARY_SIGNOFF_TOOL) {magic}
+set ::env(PROCESS) {180}
+set ::env(PWD) {/openlane}
+set ::env(QUIT_ON_HOLD_VIOLATIONS) {1}
+set ::env(QUIT_ON_ILLEGAL_OVERLAPS) {1}
+set ::env(QUIT_ON_LONG_WIRE) {0}
+set ::env(QUIT_ON_LVS_ERROR) {1}
+set ::env(QUIT_ON_MAGIC_DRC) {1}
+set ::env(QUIT_ON_SETUP_VIOLATIONS) {1}
+set ::env(QUIT_ON_TIMING_VIOLATIONS) {1}
+set ::env(QUIT_ON_TR_DRC) {1}
+set ::env(RCX_CC_MODEL) {10}
+set ::env(RCX_CONTEXT_DEPTH) {5}
+set ::env(RCX_CORNER_COUNT) {1}
+set ::env(RCX_COUPLING_THRESHOLD) {0.1}
+set ::env(RCX_MAX_RESISTANCE) {50}
+set ::env(RCX_MERGE_VIA_WIRE_RES) {1}
+set ::env(RCX_RULES) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.nom.magic}
+set ::env(RCX_RULES_MAX) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.max.magic}
+set ::env(RCX_RULES_MIN) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.min.magic}
+set ::env(RCX_SDC_FILE) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.sdc}
+set ::env(REPORTS_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports}
+set ::env(RESULTS_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results}
+set ::env(RIGHT_MARGIN_MULT) {12}
+set ::env(RIPPLE_CARRY_ADDER_MAP) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/rca_map.v}
+set ::env(ROUTING_CORES) {2}
+set ::env(ROUTING_CURRENT_DEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.def}
+set ::env(RSZ_DONT_TOUCH_RX) {\$^}
+set ::env(RSZ_LIB) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/resizer_gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib}
+set ::env(RSZ_USE_OLD_REMOVER) {0}
+set ::env(RT_MAX_LAYER) {Metal4}
+set ::env(RT_MIN_LAYER) {Metal2}
+set ::env(RUN_CVC) {1}
+set ::env(RUN_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29}
+set ::env(RUN_DRT) {1}
+set ::env(RUN_FILL_INSERTION) {1}
+set ::env(RUN_IRDROP_REPORT) {0}
+set ::env(RUN_KLAYOUT) {0}
+set ::env(RUN_KLAYOUT_DRC) {0}
+set ::env(RUN_KLAYOUT_XOR) {0}
+set ::env(RUN_LVS) {1}
+set ::env(RUN_MAGIC) {1}
+set ::env(RUN_MAGIC_DRC) {1}
+set ::env(RUN_SPEF_EXTRACTION) {1}
+set ::env(RUN_STANDALONE) {1}
+set ::env(RUN_TAG) {22_12_03_16_29}
+set ::env(RUN_TAP_DECAP_INSERTION) {1}
+set ::env(SCLPATH) {/home/htf6ry/GF180PDK//gf180mcuC/gf180mcu_fd_sc_mcu7t5v0}
+set ::env(SCRIPTS_DIR) {/openlane/scripts}
+set ::env(SHLVL) {1}
+set ::env(SPEF_EXTRACTOR) {openrcx}
+set ::env(START_TIME) {2022.12.03_21.29.36}
+set ::env(STA_PRE_CTS) {0}
+set ::env(STA_REPORT_POWER) {1}
+set ::env(STA_WRITE_LIB) {1}
+set ::env(STD_CELL_GROUND_PINS) {VSS}
+set ::env(STD_CELL_LIBRARY) {gf180mcu_fd_sc_mcu7t5v0}
+set ::env(STD_CELL_LIBRARY_CDL) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/cdl/gf180mcu_fd_sc_mcu7t5v0.cdl}
+set ::env(STD_CELL_LIBRARY_OPT) {gf180mcu_fd_sc_mcu7t5v0}
+set ::env(STD_CELL_POWER_PINS) {VDD}
+set ::env(SYNTH_ADDER_TYPE) {YOSYS}
+set ::env(SYNTH_BIN) {yosys}
+set ::env(SYNTH_BUFFERING) {1}
+set ::env(SYNTH_CAP_LOAD) {72.91}
+set ::env(SYNTH_CLK_DRIVING_CELL) {gf180mcu_fd_sc_mcu7t5v0__inv_4}
+set ::env(SYNTH_CLK_DRIVING_CELL_PIN) {ZN}
+set ::env(SYNTH_CLOCK_TRANSITION) {0.15}
+set ::env(SYNTH_CLOCK_UNCERTAINTY) {0.25}
+set ::env(SYNTH_DEFINES) {MPRJ_IO_PADS=38}
+set ::env(SYNTH_DRIVING_CELL) {gf180mcu_fd_sc_mcu7t5v0__inv_1}
+set ::env(SYNTH_DRIVING_CELL_PIN) {ZN}
+set ::env(SYNTH_ELABORATE_ONLY) {0}
+set ::env(SYNTH_EXTRA_MAPPING_FILE) {}
+set ::env(SYNTH_FLAT_TOP) {0}
+set ::env(SYNTH_LATCH_MAP) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/latch_map.v}
+set ::env(SYNTH_MAX_FANOUT) {10}
+set ::env(SYNTH_MAX_TRAN) {3}
+set ::env(SYNTH_MIN_BUF_PORT) {gf180mcu_fd_sc_mcu7t5v0__buf_1 I Z}
+set ::env(SYNTH_NO_FLAT) {0}
+set ::env(SYNTH_OPT) {0}
+set ::env(SYNTH_READ_BLACKBOX_LIB) {0}
+set ::env(SYNTH_SCRIPT) {/openlane/scripts/yosys/synth.tcl}
+set ::env(SYNTH_SHARE_RESOURCES) {1}
+set ::env(SYNTH_SIZING) {0}
+set ::env(SYNTH_STRATEGY) {AREA 0}
+set ::env(SYNTH_TIEHI_PORT) {gf180mcu_fd_sc_mcu7t5v0__tieh Z}
+set ::env(SYNTH_TIELO_PORT) {gf180mcu_fd_sc_mcu7t5v0__tiel ZN}
+set ::env(SYNTH_TIMING_DERATE) {0.05}
+set ::env(TAKE_LAYOUT_SCROT) {0}
+set ::env(TECH_LEF) {/home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef}
+set ::env(TECH_METAL_LAYERS) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(TERM) {xterm}
+set ::env(TERMINAL_OUTPUT) {/dev/null}
+set ::env(TMP_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp}
+set ::env(TOP_MARGIN_MULT) {4}
+set ::env(TRACKS_INFO_FILE) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info}
+set ::env(TRACKS_INFO_FILE_PROCESSED) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/config.tracks}
+set ::env(TRISTATE_BUFFER_MAP) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tribuff_map.v}
+set ::env(USE_ARC_ANTENNA_CHECK) {1}
+set ::env(USE_GPIO_PADS) {0}
+set ::env(VCHECK_OUTPUT) {}
+set ::env(VDD_NET) {vdd}
+set ::env(VDD_NETS) {vdd}
+set ::env(VDD_PIN) {vdd}
+set ::env(VERILOG_FILES) {/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v}
+set ::env(WIRE_RC_LAYER) {Metal2}
+set ::env(YOSYS_REWRITE_VERILOG) {0}
+set ::env(_) {/openlane/flow.tcl}
+set ::env(cts_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/cts}
+set ::env(cts_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/cts}
+set ::env(cts_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts}
+set ::env(cts_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts}
+set ::env(drc_prefix) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc}
+set ::env(eco_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/eco}
+set ::env(eco_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/eco}
+set ::env(eco_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/eco}
+set ::env(eco_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/eco}
+set ::env(floorplan_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan}
+set ::env(floorplan_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/floorplan}
+set ::env(floorplan_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/floorplan}
+set ::env(floorplan_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/floorplan}
+set ::env(fp_report_prefix) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/floorplan/3-initial_fp}
+set ::env(placement_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/placement}
+set ::env(placement_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/placement}
+set ::env(placement_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/placement}
+set ::env(placement_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement}
+set ::env(routing_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing}
+set ::env(routing_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/routing}
+set ::env(routing_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing}
+set ::env(routing_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing}
+set ::env(signoff_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff}
+set ::env(signoff_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff}
+set ::env(signoff_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff}
+set ::env(signoff_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff}
+set ::env(synth_report_prefix) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/synthesis/1-synthesis}
+set ::env(synthesis_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/synthesis}
+set ::env(synthesis_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/synthesis}
+set ::env(synthesis_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/synthesis}
+set ::env(synthesis_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis}
+set ::env(timer_end) {1670103271}
+set ::env(timer_routed) {1670103076}
+set ::env(timer_start) {1670102976}
diff --git a/openlane/cntr_example/runs/cntr_example/config_in.tcl b/openlane/cntr_example/runs/cntr_example/config_in.tcl
new file mode 100644
index 0000000..7a88c06
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/config_in.tcl
@@ -0,0 +1,48 @@
+# User config
+set script_dir [file dirname [file normalize [info script]]]
+
+# name of your project, should also match the name of the top module
+set ::env(DESIGN_NAME) cntr_example
+
+set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0"
+
+# add your source files here
+#set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/../../verilog/rtl/wrapped_multiplier.v \
+#set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/../../verilog/rtl/wrapped_multiplier.v \
+#    $::env(DESIGN_DIR)/../../verilog/rtl/multilib.v"
+set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/../../verilog/rtl/cntr_example.v]
+
+# set absolute size of the die to 300 x 300 um
+#set ::env(DIE_AREA) "0 0 900 900" for two 4-bit counter
+set ::env(DIE_AREA) "0 0 1500 1500"
+set ::env(FP_SIZING) absolute
+
+#set ::env(FP_CORE_UTIL) 40 for two 4-bit counter
+set ::env(FP_CORE_UTIL) 20
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
+# define number of IO pads
+set ::env(SYNTH_DEFINES) "MPRJ_IO_PADS=38"
+
+# clock period is ns
+# need 40MHz for VGA out = 25ns
+# copied from VGA example
+#set ::env(CLOCK_PERIOD) "35" for two 4-bit counter
+set ::env(CLOCK_PERIOD) "65"
+set ::env(CLOCK_PORT) "wb_clk_i"
+#set ::env(CLOCK_PORT) "clk"
+
+# macro needs to work inside Caravel, so can't be core and can't use metal 5
+set ::env(DESIGN_IS_CORE) 0
+set ::env(RT_MAX_LAYER) {Metal4}
+
+# define power straps so the macro works inside Caravel's PDN
+set ::env(VDD_NETS) [list {vdd}]
+set ::env(GND_NETS) [list {vss}]
+
+# regular pin order seems to help with aggregating all the macros for the group project
+#set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+set ::env(FP_IO_VTHICKNESS_MULT) 4
+set ::env(FP_IO_HTHICKNESS_MULT) 4
+
diff --git a/openlane/cntr_example/runs/cntr_example/logs/cts/10-cts.log b/openlane/cntr_example/runs/cntr_example/logs/cts/10-cts.log
new file mode 100644
index 0000000..e0ce5cd
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/cts/10-cts.log
@@ -0,0 +1,660 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO]: Setting RC values...
+[INFO]: Configuring cts characterization...
+[INFO]: Performing clock tree synthesis...
+[INFO]: Looking for the following net(s): wb_clk_i
+[INFO]: Running Clock Tree Synthesis...
+[INFO CTS-0049] Characterization buffer is: gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.
+[INFO CTS-0038] Number of created patterns = 50000.
+[INFO CTS-0038] Number of created patterns = 100000.
+[INFO CTS-0039] Number of created patterns = 137808.
+[INFO CTS-0084] Compiling LUT.
+Min. len    Max. len    Min. cap    Max. cap    Min. slew   Max. slew
+2           8           1           34          1           107         
+[WARNING CTS-0043] 4752 wires are pure wire and no slew degradation.
+TritonCTS forced slew degradation on these wires.
+[INFO CTS-0046]     Number of wire segments: 137808.
+[INFO CTS-0047]     Number of keys in characterization LUT: 1811.
+[INFO CTS-0048]     Actual min input cap: 1.
+[INFO CTS-0007] Net "wb_clk_i" found for clock "wb_clk_i".
+[INFO CTS-0010]  Clock net "wb_clk_i" has 20 sinks.
+[INFO CTS-0008] TritonCTS found 1 clock nets.
+[INFO CTS-0097] Characterization used 2 buffer(s) types.
+[INFO CTS-0027] Generating H-Tree topology for net wb_clk_i.
+[INFO CTS-0028]  Total number of sinks: 20.
+[INFO CTS-0029]  Sinks will be clustered in groups of up to 25 and with maximum cluster diameter of 50.0 um.
+[INFO CTS-0030]  Number of static layers: 0.
+[INFO CTS-0020]  Wire segment unit: 38000  dbu (19 um).
+[INFO CTS-0023]  Original sink region: [(19040, 2646000), (218400, 2779280)].
+[INFO CTS-0024]  Normalized sink region: [(0.501053, 69.6316), (5.74737, 73.1389)].
+[INFO CTS-0025]     Width:  5.2463.
+[INFO CTS-0026]     Height: 3.5074.
+[WARNING CTS-0045] Creating fake entries in the LUT.
+ Level 1
+    Direction: Horizontal
+    Sinks per sub-region: 10
+    Sub-region size: 2.6232 X 3.5074
+[INFO CTS-0034]     Segment length (rounded): 1.
+    Key: 137808 inSlew: 1 inCap: 1 outSlew: 2 load: 1 length: 1 delay: 1
+[INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
+[INFO CTS-0035]  Number of sinks covered: 20.
+[INFO CTS-0036]  Average source sink dist: 79120.00 dbu.
+[INFO CTS-0037]  Number of outlier sinks: 0.
+[INFO CTS-0018]     Created 3 clock buffers.
+[INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
+[INFO CTS-0013]     Maximum number of buffers in the clock path: 2.
+[INFO CTS-0015]     Created 3 clock nets.
+[INFO CTS-0016]     Fanout distribution for the current clock = 9:1, 11:1..
+[INFO CTS-0017]     Max level of the clock tree: 1.
+[INFO CTS-0098] Clock net "wb_clk_i"
+[INFO CTS-0099]  Sinks 20
+[INFO CTS-0100]  Leaf buffers 0
+[INFO CTS-0101]  Average sink wire length 140.89 um
+[INFO CTS-0102]  Path depth 2 - 2
+[INFO]: Repairing long wires on clock nets...
+[INFO RSZ-0058] Using max wire length 22815um.
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts/cntr_example.odb...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts/cntr_example.def...
+Writing timing constraints to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts/cntr_example.sdc...
+[INFO]: Legalizing...
+Placement Analysis
+---------------------------------
+total displacement         17.9 u
+average displacement        0.0 u
+max displacement            8.4 u
+original HPWL           60462.2 u
+legalized HPWL          60593.7 u
+delta HPWL                    0 %
+
+[INFO DPL-0020] Mirrored 63 instances
+[INFO DPL-0021] HPWL before           60593.7 u
+[INFO DPL-0022] HPWL after            60457.6 u
+[INFO DPL-0023] HPWL delta               -0.2 %
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts/cntr_example.odb...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts/cntr_example.def...
+Writing timing constraints to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts/cntr_example.sdc...
+cts_report
+[INFO CTS-0003] Total number of Clock Roots: 1.
+[INFO CTS-0004] Total number of Buffers Inserted: 3.
+[INFO CTS-0005] Total number of Clock Subnets: 3.
+[INFO CTS-0006] Total number of Sinks: 20.
+cts_report_end
+min_report
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.30    0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.70 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.40    1.14    1.84 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.05                           net16 (net)
+                  0.40    0.01    1.85 v _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  0.60    0.44    2.29 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     1    0.01                           _008_ (net)
+                  0.60    0.00    2.29 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.29   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.77 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.02   clock uncertainty
+                         -0.07    0.95   clock reconvergence pessimism
+                          0.02    0.97   library hold time
+                                  0.97   data required time
+-----------------------------------------------------------------------------
+                                  0.97   data required time
+                                 -2.29   data arrival time
+-----------------------------------------------------------------------------
+                                  1.32   slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.30    0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.70 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.55    1.30    2.00 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     5    0.04                           net21 (net)
+                  0.56    0.02    2.02 ^ _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.38    0.30    2.31 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _013_ (net)
+                  0.38    0.00    2.32 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.32   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.77 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.02   clock uncertainty
+                         -0.07    0.95   clock reconvergence pessimism
+                          0.03    0.97   library hold time
+                                  0.97   data required time
+-----------------------------------------------------------------------------
+                                  0.97   data required time
+                                 -2.32   data arrival time
+-----------------------------------------------------------------------------
+                                  1.34   slack (MET)
+
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.31    0.71 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.71 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.57    1.31    2.02 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     5    0.04                           net6 (net)
+                  0.57    0.01    2.03 ^ _087_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.39    0.30    2.33 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _017_ (net)
+                  0.39    0.00    2.34 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.34   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.34    0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.78 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.03   clock uncertainty
+                         -0.07    0.96   clock reconvergence pessimism
+                          0.02    0.98   library hold time
+                                  0.98   data required time
+-----------------------------------------------------------------------------
+                                  0.98   data required time
+                                 -2.34   data arrival time
+-----------------------------------------------------------------------------
+                                  1.36   slack (MET)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.30    0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.70 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.57    1.31    2.01 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     5    0.04                           net10 (net)
+                  0.58    0.01    2.03 ^ _051_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.40    0.31    2.33 v _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _001_ (net)
+                  0.40    0.00    2.34 v _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.34   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.77 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.02   clock uncertainty
+                         -0.07    0.95   clock reconvergence pessimism
+                          0.02    0.97   library hold time
+                                  0.97   data required time
+-----------------------------------------------------------------------------
+                                  0.97   data required time
+                                 -2.34   data arrival time
+-----------------------------------------------------------------------------
+                                  1.37   slack (MET)
+
+
+Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.30    0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.70 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.63    1.35    2.05 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     5    0.05                           net13 (net)
+                  0.63    0.01    2.06 ^ _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.38    0.29    2.35 v _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _005_ (net)
+                  0.38    0.00    2.36 v _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.36   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.77 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.02   clock uncertainty
+                         -0.07    0.95   clock reconvergence pessimism
+                          0.03    0.97   library hold time
+                                  0.97   data required time
+-----------------------------------------------------------------------------
+                                  0.97   data required time
+                                 -2.36   data arrival time
+-----------------------------------------------------------------------------
+                                  1.38   slack (MET)
+
+
+min_report_end
+max_report
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.34    0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.78 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.71    1.54    2.32 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.06                           net9 (net)
+                  0.71    0.03    2.34 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.72    3.06 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[16] (net)
+                  0.48    0.00    3.06 ^ io_out[16] (out)
+                                  3.06   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.06   data arrival time
+-----------------------------------------------------------------------------
+                                 48.69   slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[12] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.77 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.71    1.54    2.31 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.06                           net5 (net)
+                  0.72    0.03    2.34 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.72    3.05 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[12] (net)
+                  0.48    0.00    3.05 ^ io_out[12] (out)
+                                  3.05   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.05   data arrival time
+-----------------------------------------------------------------------------
+                                 48.70   slack (MET)
+
+
+Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[3] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.77 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  0.83    1.51    2.28 ^ _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     2    0.03                           net15 (net)
+                  0.83    0.01    2.30 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.73    3.03 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[3] (net)
+                  0.48    0.00    3.03 ^ io_out[3] (out)
+                                  3.03   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.03   data arrival time
+-----------------------------------------------------------------------------
+                                 48.72   slack (MET)
+
+
+Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[8] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.34    0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.78 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.66    1.51    2.29 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.05                           net20 (net)
+                  0.66    0.02    2.31 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.71    3.02 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[8] (net)
+                  0.48    0.00    3.02 ^ io_out[8] (out)
+                                  3.02   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.02   data arrival time
+-----------------------------------------------------------------------------
+                                 48.73   slack (MET)
+
+
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.34    0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.78 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.65    1.51    2.29 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.05                           net2 (net)
+                  0.65    0.00    2.29 ^ output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.70    2.99 ^ output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[0] (net)
+                  0.48    0.00    2.99 ^ io_out[0] (out)
+                                  2.99   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.99   data arrival time
+-----------------------------------------------------------------------------
+                                 48.76   slack (MET)
+
+
+max_report_end
+check_report
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.34    0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.78 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.71    1.54    2.32 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.06                           net9 (net)
+                  0.71    0.03    2.34 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.72    3.06 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[16] (net)
+                  0.48    0.00    3.06 ^ io_out[16] (out)
+                                  3.06   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.06   data arrival time
+-----------------------------------------------------------------------------
+                                 48.69   slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
+check_report_end
+check_slew
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
+check_slew_end
+tns_report
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
+tns_report_end
+wns_report
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
+wns_report_end
+worst_slack
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 48.69
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 1.32
+worst_slack_end
+clock_skew
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency      CRPR       Skew
+_106_/CLK ^
+   0.78
+_108_/CLK ^
+   0.70     -0.04       0.04
+
+clock_skew_end
+power_report
+
+===========================================================================
+ report_power
+============================================================================
+Group                  Internal  Switching    Leakage      Total
+                          Power      Power      Power      Power (Watts)
+----------------------------------------------------------------
+Sequential             7.07e-05   7.86e-06   1.98e-09   7.86e-05  42.6%
+Combinational          6.84e-05   3.72e-05   3.25e-07   1.06e-04  57.4%
+Macro                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+----------------------------------------------------------------
+Total                  1.39e-04   4.50e-05   3.27e-07   1.85e-04 100.0%
+                          75.4%      24.4%       0.2%
+power_report_end
+area_report
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 67586 u^2 3% utilization.
+area_report_end
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts/cntr_example.odb...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts/cntr_example.def...
+Writing timing constraints to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts/cntr_example.sdc...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/cts/11-resizer.log b/openlane/cntr_example/runs/cntr_example/logs/cts/11-resizer.log
new file mode 100644
index 0000000..6f4a3a8
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/cts/11-resizer.log
@@ -0,0 +1,601 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO]: Setting RC values...
+[INFO RSZ-0033] No hold violations found.
+Placement Analysis
+---------------------------------
+total displacement          0.0 u
+average displacement        0.0 u
+max displacement            0.0 u
+original HPWL           60457.6 u
+legalized HPWL          60593.7 u
+delta HPWL                    0 %
+
+[INFO DPL-0020] Mirrored 63 instances
+[INFO DPL-0021] HPWL before           60593.7 u
+[INFO DPL-0022] HPWL after            60457.6 u
+[INFO DPL-0023] HPWL delta               -0.2 %
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.odb...
+Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.def...
+Writing timing constraints to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.sdc...
+min_report
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.30    0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.70 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.40    1.14    1.84 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.05                           net16 (net)
+                  0.40    0.01    1.85 v _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  0.60    0.44    2.29 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     1    0.01                           _008_ (net)
+                  0.60    0.00    2.29 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.29   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.77 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.02   clock uncertainty
+                         -0.07    0.95   clock reconvergence pessimism
+                          0.02    0.97   library hold time
+                                  0.97   data required time
+-----------------------------------------------------------------------------
+                                  0.97   data required time
+                                 -2.29   data arrival time
+-----------------------------------------------------------------------------
+                                  1.32   slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.30    0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.70 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.55    1.30    2.00 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     5    0.04                           net21 (net)
+                  0.56    0.02    2.02 ^ _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.38    0.30    2.31 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _013_ (net)
+                  0.38    0.00    2.32 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.32   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.77 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.02   clock uncertainty
+                         -0.07    0.95   clock reconvergence pessimism
+                          0.03    0.97   library hold time
+                                  0.97   data required time
+-----------------------------------------------------------------------------
+                                  0.97   data required time
+                                 -2.32   data arrival time
+-----------------------------------------------------------------------------
+                                  1.34   slack (MET)
+
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.31    0.71 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.71 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.57    1.31    2.02 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     5    0.04                           net6 (net)
+                  0.57    0.01    2.03 ^ _087_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.39    0.30    2.33 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _017_ (net)
+                  0.39    0.00    2.34 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.34   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.34    0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.78 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.03   clock uncertainty
+                         -0.07    0.96   clock reconvergence pessimism
+                          0.02    0.98   library hold time
+                                  0.98   data required time
+-----------------------------------------------------------------------------
+                                  0.98   data required time
+                                 -2.34   data arrival time
+-----------------------------------------------------------------------------
+                                  1.36   slack (MET)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.30    0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.70 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.57    1.31    2.01 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     5    0.04                           net10 (net)
+                  0.58    0.01    2.03 ^ _051_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.40    0.31    2.33 v _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _001_ (net)
+                  0.40    0.00    2.34 v _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.34   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.77 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.02   clock uncertainty
+                         -0.07    0.95   clock reconvergence pessimism
+                          0.02    0.97   library hold time
+                                  0.97   data required time
+-----------------------------------------------------------------------------
+                                  0.97   data required time
+                                 -2.34   data arrival time
+-----------------------------------------------------------------------------
+                                  1.37   slack (MET)
+
+
+Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.30    0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.70 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.63    1.35    2.05 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     5    0.05                           net13 (net)
+                  0.63    0.01    2.06 ^ _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.38    0.29    2.35 v _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _005_ (net)
+                  0.38    0.00    2.36 v _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.36   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.77 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.02   clock uncertainty
+                         -0.07    0.95   clock reconvergence pessimism
+                          0.03    0.97   library hold time
+                                  0.97   data required time
+-----------------------------------------------------------------------------
+                                  0.97   data required time
+                                 -2.36   data arrival time
+-----------------------------------------------------------------------------
+                                  1.38   slack (MET)
+
+
+min_report_end
+max_report
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.34    0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.78 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.71    1.54    2.32 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.06                           net9 (net)
+                  0.71    0.03    2.34 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.72    3.06 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[16] (net)
+                  0.48    0.00    3.06 ^ io_out[16] (out)
+                                  3.06   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.06   data arrival time
+-----------------------------------------------------------------------------
+                                 48.69   slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[12] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.77 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.71    1.54    2.31 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.06                           net5 (net)
+                  0.72    0.03    2.34 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.72    3.05 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[12] (net)
+                  0.48    0.00    3.05 ^ io_out[12] (out)
+                                  3.05   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.05   data arrival time
+-----------------------------------------------------------------------------
+                                 48.70   slack (MET)
+
+
+Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[3] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.77 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  0.83    1.51    2.28 ^ _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     2    0.03                           net15 (net)
+                  0.83    0.01    2.30 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.73    3.03 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[3] (net)
+                  0.48    0.00    3.03 ^ io_out[3] (out)
+                                  3.03   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.03   data arrival time
+-----------------------------------------------------------------------------
+                                 48.72   slack (MET)
+
+
+Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[8] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.34    0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.78 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.66    1.51    2.29 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.05                           net20 (net)
+                  0.66    0.02    2.31 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.71    3.02 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[8] (net)
+                  0.48    0.00    3.02 ^ io_out[8] (out)
+                                  3.02   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.02   data arrival time
+-----------------------------------------------------------------------------
+                                 48.73   slack (MET)
+
+
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.34    0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.78 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.65    1.51    2.29 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.05                           net2 (net)
+                  0.65    0.00    2.29 ^ output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.70    2.99 ^ output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[0] (net)
+                  0.48    0.00    2.99 ^ io_out[0] (out)
+                                  2.99   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.99   data arrival time
+-----------------------------------------------------------------------------
+                                 48.76   slack (MET)
+
+
+max_report_end
+check_report
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.34    0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.78 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.71    1.54    2.32 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.06                           net9 (net)
+                  0.71    0.03    2.34 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.72    3.06 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[16] (net)
+                  0.48    0.00    3.06 ^ io_out[16] (out)
+                                  3.06   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.06   data arrival time
+-----------------------------------------------------------------------------
+                                 48.69   slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
+check_report_end
+check_slew
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
+check_slew_end
+tns_report
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
+tns_report_end
+wns_report
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
+wns_report_end
+worst_slack
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 48.69
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 1.32
+worst_slack_end
+clock_skew
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency      CRPR       Skew
+_106_/CLK ^
+   0.78
+_108_/CLK ^
+   0.70     -0.04       0.04
+
+clock_skew_end
+power_report
+
+===========================================================================
+ report_power
+============================================================================
+Group                  Internal  Switching    Leakage      Total
+                          Power      Power      Power      Power (Watts)
+----------------------------------------------------------------
+Sequential             7.07e-05   7.86e-06   1.98e-09   7.86e-05  42.6%
+Combinational          6.84e-05   3.72e-05   3.25e-07   1.06e-04  57.4%
+Macro                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+----------------------------------------------------------------
+Total                  1.39e-04   4.50e-05   3.27e-07   1.85e-04 100.0%
+                          75.4%      24.4%       0.2%
+power_report_end
+area_report
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 67586 u^2 3% utilization.
+area_report_end
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.odb...
+Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.def...
+Writing timing constraints to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.sdc...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/floorplan/3-initial_fp.log b/openlane/cntr_example/runs/cntr_example/logs/floorplan/3-initial_fp.log
new file mode 100644
index 0000000..c8ec028
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/floorplan/3-initial_fp.log
@@ -0,0 +1,16 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO ODB-0222] Reading LEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef
+[INFO ODB-0223]     Created 13 technology layers
+[INFO ODB-0224]     Created 60 technology vias
+[INFO ODB-0225]     Created 229 library cells
+[INFO ODB-0226] Finished LEF file:  /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef
+Reading netlist...
+[INFO IFP-0001] Added 374 rows of 2654 sites.
+[INFO IFP-0030] Inserted 0 tiecells using gf180mcu_fd_sc_mcu7t5v0__tiel/ZN.
+[INFO IFP-0030] Inserted 0 tiecells using gf180mcu_fd_sc_mcu7t5v0__tieh/Z.
+[INFO] Extracting DIE_AREA and CORE_AREA from the floorplan
+[INFO] Floorplanned on a die area of 0.0 0.0 1500.0 1500.0 (microns). Saving to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/floorplan/3-initial_fp_die_area.rpt.
+[INFO] Floorplanned on a core area of 6.72 15.68 1492.96 1481.76 (microns). Saving to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/floorplan/3-initial_fp_core_area.rpt.
+[WARNING] Did not save OpenROAD database!
diff --git a/openlane/cntr_example/runs/cntr_example/logs/floorplan/4-io.log b/openlane/cntr_example/runs/cntr_example/logs/floorplan/4-io.log
new file mode 100644
index 0000000..718922b
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/floorplan/4-io.log
@@ -0,0 +1,8 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Found 0 macro blocks.
+Using 1u default distance from corners.
+[INFO PPL-0007] Random pin placement.
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/floorplan/4-io.odb...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/floorplan/4-io.def...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/floorplan/5-tap.log b/openlane/cntr_example/runs/cntr_example/logs/floorplan/5-tap.log
new file mode 100644
index 0000000..722ea74
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/floorplan/5-tap.log
@@ -0,0 +1,7 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO TAP-0004] Inserted 748 endcaps.
+[INFO TAP-0005] Inserted 13914 tapcells.
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/floorplan/cntr_example.odb...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/floorplan/cntr_example.def...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/floorplan/6-pdn.log b/openlane/cntr_example/runs/cntr_example/logs/floorplan/6-pdn.log
new file mode 100644
index 0000000..87eec12
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/floorplan/6-pdn.log
@@ -0,0 +1,61 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO PDN-0001] Inserting grid: stdcell_grid
+[WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area.
+[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
+[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
+[WARNING PSM-0019] Voltage on net vdd is not explicitly set.
+[WARNING PSM-0022] Using voltage 0.000V for VDD network.
+[WARNING PSM-0065] VSRC location not specified, using default checkerboard pattern with one VDD every size bumps in x-direction and one in two bumps in the y-direction
+[INFO PSM-0076] Setting metal node density to be standard cell height times 5.
+[WARNING PSM-0030] VSRC location at (119.840um, 118.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (176.640um, 121.520um).
+[WARNING PSM-0030] VSRC location at (959.840um, 118.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (944.640um, 121.520um).
+[WARNING PSM-0030] VSRC location at (399.840um, 258.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (330.240um, 254.800um).
+[WARNING PSM-0030] VSRC location at (1239.840um, 258.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (1251.840um, 262.640um).
+[WARNING PSM-0030] VSRC location at (679.840um, 398.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (637.440um, 395.920um).
+[WARNING PSM-0030] VSRC location at (119.840um, 538.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (176.640um, 537.040um).
+[WARNING PSM-0030] VSRC location at (959.840um, 538.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (944.640um, 537.040um).
+[WARNING PSM-0030] VSRC location at (399.840um, 678.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (330.240um, 678.160um).
+[WARNING PSM-0030] VSRC location at (1239.840um, 678.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (1251.840um, 678.160um).
+[WARNING PSM-0030] VSRC location at (679.840um, 818.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (637.440um, 819.280um).
+[WARNING PSM-0030] VSRC location at (119.840um, 958.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (176.640um, 960.400um).
+[WARNING PSM-0030] VSRC location at (959.840um, 958.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (944.640um, 960.400um).
+[WARNING PSM-0030] VSRC location at (399.840um, 1098.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (330.240um, 1101.520um).
+[WARNING PSM-0030] VSRC location at (1239.840um, 1098.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (1251.840um, 1101.520um).
+[WARNING PSM-0030] VSRC location at (679.840um, 1238.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (637.440um, 1234.800um).
+[WARNING PSM-0030] VSRC location at (119.840um, 1378.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (176.640um, 1375.920um).
+[WARNING PSM-0030] VSRC location at (959.840um, 1378.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (944.640um, 1375.920um).
+[INFO PSM-0031] Number of PDN nodes on net vdd = 20403.
+[INFO PSM-0064] Number of voltage sources = 17.
+[INFO PSM-0040] All PDN stripes on net vdd are connected.
+[WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area.
+[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
+[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
+[WARNING PSM-0019] Voltage on net vss is not explicitly set.
+[WARNING PSM-0021] Using voltage 0.000V for ground network.
+[WARNING PSM-0065] VSRC location not specified, using default checkerboard pattern with one VDD every size bumps in x-direction and one in two bumps in the y-direction
+[INFO PSM-0076] Setting metal node density to be standard cell height times 5.
+[WARNING PSM-0030] VSRC location at (119.840um, 118.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (99.840um, 117.600um).
+[WARNING PSM-0030] VSRC location at (959.840um, 118.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (1021.440um, 117.600um).
+[WARNING PSM-0030] VSRC location at (399.840um, 258.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (407.040um, 258.720um).
+[WARNING PSM-0030] VSRC location at (1239.840um, 258.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (1175.040um, 258.720um).
+[WARNING PSM-0030] VSRC location at (679.840um, 398.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (714.240um, 399.840um).
+[WARNING PSM-0030] VSRC location at (119.840um, 538.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (99.840um, 540.960um).
+[WARNING PSM-0030] VSRC location at (959.840um, 538.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (1021.440um, 540.960um).
+[WARNING PSM-0030] VSRC location at (399.840um, 678.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (407.040um, 682.080um).
+[WARNING PSM-0030] VSRC location at (1239.840um, 678.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (1175.040um, 682.080um).
+[WARNING PSM-0030] VSRC location at (679.840um, 818.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (714.240um, 815.360um).
+[WARNING PSM-0030] VSRC location at (119.840um, 958.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (99.840um, 956.480um).
+[WARNING PSM-0030] VSRC location at (959.840um, 958.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (1021.440um, 956.480um).
+[WARNING PSM-0030] VSRC location at (399.840um, 1098.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (407.040um, 1097.600um).
+[WARNING PSM-0030] VSRC location at (1239.840um, 1098.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (1175.040um, 1097.600um).
+[WARNING PSM-0030] VSRC location at (679.840um, 1238.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (714.240um, 1238.720um).
+[WARNING PSM-0030] VSRC location at (119.840um, 1378.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (99.840um, 1379.840um).
+[WARNING PSM-0030] VSRC location at (959.840um, 1378.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (1021.440um, 1379.840um).
+[INFO PSM-0031] Number of PDN nodes on net vss = 20512.
+[INFO PSM-0064] Number of voltage sources = 17.
+[INFO PSM-0040] All PDN stripes on net vss are connected.
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/floorplan/6-pdn.odb...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/floorplan/6-pdn.def...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/placement/7-global.log b/openlane/cntr_example/runs/cntr_example/logs/placement/7-global.log
new file mode 100644
index 0000000..da8647a
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/placement/7-global.log
@@ -0,0 +1,812 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO]: Setting RC values...
+[INFO]: Setting signal min routing layer to: Metal2 and clock min routing layer to Metal2. 
+[INFO]: Setting signal max routing layer to: Metal4 and clock max routing layer to Metal4. 
+[INFO GPL-0002] DBU: 2000
+[INFO GPL-0003] SiteSize: 1120 7840
+[INFO GPL-0004] CoreAreaLxLy: 13440 31360
+[INFO GPL-0005] CoreAreaUxUy: 2985920 2963520
+[INFO GPL-0006] NumInstances: 13999
+[INFO GPL-0007] NumPlaceInstances: 85
+[INFO GPL-0008] NumFixedInstances: 13914
+[INFO GPL-0009] NumDummyInstances: 0
+[INFO GPL-0010] NumNets: 87
+[INFO GPL-0011] NumPins: 277
+[INFO GPL-0012] DieAreaLxLy: 0 0
+[INFO GPL-0013] DieAreaUxUy: 3000000 3000000
+[INFO GPL-0014] CoreAreaLxLy: 13440 31360
+[INFO GPL-0015] CoreAreaUxUy: 2985920 2963520
+[INFO GPL-0016] CoreArea: 8715786956800
+[INFO GPL-0017] NonPlaceInstsArea: 244352102400
+[INFO GPL-0018] PlaceInstsArea: 8710553600
+[INFO GPL-0019] Util(%): 0.10
+[INFO GPL-0020] StdInstsArea: 8710553600
+[INFO GPL-0021] MacroInstsArea: 0
+[InitialPlace]  Iter: 1 CG residual: 0.00001293 HPWL: 121504480
+[InitialPlace]  Iter: 2 CG residual: 0.00000011 HPWL: 50502279
+[InitialPlace]  Iter: 3 CG residual: 0.00000011 HPWL: 50387047
+[InitialPlace]  Iter: 4 CG residual: 0.00000166 HPWL: 50136908
+[InitialPlace]  Iter: 5 CG residual: 0.00000208 HPWL: 49581905
+[INFO GPL-0031] FillerInit: NumGCells: 22053
+[INFO GPL-0032] FillerInit: NumGNets: 87
+[INFO GPL-0033] FillerInit: NumGPins: 277
+[INFO GPL-0023] TargetDensity: 0.25
+[INFO GPL-0024] AveragePlaceInstArea: 102477101
+[INFO GPL-0025] IdealBinArea: 409908416
+[INFO GPL-0026] IdealBinCnt: 21262
+[INFO GPL-0027] TotalBinArea: 8715786956800
+[INFO GPL-0028] BinCnt: 128 128
+[INFO GPL-0029] BinSize: 23223 22908
+[INFO GPL-0030] NumBins: 16384
+[NesterovSolve] Iter: 1 overflow: 0.372824 HPWL: 48586473
+[INFO GPL-0100] worst slack 4.97e-08
+[INFO GPL-0103] Weighted 25 nets.
+[NesterovSolve] Snapshot saved at iter = 0
+[NesterovSolve] Iter: 10 overflow: 0.350848 HPWL: 50561001
+[NesterovSolve] Iter: 20 overflow: 0.373211 HPWL: 53612478
+[NesterovSolve] Iter: 30 overflow: 0.427115 HPWL: 58290744
+[NesterovSolve] Iter: 40 overflow: 0.439436 HPWL: 65637616
+[NesterovSolve] Iter: 50 overflow: 0.487212 HPWL: 75700722
+[NesterovSolve] Iter: 60 overflow: 0.516023 HPWL: 90249661
+[NesterovSolve] Iter: 70 overflow: 0.515241 HPWL: 110017678
+[NesterovSolve] Iter: 80 overflow: 0.517279 HPWL: 132826103
+[NesterovSolve] Iter: 90 overflow: 0.550264 HPWL: 147375030
+[NesterovSolve] Iter: 100 overflow: 0.545525 HPWL: 144241248
+[NesterovSolve] Iter: 110 overflow: 0.545449 HPWL: 138893993
+[NesterovSolve] Iter: 120 overflow: 0.528501 HPWL: 135361146
+[NesterovSolve] Iter: 130 overflow: 0.531204 HPWL: 135325843
+[NesterovSolve] Iter: 140 overflow: 0.514775 HPWL: 138378408
+[NesterovSolve] Iter: 150 overflow: 0.544424 HPWL: 141104434
+[NesterovSolve] Iter: 160 overflow: 0.541205 HPWL: 141902535
+[NesterovSolve] Iter: 170 overflow: 0.514129 HPWL: 139036037
+[NesterovSolve] Iter: 180 overflow: 0.513492 HPWL: 136813973
+[NesterovSolve] Iter: 190 overflow: 0.543146 HPWL: 135837556
+[NesterovSolve] Iter: 200 overflow: 0.513345 HPWL: 140533706
+[NesterovSolve] Iter: 210 overflow: 0.54293 HPWL: 143781338
+[NesterovSolve] Iter: 220 overflow: 0.543094 HPWL: 143942155
+[NesterovSolve] Iter: 230 overflow: 0.543562 HPWL: 140252004
+[NesterovSolve] Iter: 240 overflow: 0.51372 HPWL: 136703618
+[NesterovSolve] Iter: 250 overflow: 0.543647 HPWL: 134993615
+[NesterovSolve] Iter: 260 overflow: 0.520328 HPWL: 137469985
+[NesterovSolve] Iter: 270 overflow: 0.54296 HPWL: 141393638
+[NesterovSolve] Iter: 280 overflow: 0.542662 HPWL: 143600611
+[NesterovSolve] Iter: 290 overflow: 0.542433 HPWL: 142224251
+[NesterovSolve] Iter: 300 overflow: 0.542025 HPWL: 138951207
+[NesterovSolve] Iter: 310 overflow: 0.54166 HPWL: 136187240
+[NesterovSolve] Iter: 320 overflow: 0.541248 HPWL: 134800427
+[NesterovSolve] Iter: 330 overflow: 0.545272 HPWL: 147079069
+[NesterovSolve] Iter: 340 overflow: 0.510172 HPWL: 125715192
+[NesterovSolve] Iter: 350 overflow: 0.53928 HPWL: 110138217
+[NesterovSolve] Iter: 360 overflow: 0.53873 HPWL: 112705291
+[NesterovSolve] Iter: 370 overflow: 0.538178 HPWL: 118909907
+[NesterovSolve] Iter: 380 overflow: 0.507703 HPWL: 118580853
+[NesterovSolve] Iter: 390 overflow: 0.507454 HPWL: 111114835
+[NesterovSolve] Iter: 400 overflow: 0.536392 HPWL: 110156425
+[NesterovSolve] Iter: 410 overflow: 0.510704 HPWL: 122782417
+[NesterovSolve] Iter: 420 overflow: 0.536132 HPWL: 140675852
+[NesterovSolve] Iter: 430 overflow: 0.515416 HPWL: 145230105
+[NesterovSolve] Iter: 440 overflow: 0.535174 HPWL: 139774171
+[NesterovSolve] Iter: 450 overflow: 0.534075 HPWL: 134691805
+[NesterovSolve] Iter: 460 overflow: 0.518433 HPWL: 131315653
+[NesterovSolve] Iter: 470 overflow: 0.530573 HPWL: 131390099
+[NesterovSolve] Iter: 480 overflow: 0.528603 HPWL: 134297720
+[NesterovSolve] Iter: 490 overflow: 0.497286 HPWL: 138012032
+[NesterovSolve] Iter: 500 overflow: 0.494122 HPWL: 141626468
+[NesterovSolve] Iter: 510 overflow: 0.472386 HPWL: 143718905
+[NesterovSolve] Iter: 520 overflow: 0.525096 HPWL: 143301667
+[NesterovSolve] Iter: 530 overflow: 0.525017 HPWL: 140819193
+[NesterovSolve] Iter: 540 overflow: 0.520695 HPWL: 138004987
+[NesterovSolve] Iter: 550 overflow: 0.495062 HPWL: 136381809
+[NesterovSolve] Iter: 560 overflow: 0.525084 HPWL: 136568011
+[NesterovSolve] Iter: 570 overflow: 0.498785 HPWL: 137886850
+[NesterovSolve] Iter: 580 overflow: 0.471509 HPWL: 137542611
+[NesterovSolve] Iter: 590 overflow: 0.366329 HPWL: 135329251
+[NesterovSolve] Iter: 600 overflow: 0.404556 HPWL: 134986774
+[NesterovSolve] Iter: 610 overflow: 0.321349 HPWL: 136033179
+[NesterovSolve] Iter: 620 overflow: 0.313206 HPWL: 135201733
+[NesterovSolve] Iter: 630 overflow: 0.317341 HPWL: 134441402
+[NesterovSolve] Iter: 640 overflow: 0.319015 HPWL: 134816719
+[INFO GPL-0100] worst slack 4.94e-08
+[INFO GPL-0103] Weighted 25 nets.
+[NesterovSolve] Iter: 650 overflow: 0.285066 HPWL: 134216573
+[NesterovSolve] Iter: 660 overflow: 0.254171 HPWL: 134170608
+[INFO GPL-0100] worst slack 4.94e-08
+[INFO GPL-0103] Weighted 25 nets.
+[NesterovSolve] Iter: 670 overflow: 0.242709 HPWL: 134205549
+[NesterovSolve] Iter: 680 overflow: 0.208242 HPWL: 133888686
+[NesterovSolve] Iter: 690 overflow: 0.22342 HPWL: 134110573
+[NesterovSolve] Iter: 700 overflow: 0.198634 HPWL: 134329903
+[INFO GPL-0075] Routability numCall: 1 inflationIterCnt: 1 bloatIterCnt: 0
+[INFO GPL-0036] TileLxLy: 0 0
+[INFO GPL-0037] TileSize: 16800 16800
+[INFO GPL-0038] TileCnt: 178 178
+[INFO GPL-0039] numRoutingLayers: 5
+[INFO GPL-0040] NumTiles: 31684
+[INFO GPL-0063] TotalRouteOverflowH2: 0.0
+[INFO GPL-0064] TotalRouteOverflowV2: 0.0
+[INFO GPL-0065] OverflowTileCnt2: 0
+[INFO GPL-0066] 0.5%RC: 0.6089627129636752
+[INFO GPL-0067] 1.0%RC: 0.589171995402901
+[INFO GPL-0068] 2.0%RC: 0.5446571077456315
+[INFO GPL-0069] 5.0%RC: 0.5040568925996609
+[INFO GPL-0070] 0.5rcK: 1.0
+[INFO GPL-0071] 1.0rcK: 1.0
+[INFO GPL-0072] 2.0rcK: 0.0
+[INFO GPL-0073] 5.0rcK: 0.0
+[INFO GPL-0074] FinalRC: 0.59906733
+[NesterovSolve] Iter: 710 overflow: 0.209623 HPWL: 134282246
+[NesterovSolve] Iter: 720 overflow: 0.21514 HPWL: 134505639
+[NesterovSolve] Iter: 730 overflow: 0.204589 HPWL: 134766989
+[NesterovSolve] Iter: 740 overflow: 0.214148 HPWL: 134843104
+[NesterovSolve] Iter: 750 overflow: 0.202656 HPWL: 134645136
+[NesterovSolve] Iter: 760 overflow: 0.195019 HPWL: 134875771
+[NesterovSolve] Iter: 770 overflow: 0.19559 HPWL: 134717111
+[NesterovSolve] Iter: 780 overflow: 0.18259 HPWL: 134639125
+[NesterovSolve] Iter: 790 overflow: 0.183677 HPWL: 134447965
+[NesterovSolve] Iter: 800 overflow: 0.18512 HPWL: 134695018
+[NesterovSolve] Iter: 810 overflow: 0.183195 HPWL: 135042766
+[NesterovSolve] Iter: 820 overflow: 0.180501 HPWL: 135499335
+[NesterovSolve] Iter: 830 overflow: 0.192978 HPWL: 136208135
+[NesterovSolve] Iter: 840 overflow: 0.200543 HPWL: 137006193
+[NesterovSolve] Iter: 850 overflow: 0.183627 HPWL: 137149846
+[NesterovSolve] Iter: 860 overflow: 0.203779 HPWL: 136662001
+[NesterovSolve] Iter: 870 overflow: 0.20725 HPWL: 135861432
+[NesterovSolve] Iter: 880 overflow: 0.205776 HPWL: 134977516
+[NesterovSolve] Iter: 890 overflow: 0.178879 HPWL: 134369153
+[NesterovSolve] Iter: 900 overflow: 0.2044 HPWL: 134332888
+[NesterovSolve] Iter: 910 overflow: 0.17475 HPWL: 134749706
+[NesterovSolve] Iter: 920 overflow: 0.206754 HPWL: 135579558
+[NesterovSolve] Iter: 930 overflow: 0.207131 HPWL: 135869773
+[NesterovSolve] Iter: 940 overflow: 0.186968 HPWL: 136040301
+[NesterovSolve] Iter: 950 overflow: 0.204622 HPWL: 136213001
+[NesterovSolve] Iter: 960 overflow: 0.20721 HPWL: 135722848
+[NesterovSolve] Iter: 970 overflow: 0.1954 HPWL: 135792198
+[NesterovSolve] Iter: 980 overflow: 0.173967 HPWL: 135616630
+[NesterovSolve] Iter: 990 overflow: 0.183282 HPWL: 136002247
+[NesterovSolve] Iter: 1000 overflow: 0.187069 HPWL: 136221281
+[NesterovSolve] Iter: 1010 overflow: 0.207369 HPWL: 136336667
+[NesterovSolve] Iter: 1020 overflow: 0.202625 HPWL: 136078451
+[NesterovSolve] Iter: 1030 overflow: 0.180536 HPWL: 135630083
+[NesterovSolve] Iter: 1040 overflow: 0.176703 HPWL: 135066344
+[NesterovSolve] Iter: 1050 overflow: 0.205947 HPWL: 134276346
+[NesterovSolve] Iter: 1060 overflow: 0.203544 HPWL: 134381744
+[NesterovSolve] Iter: 1070 overflow: 0.173962 HPWL: 134145288
+[NesterovSolve] Iter: 1080 overflow: 0.205698 HPWL: 134140058
+[NesterovSolve] Iter: 1090 overflow: 0.204804 HPWL: 133970671
+[NesterovSolve] Iter: 1100 overflow: 0.203792 HPWL: 134011195
+[NesterovSolve] Iter: 1110 overflow: 0.191322 HPWL: 134246391
+[NesterovSolve] Iter: 1120 overflow: 0.179055 HPWL: 134361477
+[NesterovSolve] Iter: 1130 overflow: 0.205704 HPWL: 134199141
+[NesterovSolve] Iter: 1140 overflow: 0.20721 HPWL: 134260630
+[NesterovSolve] Iter: 1150 overflow: 0.203666 HPWL: 134322054
+[NesterovSolve] Iter: 1160 overflow: 0.20721 HPWL: 134280340
+[NesterovSolve] Iter: 1170 overflow: 0.206849 HPWL: 134537678
+[NesterovSolve] Iter: 1180 overflow: 0.180627 HPWL: 134923493
+[NesterovSolve] Iter: 1190 overflow: 0.205724 HPWL: 135917221
+[NesterovSolve] Iter: 1200 overflow: 0.182616 HPWL: 136783140
+[NesterovSolve] Iter: 1210 overflow: 0.207223 HPWL: 137661350
+[NesterovSolve] Iter: 1220 overflow: 0.179932 HPWL: 137978932
+[NesterovSolve] Iter: 1230 overflow: 0.202385 HPWL: 138184263
+[NesterovSolve] Iter: 1240 overflow: 0.203798 HPWL: 138574231
+[NesterovSolve] Iter: 1250 overflow: 0.184768 HPWL: 139116267
+[NesterovSolve] Iter: 1260 overflow: 0.205776 HPWL: 139640409
+[NesterovSolve] Iter: 1270 overflow: 0.185004 HPWL: 140184607
+[NesterovSolve] Iter: 1280 overflow: 0.180045 HPWL: 140689932
+[NesterovSolve] Iter: 1290 overflow: 0.185259 HPWL: 141457361
+[NesterovSolve] Iter: 1300 overflow: 0.184925 HPWL: 142207403
+[NesterovSolve] Iter: 1310 overflow: 0.205776 HPWL: 142978260
+[NesterovSolve] Iter: 1320 overflow: 0.191332 HPWL: 143820194
+[NesterovSolve] Iter: 1330 overflow: 0.199727 HPWL: 144434119
+[NesterovSolve] Iter: 1340 overflow: 0.193453 HPWL: 144519626
+[NesterovSolve] Iter: 1350 overflow: 0.178593 HPWL: 144601019
+[NesterovSolve] Iter: 1360 overflow: 0.206444 HPWL: 144463862
+[NesterovSolve] Iter: 1370 overflow: 0.193863 HPWL: 144606535
+[NesterovSolve] Iter: 1380 overflow: 0.198693 HPWL: 144520860
+[NesterovSolve] Iter: 1390 overflow: 0.186644 HPWL: 144736141
+[NesterovSolve] Iter: 1400 overflow: 0.193656 HPWL: 145277637
+[NesterovSolve] Iter: 1410 overflow: 0.170126 HPWL: 145618132
+[NesterovSolve] Iter: 1420 overflow: 0.204803 HPWL: 146098659
+[NesterovSolve] Iter: 1430 overflow: 0.206405 HPWL: 146662537
+[NesterovSolve] Iter: 1440 overflow: 0.206757 HPWL: 147116618
+[NesterovSolve] Iter: 1450 overflow: 0.205917 HPWL: 147399476
+[NesterovSolve] Iter: 1460 overflow: 0.186807 HPWL: 147382211
+[NesterovSolve] Iter: 1470 overflow: 0.179113 HPWL: 147422945
+[NesterovSolve] Iter: 1480 overflow: 0.20435 HPWL: 147667106
+[NesterovSolve] Iter: 1490 overflow: 0.205776 HPWL: 148545959
+[NesterovSolve] Iter: 1500 overflow: 0.187928 HPWL: 149344082
+[NesterovSolve] Iter: 1510 overflow: 0.187517 HPWL: 149929077
+[NesterovSolve] Iter: 1520 overflow: 0.204279 HPWL: 150040684
+[NesterovSolve] Iter: 1530 overflow: 0.204163 HPWL: 150542328
+[NesterovSolve] Iter: 1540 overflow: 0.206145 HPWL: 151341921
+[NesterovSolve] Iter: 1550 overflow: 0.206544 HPWL: 151663532
+[NesterovSolve] Iter: 1560 overflow: 0.187538 HPWL: 152127695
+[NesterovSolve] Iter: 1570 overflow: 0.178754 HPWL: 152349751
+[NesterovSolve] Iter: 1580 overflow: 0.195625 HPWL: 152536599
+[NesterovSolve] Iter: 1590 overflow: 0.200352 HPWL: 152779876
+[NesterovSolve] Iter: 1600 overflow: 0.204123 HPWL: 153076828
+[NesterovSolve] Iter: 1610 overflow: 0.193046 HPWL: 153472062
+[NesterovSolve] Iter: 1620 overflow: 0.181604 HPWL: 153453950
+[NesterovSolve] Iter: 1630 overflow: 0.203479 HPWL: 153932290
+[NesterovSolve] Iter: 1640 overflow: 0.206818 HPWL: 154351959
+[NesterovSolve] Iter: 1650 overflow: 0.185574 HPWL: 154294274
+[NesterovSolve] Iter: 1660 overflow: 0.200165 HPWL: 154571220
+[NesterovSolve] Iter: 1670 overflow: 0.195822 HPWL: 154701198
+[NesterovSolve] Iter: 1680 overflow: 0.202787 HPWL: 154372594
+[NesterovSolve] Iter: 1690 overflow: 0.186644 HPWL: 154251822
+[NesterovSolve] Iter: 1700 overflow: 0.206773 HPWL: 154313853
+[NesterovSolve] Iter: 1710 overflow: 0.18528 HPWL: 154442306
+[NesterovSolve] Iter: 1720 overflow: 0.206188 HPWL: 154709221
+[NesterovSolve] Iter: 1730 overflow: 0.206505 HPWL: 154943943
+[NesterovSolve] Iter: 1740 overflow: 0.178317 HPWL: 155280597
+[NesterovSolve] Iter: 1750 overflow: 0.206793 HPWL: 155394480
+[NesterovSolve] Iter: 1760 overflow: 0.206109 HPWL: 155294418
+[NesterovSolve] Iter: 1770 overflow: 0.20678 HPWL: 155334012
+[NesterovSolve] Iter: 1780 overflow: 0.178082 HPWL: 155261285
+[NesterovSolve] Iter: 1790 overflow: 0.193606 HPWL: 155017680
+[NesterovSolve] Iter: 1800 overflow: 0.204441 HPWL: 155215959
+[NesterovSolve] Iter: 1810 overflow: 0.183019 HPWL: 155781456
+[NesterovSolve] Iter: 1820 overflow: 0.207527 HPWL: 156523832
+[NesterovSolve] Iter: 1830 overflow: 0.184764 HPWL: 157398479
+[NesterovSolve] Iter: 1840 overflow: 0.207165 HPWL: 157811625
+[NesterovSolve] Iter: 1850 overflow: 0.194183 HPWL: 158409261
+[NesterovSolve] Iter: 1860 overflow: 0.206107 HPWL: 159196701
+[NesterovSolve] Iter: 1870 overflow: 0.188304 HPWL: 159667327
+[NesterovSolve] Iter: 1880 overflow: 0.189482 HPWL: 159742931
+[NesterovSolve] Iter: 1890 overflow: 0.195047 HPWL: 160021748
+[NesterovSolve] Iter: 1900 overflow: 0.174163 HPWL: 160490278
+[NesterovSolve] Iter: 1910 overflow: 0.198162 HPWL: 160668119
+[NesterovSolve] Iter: 1920 overflow: 0.206424 HPWL: 160760177
+[NesterovSolve] Iter: 1930 overflow: 0.204631 HPWL: 160835264
+[NesterovSolve] Iter: 1940 overflow: 0.208937 HPWL: 160909090
+[NesterovSolve] Iter: 1950 overflow: 0.192961 HPWL: 161161625
+[NesterovSolve] Iter: 1960 overflow: 0.191339 HPWL: 161543923
+[NesterovSolve] Iter: 1970 overflow: 0.434672 HPWL: 48787165
+[NesterovSolve] Iter: 1980 overflow: 0.346998 HPWL: 51577135
+[NesterovSolve] Iter: 1990 overflow: 0.363594 HPWL: 55033137
+[NesterovSolve] Iter: 2000 overflow: 0.461467 HPWL: 60646438
+[NesterovSolve] Iter: 2010 overflow: 0.464723 HPWL: 69215089
+[NesterovSolve] Iter: 2020 overflow: 0.518067 HPWL: 80807302
+[NesterovSolve] Iter: 2030 overflow: 0.515687 HPWL: 97337105
+[NesterovSolve] Iter: 2040 overflow: 0.517266 HPWL: 119097704
+[NesterovSolve] Iter: 2050 overflow: 0.493969 HPWL: 141715325
+[NesterovSolve] Iter: 2060 overflow: 0.537366 HPWL: 145823112
+[NesterovSolve] Iter: 2070 overflow: 0.543312 HPWL: 140414403
+[NesterovSolve] Iter: 2080 overflow: 0.541561 HPWL: 135872115
+[NesterovSolve] Iter: 2090 overflow: 0.539403 HPWL: 133707377
+[NesterovSolve] Iter: 2100 overflow: 0.539942 HPWL: 134912034
+[NesterovSolve] Iter: 2110 overflow: 0.539887 HPWL: 137647079
+[NesterovSolve] Iter: 2120 overflow: 0.539775 HPWL: 140039724
+[NesterovSolve] Iter: 2130 overflow: 0.509504 HPWL: 140990223
+[NesterovSolve] Iter: 2140 overflow: 0.536476 HPWL: 139037321
+[NesterovSolve] Iter: 2150 overflow: 0.533009 HPWL: 135973547
+[NesterovSolve] Iter: 2160 overflow: 0.535296 HPWL: 134238889
+[NesterovSolve] Iter: 2170 overflow: 0.537349 HPWL: 135443640
+[NesterovSolve] Iter: 2180 overflow: 0.511302 HPWL: 137114678
+[NesterovSolve] Iter: 2190 overflow: 0.500401 HPWL: 138350267
+[NesterovSolve] Iter: 2200 overflow: 0.49858 HPWL: 138128597
+[NesterovSolve] Iter: 2210 overflow: 0.5322 HPWL: 136848354
+[NesterovSolve] Iter: 2220 overflow: 0.527713 HPWL: 134142081
+[NesterovSolve] Iter: 2230 overflow: 0.514439 HPWL: 133210453
+[NesterovSolve] Iter: 2240 overflow: 0.525084 HPWL: 134193150
+[NesterovSolve] Iter: 2250 overflow: 0.528006 HPWL: 135167952
+[NesterovSolve] Iter: 2260 overflow: 0.525799 HPWL: 135413336
+[NesterovSolve] Iter: 2270 overflow: 0.525096 HPWL: 134317857
+[NesterovSolve] Iter: 2280 overflow: 0.525017 HPWL: 132817908
+[NesterovSolve] Iter: 2290 overflow: 0.495062 HPWL: 131448763
+[NesterovSolve] Iter: 2300 overflow: 0.525068 HPWL: 130579843
+[NesterovSolve] Iter: 2310 overflow: 0.525068 HPWL: 130256626
+[NesterovSolve] Iter: 2320 overflow: 0.525084 HPWL: 130303333
+[NesterovSolve] Iter: 2330 overflow: 0.525017 HPWL: 130548390
+[NesterovSolve] Iter: 2340 overflow: 0.49509 HPWL: 130651256
+[NesterovSolve] Iter: 2350 overflow: 0.498247 HPWL: 130366954
+[NesterovSolve] Iter: 2360 overflow: 0.525017 HPWL: 129641753
+[NesterovSolve] Iter: 2370 overflow: 0.495448 HPWL: 128575187
+[NesterovSolve] Iter: 2380 overflow: 0.525084 HPWL: 127462557
+[NesterovSolve] Iter: 2390 overflow: 0.461643 HPWL: 126529103
+[NesterovSolve] Iter: 2400 overflow: 0.466052 HPWL: 126104071
+[NesterovSolve] Iter: 2410 overflow: 0.494547 HPWL: 126049365
+[NesterovSolve] Iter: 2420 overflow: 0.506047 HPWL: 126014935
+[NesterovSolve] Iter: 2430 overflow: 0.525017 HPWL: 125620470
+[NesterovSolve] Iter: 2440 overflow: 0.515599 HPWL: 124754363
+[NesterovSolve] Iter: 2450 overflow: 0.496245 HPWL: 123947203
+[NesterovSolve] Iter: 2460 overflow: 0.467015 HPWL: 123575834
+[NesterovSolve] Iter: 2470 overflow: 0.42622 HPWL: 123578030
+[NesterovSolve] Iter: 2480 overflow: 0.394168 HPWL: 123281162
+[NesterovSolve] Iter: 2490 overflow: 0.373554 HPWL: 122613367
+[NesterovSolve] Iter: 2500 overflow: 0.344849 HPWL: 122479354
+[NesterovSolve] Iter: 2510 overflow: 0.316221 HPWL: 122484250
+[NesterovSolve] Iter: 2520 overflow: 0.277967 HPWL: 122171795
+[NesterovSolve] Iter: 2530 overflow: 0.220836 HPWL: 122091221
+[NesterovSolve] Iter: 2540 overflow: 0.173352 HPWL: 121739074
+[INFO GPL-0100] worst slack 4.92e-08
+[INFO GPL-0103] Weighted 25 nets.
+[NesterovSolve] Finished with Overflow: 0.088836
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/7-global.odb...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/7-global.def...
+[INFO]: Setting RC values...
+min_report
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.18    1.54    1.54 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     3    0.08                           io_out[6] (net)
+                  1.18    0.02    1.56 v _070_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.50    0.47    2.03 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.00                           _033_ (net)
+                  0.50    0.00    2.03 ^ _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  0.32    0.29    2.32 v _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     1    0.01                           _010_ (net)
+                  0.32    0.00    2.32 v _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  2.32   data arrival time
+
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                                  0.25 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.03    0.28   library hold time
+                                  0.28   data required time
+-----------------------------------------------------------------------------
+                                  0.28   data required time
+                                 -2.32   data arrival time
+-----------------------------------------------------------------------------
+                                  2.04   slack (MET)
+
+
+Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.20    1.55    1.55 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     3    0.08                           io_out[14] (net)
+                  1.20    0.02    1.57 v _088_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.51    0.49    2.06 ^ _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _043_ (net)
+                  0.51    0.00    2.06 ^ _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  0.32    0.28    2.34 v _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     1    0.01                           _018_ (net)
+                  0.32    0.00    2.34 v _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  2.34   data arrival time
+
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                                  0.25 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.03    0.28   library hold time
+                                  0.28   data required time
+-----------------------------------------------------------------------------
+                                  0.28   data required time
+                                 -2.34   data arrival time
+-----------------------------------------------------------------------------
+                                  2.06   slack (MET)
+
+
+Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.15    1.53    1.53 v _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     2    0.08                           io_out[15] (net)
+                  1.15    0.00    1.54 v _092_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  0.42    0.54    2.07 ^ _092_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     1    0.00                           _046_ (net)
+                  0.42    0.00    2.07 ^ _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  0.34    0.29    2.36 v _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     1    0.01                           _019_ (net)
+                  0.34    0.00    2.36 v _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  2.36   data arrival time
+
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                                  0.25 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.03    0.28   library hold time
+                                  0.28   data required time
+-----------------------------------------------------------------------------
+                                  0.28   data required time
+                                 -2.36   data arrival time
+-----------------------------------------------------------------------------
+                                  2.09   slack (MET)
+
+
+Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.17    1.53    1.53 v _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     2    0.08                           io_out[7] (net)
+                  1.17    0.02    1.56 v _074_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  0.42    0.54    2.09 ^ _074_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     1    0.00                           _036_ (net)
+                  0.42    0.00    2.09 ^ _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  0.35    0.30    2.39 v _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     1    0.01                           _011_ (net)
+                  0.35    0.00    2.39 v _105_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  2.39   data arrival time
+
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                                  0.25 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.02    0.27   library hold time
+                                  0.27   data required time
+-----------------------------------------------------------------------------
+                                  0.27   data required time
+                                 -2.39   data arrival time
+-----------------------------------------------------------------------------
+                                  2.12   slack (MET)
+
+
+Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.29    1.59    1.59 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     3    0.08                           io_out[2] (net)
+                  1.30    0.03    1.62 v _061_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.52    0.49    2.11 ^ _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _028_ (net)
+                  0.52    0.00    2.11 ^ _064_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  0.34    0.30    2.41 v _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     1    0.01                           _006_ (net)
+                  0.34    0.00    2.42 v _100_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  2.42   data arrival time
+
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                                  0.25 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.03    0.28   library hold time
+                                  0.28   data required time
+-----------------------------------------------------------------------------
+                                  0.28   data required time
+                                 -2.42   data arrival time
+-----------------------------------------------------------------------------
+                                  2.14   slack (MET)
+
+
+min_report_end
+max_report
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                         13.00   13.00 ^ input external delay
+                  0.49    0.27   13.27 ^ wb_rst_i (in)
+     2    0.02                           wb_rst_i (net)
+                  0.49    0.00   13.27 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    1.05   14.31 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+    10    0.05                           _021_ (net)
+                  1.29    0.00   14.31 ^ _050_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.65    0.32   14.63 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _022_ (net)
+                  0.65    0.00   14.63 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.98    0.79   15.42 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _001_ (net)
+                  0.98    0.00   15.42 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 15.42   data arrival time
+
+                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (ideal)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                                 64.75 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.44   64.31   library setup time
+                                 64.31   data required time
+-----------------------------------------------------------------------------
+                                 64.31   data required time
+                                -15.42   data arrival time
+-----------------------------------------------------------------------------
+                                 48.89   slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[12] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.93    2.77    2.77 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.10                           io_out[12] (net)
+                  2.93    0.09    2.86 ^ io_out[12] (out)
+                                  2.86   data arrival time
+
+                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (ideal)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.86   data arrival time
+-----------------------------------------------------------------------------
+                                 48.89   slack (MET)
+
+
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.92    2.76    2.76 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.10                           io_out[16] (net)
+                  2.93    0.09    2.85 ^ io_out[16] (out)
+                                  2.85   data arrival time
+
+                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (ideal)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.85   data arrival time
+-----------------------------------------------------------------------------
+                                 48.90   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                         13.00   13.00 ^ input external delay
+                  0.49    0.27   13.27 ^ wb_rst_i (in)
+     2    0.02                           wb_rst_i (net)
+                  0.49    0.00   13.27 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    1.05   14.31 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+    10    0.05                           _021_ (net)
+                  1.29    0.00   14.32 ^ _068_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.64    0.30   14.61 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.00                           _032_ (net)
+                  0.64    0.00   14.61 v _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.98    0.78   15.40 ^ _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _009_ (net)
+                  0.98    0.00   15.40 ^ _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 15.40   data arrival time
+
+                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (ideal)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                                 64.75 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.44   64.31   library setup time
+                                 64.31   data required time
+-----------------------------------------------------------------------------
+                                 64.31   data required time
+                                -15.40   data arrival time
+-----------------------------------------------------------------------------
+                                 48.91   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                         13.00   13.00 ^ input external delay
+                  0.49    0.27   13.27 ^ wb_rst_i (in)
+     2    0.02                           wb_rst_i (net)
+                  0.49    0.00   13.27 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    1.05   14.31 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+    10    0.05                           _021_ (net)
+                  1.29    0.00   14.32 ^ _086_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.63    0.30   14.61 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.00                           _042_ (net)
+                  0.63    0.00   14.61 v _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.97    0.77   15.39 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _017_ (net)
+                  0.97    0.00   15.39 ^ _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 15.39   data arrival time
+
+                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (ideal)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                                 64.75 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.44   64.31   library setup time
+                                 64.31   data required time
+-----------------------------------------------------------------------------
+                                 64.31   data required time
+                                -15.39   data arrival time
+-----------------------------------------------------------------------------
+                                 48.92   slack (MET)
+
+
+max_report_end
+check_report
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                         13.00   13.00 ^ input external delay
+                  0.49    0.27   13.27 ^ wb_rst_i (in)
+     2    0.02                           wb_rst_i (net)
+                  0.49    0.00   13.27 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    1.05   14.31 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+    10    0.05                           _021_ (net)
+                  1.29    0.00   14.31 ^ _050_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.65    0.32   14.63 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _022_ (net)
+                  0.65    0.00   14.63 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.98    0.79   15.42 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _001_ (net)
+                  0.98    0.00   15.42 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 15.42   data arrival time
+
+                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (ideal)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                                 64.75 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.44   64.31   library setup time
+                                 64.31   data required time
+-----------------------------------------------------------------------------
+                                 64.31   data required time
+                                -15.42   data arrival time
+-----------------------------------------------------------------------------
+                                 48.89   slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
+check_report_end
+check_slew
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
+check_slew_end
+tns_report
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
+tns_report_end
+wns_report
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
+wns_report_end
+worst_slack
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 48.89
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 2.04
+worst_slack_end
+clock_skew
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency      CRPR       Skew
+_094_/CLK ^
+   0.23
+_094_/CLK ^
+   0.21      0.00       0.02
+
+clock_skew_end
+power_report
+
+===========================================================================
+ report_power
+============================================================================
+Group                  Internal  Switching    Leakage      Total
+                          Power      Power      Power      Power (Watts)
+----------------------------------------------------------------
+Sequential             6.99e-05   1.61e-05   1.89e-09   8.60e-05  89.8%
+Combinational          4.62e-06   4.80e-06   3.22e-07   9.74e-06  10.2%
+Macro                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+----------------------------------------------------------------
+Total                  7.45e-05   2.09e-05   3.24e-07   9.58e-05 100.0%
+                          77.8%      21.8%       0.3%
+power_report_end
+area_report
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 66550 u^2 3% utilization.
+area_report_end
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/7-global.odb...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/7-global.def...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/placement/8-resizer.log b/openlane/cntr_example/runs/cntr_example/logs/placement/8-resizer.log
new file mode 100644
index 0000000..0558bcb
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/placement/8-resizer.log
@@ -0,0 +1,537 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO]: Setting RC values...
+[INFO RSZ-0027] Inserted 1 input buffers.
+[INFO RSZ-0028] Inserted 20 output buffers.
+[INFO RSZ-0058] Using max wire length 22815um.
+[INFO RSZ-0039] Resized 37 instances.
+[INFO RSZ-0042] Inserted 18 tie gf180mcu_fd_sc_mcu7t5v0__tiel instances.
+Placement Analysis
+---------------------------------
+total displacement        241.6 u
+average displacement        0.0 u
+max displacement            9.5 u
+original HPWL           60426.6 u
+legalized HPWL          60417.9 u
+delta HPWL                    0 %
+
+[INFO DPL-0020] Mirrored 62 instances
+[INFO DPL-0021] HPWL before           60417.9 u
+[INFO DPL-0022] HPWL after            60307.8 u
+[INFO DPL-0023] HPWL delta               -0.2 %
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.odb...
+Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.def...
+Writing timing constraints to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.sdc...
+min_report
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.40    1.14    1.14 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.05                           net16 (net)
+                  0.40    0.01    1.15 v _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  0.60    0.44    1.59 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     1    0.01                           _008_ (net)
+                  0.60    0.00    1.59 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  1.59   data arrival time
+
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                                  0.25 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.03    0.28   library hold time
+                                  0.28   data required time
+-----------------------------------------------------------------------------
+                                  0.28   data required time
+                                 -1.59   data arrival time
+-----------------------------------------------------------------------------
+                                  1.32   slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.55    1.31    1.31 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     5    0.04                           net21 (net)
+                  0.56    0.02    1.32 ^ _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.38    0.30    1.62 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _013_ (net)
+                  0.38    0.00    1.62 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  1.62   data arrival time
+
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                                  0.25 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.03    0.28   library hold time
+                                  0.28   data required time
+-----------------------------------------------------------------------------
+                                  0.28   data required time
+                                 -1.62   data arrival time
+-----------------------------------------------------------------------------
+                                  1.34   slack (MET)
+
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.57    1.31    1.31 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     5    0.04                           net6 (net)
+                  0.57    0.01    1.33 ^ _087_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.39    0.30    1.63 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _017_ (net)
+                  0.39    0.00    1.63 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  1.63   data arrival time
+
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                                  0.25 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.03    0.28   library hold time
+                                  0.28   data required time
+-----------------------------------------------------------------------------
+                                  0.28   data required time
+                                 -1.63   data arrival time
+-----------------------------------------------------------------------------
+                                  1.36   slack (MET)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.57    1.32    1.32 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     5    0.04                           net10 (net)
+                  0.58    0.01    1.33 ^ _051_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.40    0.31    1.64 v _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _001_ (net)
+                  0.40    0.00    1.64 v _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  1.64   data arrival time
+
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                                  0.25 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.02    0.27   library hold time
+                                  0.27   data required time
+-----------------------------------------------------------------------------
+                                  0.27   data required time
+                                 -1.64   data arrival time
+-----------------------------------------------------------------------------
+                                  1.37   slack (MET)
+
+
+Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.63    1.36    1.36 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     5    0.05                           net13 (net)
+                  0.63    0.01    1.36 ^ _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.38    0.29    1.66 v _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _005_ (net)
+                  0.38    0.00    1.66 v _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  1.66   data arrival time
+
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                                  0.25 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.03    0.28   library hold time
+                                  0.28   data required time
+-----------------------------------------------------------------------------
+                                  0.28   data required time
+                                 -1.66   data arrival time
+-----------------------------------------------------------------------------
+                                  1.38   slack (MET)
+
+
+min_report_end
+max_report
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                         13.00   13.00 ^ input external delay
+                  0.14    0.04   13.04 ^ wb_rst_i (in)
+     1    0.00                           wb_rst_i (net)
+                  0.14    0.00   13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  0.70    0.62   13.67 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     2    0.03                           net1 (net)
+                  0.70    0.01   13.67 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  0.66    0.68   14.35 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    10    0.05                           _021_ (net)
+                  0.66    0.00   14.35 ^ _050_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.31    0.30   14.65 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _022_ (net)
+                  0.31    0.00   14.65 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.90    0.72   15.37 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _001_ (net)
+                  0.90    0.00   15.37 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 15.37   data arrival time
+
+                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (ideal)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                                 64.75 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.47   64.28   library setup time
+                                 64.28   data required time
+-----------------------------------------------------------------------------
+                                 64.28   data required time
+                                -15.37   data arrival time
+-----------------------------------------------------------------------------
+                                 48.91   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                         13.00   13.00 ^ input external delay
+                  0.14    0.04   13.04 ^ wb_rst_i (in)
+     1    0.00                           wb_rst_i (net)
+                  0.14    0.00   13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  0.70    0.62   13.67 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     2    0.03                           net1 (net)
+                  0.70    0.01   13.67 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  0.66    0.68   14.35 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    10    0.05                           _021_ (net)
+                  0.66    0.00   14.35 ^ _068_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.30    0.28   14.63 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.00                           _032_ (net)
+                  0.30    0.00   14.63 v _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.89    0.71   15.34 ^ _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _009_ (net)
+                  0.89    0.00   15.35 ^ _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 15.35   data arrival time
+
+                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (ideal)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                                 64.75 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.47   64.28   library setup time
+                                 64.28   data required time
+-----------------------------------------------------------------------------
+                                 64.28   data required time
+                                -15.35   data arrival time
+-----------------------------------------------------------------------------
+                                 48.93   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                         13.00   13.00 ^ input external delay
+                  0.14    0.04   13.04 ^ wb_rst_i (in)
+     1    0.00                           wb_rst_i (net)
+                  0.14    0.00   13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  0.70    0.62   13.67 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     2    0.03                           net1 (net)
+                  0.70    0.01   13.67 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  0.66    0.68   14.35 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    10    0.05                           _021_ (net)
+                  0.66    0.00   14.35 ^ _086_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.29    0.28   14.63 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.00                           _042_ (net)
+                  0.29    0.00   14.63 v _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.88    0.71   15.34 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _017_ (net)
+                  0.88    0.00   15.34 ^ _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 15.34   data arrival time
+
+                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (ideal)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                                 64.75 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.47   64.28   library setup time
+                                 64.28   data required time
+-----------------------------------------------------------------------------
+                                 64.28   data required time
+                                -15.34   data arrival time
+-----------------------------------------------------------------------------
+                                 48.94   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                         13.00   13.00 ^ input external delay
+                  0.14    0.04   13.04 ^ wb_rst_i (in)
+     1    0.00                           wb_rst_i (net)
+                  0.14    0.00   13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  0.70    0.62   13.67 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     2    0.03                           net1 (net)
+                  0.70    0.01   13.67 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  0.66    0.68   14.35 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    10    0.05                           _021_ (net)
+                  0.66    0.00   14.35 ^ _077_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.28    0.28   14.63 v _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.00                           _037_ (net)
+                  0.28    0.00   14.63 v _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.87    0.70   15.33 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _013_ (net)
+                  0.87    0.00   15.33 ^ _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 15.33   data arrival time
+
+                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (ideal)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                                 64.75 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.47   64.28   library setup time
+                                 64.28   data required time
+-----------------------------------------------------------------------------
+                                 64.28   data required time
+                                -15.33   data arrival time
+-----------------------------------------------------------------------------
+                                 48.95   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                         13.00   13.00 ^ input external delay
+                  0.14    0.04   13.04 ^ wb_rst_i (in)
+     1    0.00                           wb_rst_i (net)
+                  0.14    0.00   13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  0.70    0.62   13.67 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     2    0.03                           net1 (net)
+                  0.70    0.01   13.67 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  0.66    0.68   14.35 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    10    0.05                           _021_ (net)
+                  0.66    0.00   14.35 ^ _059_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.30    0.28   14.63 v _059_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.00                           _027_ (net)
+                  0.30    0.00   14.63 v _060_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.84    0.68   15.31 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _005_ (net)
+                  0.84    0.00   15.32 ^ _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 15.32   data arrival time
+
+                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (ideal)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                                 64.75 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.47   64.28   library setup time
+                                 64.28   data required time
+-----------------------------------------------------------------------------
+                                 64.28   data required time
+                                -15.32   data arrival time
+-----------------------------------------------------------------------------
+                                 48.96   slack (MET)
+
+
+max_report_end
+check_report
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                         13.00   13.00 ^ input external delay
+                  0.14    0.04   13.04 ^ wb_rst_i (in)
+     1    0.00                           wb_rst_i (net)
+                  0.14    0.00   13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  0.70    0.62   13.67 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     2    0.03                           net1 (net)
+                  0.70    0.01   13.67 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  0.66    0.68   14.35 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    10    0.05                           _021_ (net)
+                  0.66    0.00   14.35 ^ _050_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.31    0.30   14.65 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _022_ (net)
+                  0.31    0.00   14.65 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.90    0.72   15.37 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _001_ (net)
+                  0.90    0.00   15.37 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 15.37   data arrival time
+
+                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (ideal)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                                 64.75 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.47   64.28   library setup time
+                                 64.28   data required time
+-----------------------------------------------------------------------------
+                                 64.28   data required time
+                                -15.37   data arrival time
+-----------------------------------------------------------------------------
+                                 48.91   slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
+check_report_end
+check_slew
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
+check_slew_end
+tns_report
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
+tns_report_end
+wns_report
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
+wns_report_end
+worst_slack
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 48.91
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 1.32
+worst_slack_end
+clock_skew
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency      CRPR       Skew
+_094_/CLK ^
+   0.23
+_094_/CLK ^
+   0.21      0.00       0.02
+
+clock_skew_end
+power_report
+
+===========================================================================
+ report_power
+============================================================================
+Group                  Internal  Switching    Leakage      Total
+                          Power      Power      Power      Power (Watts)
+----------------------------------------------------------------
+Sequential             7.08e-05   7.86e-06   1.98e-09   7.86e-05  73.8%
+Combinational          9.21e-06   1.84e-05   3.24e-07   2.79e-05  26.2%
+Macro                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+----------------------------------------------------------------
+Total                  8.00e-05   2.62e-05   3.26e-07   1.07e-04 100.0%
+                          75.1%      24.6%       0.3%
+power_report_end
+area_report
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 67257 u^2 3% utilization.
+area_report_end
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.odb...
+Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.def...
+Writing timing constraints to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.sdc...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/placement/9-detailed.log b/openlane/cntr_example/runs/cntr_example/logs/placement/9-detailed.log
new file mode 100644
index 0000000..b5fd200
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/placement/9-detailed.log
@@ -0,0 +1,21 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Placement Analysis
+---------------------------------
+total displacement          0.0 u
+average displacement        0.0 u
+max displacement            0.0 u
+original HPWL           60307.8 u
+legalized HPWL          60417.9 u
+delta HPWL                    0 %
+
+[INFO DPL-0020] Mirrored 62 instances
+[INFO DPL-0021] HPWL before           60417.9 u
+[INFO DPL-0022] HPWL after            60307.8 u
+[INFO DPL-0023] HPWL delta               -0.2 %
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/placement/cntr_example.odb...
+Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/placement/cntr_example.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/placement/cntr_example.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/placement/cntr_example.def...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/routing/12-resizer.log b/openlane/cntr_example/runs/cntr_example/logs/routing/12-resizer.log
new file mode 100644
index 0000000..c1c3f7c
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/routing/12-resizer.log
@@ -0,0 +1,652 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO]: Setting signal min routing layer to: Metal2 and clock min routing layer to Metal2. 
+[INFO]: Setting signal max routing layer to: Metal4 and clock max routing layer to Metal4. 
+-congestion_iterations 50 -verbose
+[INFO GRT-0020] Min routing layer: Metal2
+[INFO GRT-0021] Max routing layer: Metal4
+[INFO GRT-0022] Global adjustment: 30%
+[INFO GRT-0023] Grid origin: (0, 0)
+[INFO GRT-0043] No OR_DEFAULT vias defined.
+[INFO GRT-0088] Layer Metal1  Track-Pitch = 0.5600  line-2-Via Pitch: 0.5450
+[INFO GRT-0088] Layer Metal2  Track-Pitch = 0.5600  line-2-Via Pitch: 0.5800
+[INFO GRT-0088] Layer Metal3  Track-Pitch = 0.5600  line-2-Via Pitch: 0.5800
+[INFO GRT-0088] Layer Metal4  Track-Pitch = 0.5600  line-2-Via Pitch: 0.5800
+[INFO GRT-0019] Found 4 clock nets.
+[WARNING GRT-0036] Pin io_out[19] is outside die area.
+[WARNING GRT-0036] Pin io_out[27] is outside die area.
+[INFO GRT-0001] Minimum degree: 2
+[INFO GRT-0002] Maximum degree: 12
+[INFO GRT-0003] Macros: 0
+[INFO GRT-0004] Blockages: 0
+
+[INFO GRT-0053] Routing resources analysis:
+          Routing      Original      Derated      Resource
+Layer     Direction    Resources     Resources    Reduction (%)
+---------------------------------------------------------------
+Metal1     Horizontal          0             0          0.00%
+Metal2     Vertical       443576        286032          35.52%
+Metal3     Horizontal     443576        286032          35.52%
+Metal4     Vertical       443576        283057          36.19%
+---------------------------------------------------------------
+
+[INFO GRT-0197] Via related to pin nodes: 454
+[INFO GRT-0198] Via related Steiner nodes: 24
+[INFO GRT-0199] Via filling finished.
+[INFO GRT-0111] Final number of vias: 613
+[INFO GRT-0112] Final usage 3D: 9553
+
+[INFO GRT-0096] Final congestion report:
+Layer         Resource        Demand        Usage (%)    Max H / Max V / Total Overflow
+---------------------------------------------------------------------------------------
+Metal1               0             0            0.00%             0 /  0 /  0
+Metal2          286032          3522            1.23%             0 /  0 /  0
+Metal3          286032          4192            1.47%             0 /  0 /  0
+Metal4          283057             0            0.00%             0 /  0 /  0
+---------------------------------------------------------------------------------------
+Total           855121          7714            0.90%             0 /  0 /  0
+
+[INFO GRT-0018] Total wirelength: 67779 um
+[INFO GRT-0014] Routed nets: 111
+[INFO]: Setting RC values...
+[INFO RSZ-0033] No hold violations found.
+Placement Analysis
+---------------------------------
+total displacement          0.0 u
+average displacement        0.0 u
+max displacement            0.0 u
+original HPWL           60457.6 u
+legalized HPWL          60593.7 u
+delta HPWL                    0 %
+
+[INFO DPL-0020] Mirrored 63 instances
+[INFO DPL-0021] HPWL before           60593.7 u
+[INFO DPL-0022] HPWL after            60457.6 u
+[INFO DPL-0023] HPWL delta               -0.2 %
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.odb...
+Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.def...
+Writing timing constraints to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.sdc...
+min_report
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.30    0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.70 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.40    1.14    1.84 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.05                           net16 (net)
+                  0.40    0.01    1.85 v _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  0.60    0.44    2.29 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     1    0.01                           _008_ (net)
+                  0.60    0.00    2.29 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.29   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.09    0.09 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.77 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.02   clock uncertainty
+                         -0.07    0.95   clock reconvergence pessimism
+                          0.02    0.97   library hold time
+                                  0.97   data required time
+-----------------------------------------------------------------------------
+                                  0.97   data required time
+                                 -2.29   data arrival time
+-----------------------------------------------------------------------------
+                                  1.32   slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.30    0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.70 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.55    1.30    2.00 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     5    0.04                           net21 (net)
+                  0.55    0.02    2.02 ^ _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.39    0.30    2.31 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _013_ (net)
+                  0.39    0.00    2.32 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.32   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.09    0.09 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.77 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.02   clock uncertainty
+                         -0.07    0.95   clock reconvergence pessimism
+                          0.02    0.97   library hold time
+                                  0.97   data required time
+-----------------------------------------------------------------------------
+                                  0.97   data required time
+                                 -2.32   data arrival time
+-----------------------------------------------------------------------------
+                                  1.34   slack (MET)
+
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.31    0.71 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.71 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.57    1.31    2.02 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     5    0.04                           net6 (net)
+                  0.57    0.01    2.03 ^ _087_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.39    0.30    2.34 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _017_ (net)
+                  0.39    0.00    2.34 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.34   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.09    0.09 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.34    0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.78 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.03   clock uncertainty
+                         -0.07    0.96   clock reconvergence pessimism
+                          0.02    0.98   library hold time
+                                  0.98   data required time
+-----------------------------------------------------------------------------
+                                  0.98   data required time
+                                 -2.34   data arrival time
+-----------------------------------------------------------------------------
+                                  1.36   slack (MET)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.30    0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.70 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.58    1.31    2.01 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     5    0.05                           net10 (net)
+                  0.58    0.01    2.03 ^ _051_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.40    0.31    2.34 v _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _001_ (net)
+                  0.40    0.00    2.34 v _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.34   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.09    0.09 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.77 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.02   clock uncertainty
+                         -0.07    0.95   clock reconvergence pessimism
+                          0.02    0.97   library hold time
+                                  0.97   data required time
+-----------------------------------------------------------------------------
+                                  0.97   data required time
+                                 -2.34   data arrival time
+-----------------------------------------------------------------------------
+                                  1.37   slack (MET)
+
+
+Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.08    0.08 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.31    0.71 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.71 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  0.38    1.06    1.77 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     3    0.03                           net18 (net)
+                  0.38    0.01    1.77 v _070_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.37    0.33    2.10 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.00                           _033_ (net)
+                  0.37    0.00    2.10 ^ _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  0.31    0.26    2.37 v _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     1    0.01                           _010_ (net)
+                  0.31    0.00    2.37 v _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  2.37   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.09    0.09 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.34    0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.78 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    1.03   clock uncertainty
+                         -0.07    0.96   clock reconvergence pessimism
+                          0.03    0.99   library hold time
+                                  0.99   data required time
+-----------------------------------------------------------------------------
+                                  0.99   data required time
+                                 -2.37   data arrival time
+-----------------------------------------------------------------------------
+                                  1.38   slack (MET)
+
+
+min_report_end
+max_report
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.09    0.09 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.34    0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.78 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.71    1.54    2.32 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.06                           net9 (net)
+                  0.72    0.03    2.35 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.72    3.07 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[16] (net)
+                  0.48    0.00    3.07 ^ io_out[16] (out)
+                                  3.07   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.07   data arrival time
+-----------------------------------------------------------------------------
+                                 48.68   slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[12] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.09    0.09 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.77 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.72    1.54    2.32 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.06                           net5 (net)
+                  0.72    0.03    2.34 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.72    3.06 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[12] (net)
+                  0.48    0.00    3.06 ^ io_out[12] (out)
+                                  3.06   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.06   data arrival time
+-----------------------------------------------------------------------------
+                                 48.69   slack (MET)
+
+
+Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[3] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.09    0.09 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.77 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  0.83    1.51    2.29 ^ _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     2    0.03                           net15 (net)
+                  0.83    0.01    2.30 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.73    3.03 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[3] (net)
+                  0.48    0.00    3.03 ^ io_out[3] (out)
+                                  3.03   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.03   data arrival time
+-----------------------------------------------------------------------------
+                                 48.72   slack (MET)
+
+
+Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[8] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.09    0.09 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.34    0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.78 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.66    1.51    2.29 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.05                           net20 (net)
+                  0.67    0.02    2.31 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.71    3.02 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[8] (net)
+                  0.48    0.00    3.02 ^ io_out[8] (out)
+                                  3.02   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.02   data arrival time
+-----------------------------------------------------------------------------
+                                 48.73   slack (MET)
+
+
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[4] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.09    0.09 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.13    0.00    0.77 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.65    1.50    2.27 ^ _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.05                           net16 (net)
+                  0.65    0.02    2.29 ^ output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.71    3.00 ^ output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[4] (net)
+                  0.48    0.00    3.00 ^ io_out[4] (out)
+                                  3.00   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.00   data arrival time
+-----------------------------------------------------------------------------
+                                 48.75   slack (MET)
+
+
+max_report_end
+check_report
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.18    0.09    0.09 ^ wb_clk_i (in)
+     1    0.02                           wb_clk_i (net)
+                  0.18    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.14    0.34    0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.14    0.00    0.78 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.71    1.54    2.32 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.06                           net9 (net)
+                  0.72    0.03    2.35 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.72    3.07 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[16] (net)
+                  0.48    0.00    3.07 ^ io_out[16] (out)
+                                  3.07   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.07   data arrival time
+-----------------------------------------------------------------------------
+                                 48.68   slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
+check_report_end
+check_slew
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
+check_slew_end
+tns_report
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
+tns_report_end
+wns_report
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
+wns_report_end
+worst_slack
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 48.68
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 1.32
+worst_slack_end
+clock_skew
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency      CRPR       Skew
+_106_/CLK ^
+   0.78
+_108_/CLK ^
+   0.70     -0.04       0.04
+
+clock_skew_end
+power_report
+
+===========================================================================
+ report_power
+============================================================================
+Group                  Internal  Switching    Leakage      Total
+                          Power      Power      Power      Power (Watts)
+----------------------------------------------------------------
+Sequential             7.07e-05   7.81e-06   1.98e-09   7.86e-05  42.5%
+Combinational          6.84e-05   3.74e-05   3.25e-07   1.06e-04  57.5%
+Macro                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+----------------------------------------------------------------
+Total                  1.39e-04   4.52e-05   3.27e-07   1.85e-04 100.0%
+                          75.4%      24.5%       0.2%
+power_report_end
+area_report
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 67586 u^2 3% utilization.
+area_report_end
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.odb...
+Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.def...
+Writing timing constraints to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.sdc...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/routing/13-diodes.log b/openlane/cntr_example/runs/cntr_example/logs/routing/13-diodes.log
new file mode 100644
index 0000000..c6f772d
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/routing/13-diodes.log
@@ -0,0 +1,5 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Design name: cntr_example
+Inserted 110 diodes.
diff --git a/openlane/cntr_example/runs/cntr_example/logs/routing/14-diode_legalization.log b/openlane/cntr_example/runs/cntr_example/logs/routing/14-diode_legalization.log
new file mode 100644
index 0000000..4b0b796
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/routing/14-diode_legalization.log
@@ -0,0 +1,21 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Placement Analysis
+---------------------------------
+total displacement        302.4 u
+average displacement        0.0 u
+max displacement            5.6 u
+original HPWL           60474.8 u
+legalized HPWL          60626.8 u
+delta HPWL                    0 %
+
+[INFO DPL-0020] Mirrored 107 instances
+[INFO DPL-0021] HPWL before           60626.8 u
+[INFO DPL-0022] HPWL after            60491.0 u
+[INFO DPL-0023] HPWL delta               -0.2 %
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/diodes.odb...
+Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/diodes.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/diodes.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/diodes.def...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/routing/15-fill.log b/openlane/cntr_example/runs/cntr_example/logs/routing/15-fill.log
new file mode 100644
index 0000000..f6254b2
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/routing/15-fill.log
@@ -0,0 +1,9 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO DPL-0001] Placed 43438 filler instances.
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/15-fill.odb...
+Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/15-fill.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/15-fill.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/15-fill.def...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/routing/16-global.log b/openlane/cntr_example/runs/cntr_example/logs/routing/16-global.log
new file mode 100644
index 0000000..6db2e65
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/routing/16-global.log
@@ -0,0 +1,634 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO]: Setting signal min routing layer to: Metal2 and clock min routing layer to Metal2. 
+[INFO]: Setting signal max routing layer to: Metal4 and clock max routing layer to Metal4. 
+-congestion_iterations 50 -verbose
+[INFO GRT-0020] Min routing layer: Metal2
+[INFO GRT-0021] Max routing layer: Metal4
+[INFO GRT-0022] Global adjustment: 30%
+[INFO GRT-0023] Grid origin: (0, 0)
+[INFO GRT-0043] No OR_DEFAULT vias defined.
+[INFO GRT-0088] Layer Metal1  Track-Pitch = 0.5600  line-2-Via Pitch: 0.5450
+[INFO GRT-0088] Layer Metal2  Track-Pitch = 0.5600  line-2-Via Pitch: 0.5800
+[INFO GRT-0088] Layer Metal3  Track-Pitch = 0.5600  line-2-Via Pitch: 0.5800
+[INFO GRT-0088] Layer Metal4  Track-Pitch = 0.5600  line-2-Via Pitch: 0.5800
+[INFO GRT-0019] Found 4 clock nets.
+[WARNING GRT-0036] Pin io_out[19] is outside die area.
+[WARNING GRT-0036] Pin io_out[27] is outside die area.
+[INFO GRT-0001] Minimum degree: 2
+[INFO GRT-0002] Maximum degree: 23
+[INFO GRT-0003] Macros: 0
+[INFO GRT-0004] Blockages: 0
+
+[INFO GRT-0053] Routing resources analysis:
+          Routing      Original      Derated      Resource
+Layer     Direction    Resources     Resources    Reduction (%)
+---------------------------------------------------------------
+Metal1     Horizontal          0             0          0.00%
+Metal2     Vertical       443576        286032          35.52%
+Metal3     Horizontal     443576        286032          35.52%
+Metal4     Vertical       443576        283057          36.19%
+---------------------------------------------------------------
+
+[INFO GRT-0197] Via related to pin nodes: 697
+[INFO GRT-0198] Via related Steiner nodes: 25
+[INFO GRT-0199] Via filling finished.
+[INFO GRT-0111] Final number of vias: 849
+[INFO GRT-0112] Final usage 3D: 10288
+
+[INFO GRT-0096] Final congestion report:
+Layer         Resource        Demand        Usage (%)    Max H / Max V / Total Overflow
+---------------------------------------------------------------------------------------
+Metal1               0             0            0.00%             0 /  0 /  0
+Metal2          286032          3461            1.21%             0 /  0 /  0
+Metal3          286032          4213            1.47%             0 /  0 /  0
+Metal4          283057            67            0.02%             0 /  0 /  0
+---------------------------------------------------------------------------------------
+Total           855121          7741            0.91%             0 /  0 /  0
+
+[INFO GRT-0018] Total wirelength: 69106 um
+[INFO GRT-0014] Routed nets: 111
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/16-global.odb...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/16-global.def...
+Writing routing guides to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/16-global.guide...
+[INFO]: Setting RC values...
+min_report
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.19    0.08    0.08 ^ wb_clk_i (in)
+     2    0.02                           wb_clk_i (net)
+                  0.19    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.31    0.72 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.04                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.15    0.00    0.72 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.43    1.17    1.89 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.06                           net16 (net)
+                  0.43    0.01    1.90 v _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  0.65    0.48    2.38 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.01                           _008_ (net)
+                  0.65    0.00    2.38 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.38   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.19    0.09    0.09 ^ wb_clk_i (in)
+     2    0.02                           wb_clk_i (net)
+                  0.19    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.34    0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.04                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.15    0.00    0.79 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.04   clock uncertainty
+                         -0.08    0.97   clock reconvergence pessimism
+                          0.03    0.99   library hold time
+                                  0.99   data required time
+-----------------------------------------------------------------------------
+                                  0.99   data required time
+                                 -2.38   data arrival time
+-----------------------------------------------------------------------------
+                                  1.39   slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.19    0.08    0.08 ^ wb_clk_i (in)
+     2    0.02                           wb_clk_i (net)
+                  0.19    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.31    0.72 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.04                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.15    0.00    0.72 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.62    1.34    2.06 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.05                           net21 (net)
+                  0.62    0.02    2.07 ^ _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.42    0.32    2.39 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.01                           _013_ (net)
+                  0.42    0.00    2.40 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.40   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.19    0.09    0.09 ^ wb_clk_i (in)
+     2    0.02                           wb_clk_i (net)
+                  0.19    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.34    0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.04                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.15    0.00    0.79 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.04   clock uncertainty
+                         -0.08    0.97   clock reconvergence pessimism
+                          0.02    0.99   library hold time
+                                  0.99   data required time
+-----------------------------------------------------------------------------
+                                  0.99   data required time
+                                 -2.40   data arrival time
+-----------------------------------------------------------------------------
+                                  1.41   slack (MET)
+
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.19    0.08    0.08 ^ wb_clk_i (in)
+     2    0.02                           wb_clk_i (net)
+                  0.19    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.16    0.32    0.72 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.05                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.16    0.00    0.72 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.63    1.35    2.08 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.05                           net6 (net)
+                  0.63    0.01    2.09 ^ _087_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.42    0.33    2.42 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.02                           _017_ (net)
+                  0.42    0.00    2.42 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.42   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.19    0.09    0.09 ^ wb_clk_i (in)
+     2    0.02                           wb_clk_i (net)
+                  0.19    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.45 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.16    0.35    0.80 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.05                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.16    0.00    0.80 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.05   clock uncertainty
+                         -0.08    0.98   clock reconvergence pessimism
+                          0.02    0.99   library hold time
+                                  0.99   data required time
+-----------------------------------------------------------------------------
+                                  0.99   data required time
+                                 -2.42   data arrival time
+-----------------------------------------------------------------------------
+                                  1.43   slack (MET)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.19    0.08    0.08 ^ wb_clk_i (in)
+     2    0.02                           wb_clk_i (net)
+                  0.19    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.31    0.72 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.04                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.15    0.00    0.72 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.64    1.35    2.07 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.05                           net10 (net)
+                  0.64    0.01    2.09 ^ _051_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.43    0.33    2.42 v _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.02                           _001_ (net)
+                  0.43    0.00    2.42 v _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.42   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.19    0.09    0.09 ^ wb_clk_i (in)
+     2    0.02                           wb_clk_i (net)
+                  0.19    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.34    0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.04                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.15    0.00    0.79 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.04   clock uncertainty
+                         -0.08    0.97   clock reconvergence pessimism
+                          0.01    0.98   library hold time
+                                  0.98   data required time
+-----------------------------------------------------------------------------
+                                  0.98   data required time
+                                 -2.42   data arrival time
+-----------------------------------------------------------------------------
+                                  1.44   slack (MET)
+
+
+Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.19    0.08    0.08 ^ wb_clk_i (in)
+     2    0.02                           wb_clk_i (net)
+                  0.19    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.32    0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.31    0.72 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.04                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.15    0.00    0.72 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  0.39    1.07    1.79 v _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.03                           net8 (net)
+                  0.39    0.00    1.79 v _092_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  0.42    0.34    2.13 ^ _092_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     1    0.00                           _046_ (net)
+                  0.42    0.00    2.13 ^ _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  0.35    0.30    2.43 v _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.01                           _019_ (net)
+                  0.35    0.00    2.43 v _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  2.43   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.19    0.09    0.09 ^ wb_clk_i (in)
+     2    0.02                           wb_clk_i (net)
+                  0.19    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.34    0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.04                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.15    0.00    0.79 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    1.04   clock uncertainty
+                         -0.08    0.97   clock reconvergence pessimism
+                          0.02    0.99   library hold time
+                                  0.99   data required time
+-----------------------------------------------------------------------------
+                                  0.99   data required time
+                                 -2.43   data arrival time
+-----------------------------------------------------------------------------
+                                  1.44   slack (MET)
+
+
+min_report_end
+max_report
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.19    0.09    0.09 ^ wb_clk_i (in)
+     2    0.02                           wb_clk_i (net)
+                  0.19    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.45 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.16    0.35    0.80 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.05                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.16    0.00    0.80 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.79    1.59    2.39 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.06                           net9 (net)
+                  0.79    0.03    2.42 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.73    3.15 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[16] (net)
+                  0.48    0.00    3.15 ^ io_out[16] (out)
+                                  3.15   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.15   data arrival time
+-----------------------------------------------------------------------------
+                                 48.60   slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[12] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.19    0.09    0.09 ^ wb_clk_i (in)
+     2    0.02                           wb_clk_i (net)
+                  0.19    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.34    0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.04                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.15    0.00    0.79 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.80    1.59    2.39 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.07                           net5 (net)
+                  0.80    0.03    2.41 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.73    3.14 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[12] (net)
+                  0.48    0.00    3.14 ^ io_out[12] (out)
+                                  3.14   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.14   data arrival time
+-----------------------------------------------------------------------------
+                                 48.61   slack (MET)
+
+
+Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[8] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.19    0.09    0.09 ^ wb_clk_i (in)
+     2    0.02                           wb_clk_i (net)
+                  0.19    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.45 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.16    0.35    0.80 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.05                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.16    0.00    0.80 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.74    1.56    2.36 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.06                           net20 (net)
+                  0.74    0.03    2.39 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.72    3.11 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[8] (net)
+                  0.48    0.00    3.11 ^ io_out[8] (out)
+                                  3.11   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.11   data arrival time
+-----------------------------------------------------------------------------
+                                 48.64   slack (MET)
+
+
+Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[3] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.19    0.09    0.09 ^ wb_clk_i (in)
+     2    0.02                           wb_clk_i (net)
+                  0.19    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.34    0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.04                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.15    0.00    0.79 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  0.88    1.55    2.34 ^ _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.04                           net15 (net)
+                  0.88    0.01    2.35 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.74    3.09 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[3] (net)
+                  0.48    0.00    3.10 ^ io_out[3] (out)
+                                  3.10   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.10   data arrival time
+-----------------------------------------------------------------------------
+                                 48.65   slack (MET)
+
+
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[4] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.19    0.09    0.09 ^ wb_clk_i (in)
+     2    0.02                           wb_clk_i (net)
+                  0.19    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.34    0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.04                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.15    0.00    0.79 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.73    1.55    2.34 ^ _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.06                           net16 (net)
+                  0.73    0.02    2.37 ^ output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.72    3.08 ^ output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[4] (net)
+                  0.48    0.00    3.09 ^ io_out[4] (out)
+                                  3.09   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.09   data arrival time
+-----------------------------------------------------------------------------
+                                 48.66   slack (MET)
+
+
+max_report_end
+check_report
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.19    0.09    0.09 ^ wb_clk_i (in)
+     2    0.02                           wb_clk_i (net)
+                  0.19    0.00    0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.36    0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.45 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.16    0.35    0.80 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.05                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.16    0.00    0.80 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.79    1.59    2.39 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.06                           net9 (net)
+                  0.79    0.03    2.42 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.73    3.15 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[16] (net)
+                  0.48    0.00    3.15 ^ io_out[16] (out)
+                                  3.15   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.15   data arrival time
+-----------------------------------------------------------------------------
+                                 48.60   slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
+check_report_end
+check_slew
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
+check_slew_end
+tns_report
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
+tns_report_end
+wns_report
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
+wns_report_end
+worst_slack
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 48.60
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 1.39
+worst_slack_end
+clock_skew
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency      CRPR       Skew
+_094_/CLK ^
+   0.80
+_097_/CLK ^
+   0.72     -0.04       0.04
+
+clock_skew_end
+power_report
+
+===========================================================================
+ report_power
+============================================================================
+Group                  Internal  Switching    Leakage      Total
+                          Power      Power      Power      Power (Watts)
+----------------------------------------------------------------
+Sequential             7.08e-05   8.74e-06   1.98e-09   7.95e-05  41.6%
+Combinational          6.84e-05   4.20e-05   1.28e-06   1.12e-04  58.4%
+Macro                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+----------------------------------------------------------------
+Total                  1.39e-04   5.07e-05   1.28e-06   1.91e-04 100.0%
+                          72.8%      26.5%       0.7%
+power_report_end
+area_report
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 68288 u^2 3% utilization.
+area_report_end
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/16-global.odb...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/16-global.def...
+Writing routing guides to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/16-global.guide...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/routing/16-global_write_netlist.log b/openlane/cntr_example/runs/cntr_example/logs/routing/16-global_write_netlist.log
new file mode 100644
index 0000000..534b935
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/routing/16-global_write_netlist.log
@@ -0,0 +1,7 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Setting global connections for newly added cells...
+[WARNING] Did not save OpenROAD database!
+Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/global.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/global.pnl.v...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/routing/18-detailed.log b/openlane/cntr_example/runs/cntr_example/logs/routing/18-detailed.log
new file mode 100644
index 0000000..c992ea8
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/routing/18-detailed.log
@@ -0,0 +1,258 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO ORD-0030] Using 2 thread(s).
+[INFO DRT-0149] Reading tech and libs.
+[WARNING DRT-0140] SpacingRange unsupported.
+[WARNING DRT-0140] SpacingRange unsupported.
+[WARNING DRT-0140] SpacingRange unsupported.
+[WARNING DRT-0140] SpacingRange unsupported.
+[WARNING DRT-0140] SpacingRange unsupported.
+
+Units:                2000
+Number of layers:     11
+Number of macros:     229
+Number of vias:       60
+Number of viarulegen: 18
+
+[INFO DRT-0150] Reading design.
+
+Design:                   cntr_example
+Die area:                 ( 0 0 ) ( 3000000 3000000 )
+Number of track patterns: 10
+Number of DEF vias:       3
+Number of components:     58369
+Number of terminals:      42
+Number of snets:          2
+Number of nets:           111
+
+[INFO DRT-0167] List of default vias:
+  Layer Via1
+    default via: Via1_HV
+  Layer Via2
+    default via: Via2_VH
+  Layer Via3
+    default via: Via3_HV
+  Layer Via4
+    default via: Via4_1_VH
+[INFO DRT-0162] Library cell analysis.
+[INFO DRT-0163] Instance analysis.
+  Complete 10000 instances.
+  Complete 20000 instances.
+  Complete 30000 instances.
+  Complete 40000 instances.
+  Complete 50000 instances.
+[INFO DRT-0164] Number of unique instances = 60.
+[INFO DRT-0168] Init region query.
+[INFO DRT-0018]   Complete 10000 insts.
+[INFO DRT-0018]   Complete 20000 insts.
+[INFO DRT-0018]   Complete 30000 insts.
+[INFO DRT-0018]   Complete 40000 insts.
+[INFO DRT-0018]   Complete 50000 insts.
+[INFO DRT-0024]   Complete Poly2.
+[INFO DRT-0024]   Complete CON.
+[INFO DRT-0024]   Complete Metal1.
+[INFO DRT-0024]   Complete Via1.
+[INFO DRT-0024]   Complete Metal2.
+[INFO DRT-0024]   Complete Via2.
+[INFO DRT-0024]   Complete Metal3.
+[INFO DRT-0024]   Complete Via3.
+[INFO DRT-0024]   Complete Metal4.
+[INFO DRT-0024]   Complete Via4.
+[INFO DRT-0024]   Complete Metal5.
+[INFO DRT-0033] Poly2 shape region query size = 0.
+[INFO DRT-0033] CON shape region query size = 0.
+[INFO DRT-0033] Metal1 shape region query size = 1571731.
+[INFO DRT-0033] Via1 shape region query size = 11250.
+[INFO DRT-0033] Metal2 shape region query size = 7520.
+[INFO DRT-0033] Via2 shape region query size = 11250.
+[INFO DRT-0033] Metal3 shape region query size = 7520.
+[INFO DRT-0033] Via3 shape region query size = 11250.
+[INFO DRT-0033] Metal4 shape region query size = 3790.
+[INFO DRT-0033] Via4 shape region query size = 0.
+[INFO DRT-0033] Metal5 shape region query size = 0.
+[INFO DRT-0165] Start pin access.
+[INFO DRT-0076]   Complete 100 pins.
+[INFO DRT-0078]   Complete 105 pins.
+[INFO DRT-0081]   Complete 40 unique inst patterns.
+[INFO DRT-0084]   Complete 269 groups.
+#scanned instances     = 58369
+#unique  instances     = 60
+#stdCellGenAp          = 620
+#stdCellValidPlanarAp  = 0
+#stdCellValidViaAp     = 555
+#stdCellPinNoAp        = 0
+#stdCellPinCnt         = 267
+#instTermValidViaApCnt = 0
+#macroGenAp            = 0
+#macroValidPlanarAp    = 0
+#macroValidViaAp       = 0
+#macroNoAp             = 0
+[INFO DRT-0166] Complete pin access.
+[INFO DRT-0267] cpu time = 00:00:02, elapsed time = 00:00:01, memory = 326.21 (MB), peak = 360.11 (MB)
+
+Number of guides:     1196
+
+[INFO DRT-0169] Post process guides.
+[INFO DRT-0176] GCELLGRID X 0 DO 178 STEP 16800 ;
+[INFO DRT-0177] GCELLGRID Y 0 DO 178 STEP 16800 ;
+[INFO DRT-0028]   Complete Poly2.
+[INFO DRT-0028]   Complete CON.
+[INFO DRT-0028]   Complete Metal1.
+[INFO DRT-0028]   Complete Via1.
+[INFO DRT-0028]   Complete Metal2.
+[INFO DRT-0028]   Complete Via2.
+[INFO DRT-0028]   Complete Metal3.
+[INFO DRT-0028]   Complete Via3.
+[INFO DRT-0028]   Complete Metal4.
+[INFO DRT-0028]   Complete Via4.
+[INFO DRT-0028]   Complete Metal5.
+[INFO DRT-0178] Init guide query.
+[INFO DRT-0035]   Complete Poly2 (guide).
+[INFO DRT-0035]   Complete CON (guide).
+[INFO DRT-0035]   Complete Metal1 (guide).
+[INFO DRT-0035]   Complete Via1 (guide).
+[INFO DRT-0035]   Complete Metal2 (guide).
+[INFO DRT-0035]   Complete Via2 (guide).
+[INFO DRT-0035]   Complete Metal3 (guide).
+[INFO DRT-0035]   Complete Via3 (guide).
+[INFO DRT-0035]   Complete Metal4 (guide).
+[INFO DRT-0035]   Complete Via4 (guide).
+[INFO DRT-0035]   Complete Metal5 (guide).
+[INFO DRT-0036] Poly2 guide region query size = 0.
+[INFO DRT-0036] CON guide region query size = 0.
+[INFO DRT-0036] Metal1 guide region query size = 383.
+[INFO DRT-0036] Via1 guide region query size = 0.
+[INFO DRT-0036] Metal2 guide region query size = 399.
+[INFO DRT-0036] Via2 guide region query size = 0.
+[INFO DRT-0036] Metal3 guide region query size = 264.
+[INFO DRT-0036] Via3 guide region query size = 0.
+[INFO DRT-0036] Metal4 guide region query size = 3.
+[INFO DRT-0036] Via4 guide region query size = 0.
+[INFO DRT-0036] Metal5 guide region query size = 0.
+[INFO DRT-0179] Init gr pin query.
+[INFO DRT-0245] skipped writing guide updates to database.
+[INFO DRT-0185] Post process initialize RPin region query.
+[INFO DRT-0181] Start track assignment.
+[INFO DRT-0184] Done with 402 vertical wires in 4 frboxes and 647 horizontal wires in 4 frboxes.
+[INFO DRT-0186] Done with 36 vertical wires in 4 frboxes and 59 horizontal wires in 4 frboxes.
+[INFO DRT-0182] Complete track assignment.
+[INFO DRT-0267] cpu time = 00:00:04, elapsed time = 00:00:02, memory = 415.68 (MB), peak = 632.34 (MB)
+[INFO DRT-0187] Start routing data preparation.
+[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 415.68 (MB), peak = 632.34 (MB)
+[INFO DRT-0194] Start detail routing.
+[INFO DRT-0195] Start 0th optimization iteration.
+    Completing 10% with 0 violations.
+    elapsed time = 00:00:01, memory = 769.63 (MB).
+    Completing 20% with 0 violations.
+    elapsed time = 00:00:02, memory = 1252.08 (MB).
+    Completing 30% with 0 violations.
+    elapsed time = 00:00:03, memory = 1007.61 (MB).
+    Completing 40% with 0 violations.
+    elapsed time = 00:00:04, memory = 1230.75 (MB).
+    Completing 50% with 0 violations.
+    elapsed time = 00:00:06, memory = 1436.59 (MB).
+    Completing 60% with 0 violations.
+    elapsed time = 00:00:07, memory = 1437.64 (MB).
+    Completing 70% with 0 violations.
+    elapsed time = 00:00:08, memory = 1438.79 (MB).
+    Completing 80% with 0 violations.
+    elapsed time = 00:00:09, memory = 1458.67 (MB).
+    Completing 90% with 0 violations.
+    elapsed time = 00:00:10, memory = 1458.69 (MB).
+    Completing 100% with 1 violations.
+    elapsed time = 00:00:12, memory = 1412.00 (MB).
+[INFO DRT-0199]   Number of violations = 35.
+Viol/Layer      Metal2 Metal3
+Metal Spacing        1      0
+Recheck             27      7
+[INFO DRT-0267] cpu time = 00:00:23, elapsed time = 00:00:12, memory = 1348.21 (MB), peak = 1476.13 (MB)
+Total wire length = 64342 um.
+Total wire length on LAYER Metal1 = 9 um.
+Total wire length on LAYER Metal2 = 28450 um.
+Total wire length on LAYER Metal3 = 35318 um.
+Total wire length on LAYER Metal4 = 564 um.
+Total wire length on LAYER Metal5 = 0 um.
+Total number of vias = 965.
+Up-via summary (total 965):.
+
+--------------
+  Poly2      0
+ Metal1    453
+ Metal2    510
+ Metal3      2
+ Metal4      0
+--------------
+           965
+
+
+[INFO DRT-0195] Start 1st optimization iteration.
+    Completing 10% with 35 violations.
+    elapsed time = 00:00:00, memory = 1348.21 (MB).
+    Completing 20% with 35 violations.
+    elapsed time = 00:00:02, memory = 1358.78 (MB).
+    Completing 30% with 19 violations.
+    elapsed time = 00:00:03, memory = 1000.30 (MB).
+    Completing 40% with 19 violations.
+    elapsed time = 00:00:04, memory = 1226.32 (MB).
+    Completing 50% with 19 violations.
+    elapsed time = 00:00:05, memory = 1441.34 (MB).
+    Completing 60% with 6 violations.
+    elapsed time = 00:00:07, memory = 1442.63 (MB).
+    Completing 70% with 6 violations.
+    elapsed time = 00:00:08, memory = 1443.66 (MB).
+    Completing 80% with 2 violations.
+    elapsed time = 00:00:09, memory = 1011.70 (MB).
+    Completing 90% with 2 violations.
+    elapsed time = 00:00:10, memory = 1240.90 (MB).
+    Completing 100% with 0 violations.
+    elapsed time = 00:00:12, memory = 1441.73 (MB).
+[INFO DRT-0199]   Number of violations = 0.
+[INFO DRT-0267] cpu time = 00:00:23, elapsed time = 00:00:12, memory = 902.64 (MB), peak = 1476.13 (MB)
+Total wire length = 64292 um.
+Total wire length on LAYER Metal1 = 7 um.
+Total wire length on LAYER Metal2 = 28409 um.
+Total wire length on LAYER Metal3 = 35310 um.
+Total wire length on LAYER Metal4 = 564 um.
+Total wire length on LAYER Metal5 = 0 um.
+Total number of vias = 963.
+Up-via summary (total 963):.
+
+--------------
+  Poly2      0
+ Metal1    451
+ Metal2    510
+ Metal3      2
+ Metal4      0
+--------------
+           963
+
+
+[INFO DRT-0198] Complete detail routing.
+Total wire length = 64292 um.
+Total wire length on LAYER Metal1 = 7 um.
+Total wire length on LAYER Metal2 = 28409 um.
+Total wire length on LAYER Metal3 = 35310 um.
+Total wire length on LAYER Metal4 = 564 um.
+Total wire length on LAYER Metal5 = 0 um.
+Total number of vias = 963.
+Up-via summary (total 963):.
+
+--------------
+  Poly2      0
+ Metal1    451
+ Metal2    510
+ Metal3      2
+ Metal4      0
+--------------
+           963
+
+
+[INFO DRT-0267] cpu time = 00:00:46, elapsed time = 00:00:24, memory = 902.64 (MB), peak = 1476.13 (MB)
+
+[INFO DRT-0180] Post processing.
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.odb...
+Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/routing/19-wire_lengths.log b/openlane/cntr_example/runs/cntr_example/logs/routing/19-wire_lengths.log
new file mode 100644
index 0000000..02e74fb
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/routing/19-wire_lengths.log
@@ -0,0 +1,4 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+No wire length surpasses the threshold (Infinity μm).
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/20-parasitics_extraction.nom.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/20-parasitics_extraction.nom.log
new file mode 100644
index 0000000..941f3fc
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/20-parasitics_extraction.nom.log
@@ -0,0 +1,38 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO ODB-0222] Reading LEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef
+[INFO ODB-0223]     Created 13 technology layers
+[INFO ODB-0224]     Created 60 technology vias
+[INFO ODB-0225]     Created 229 library cells
+[INFO ODB-0226] Finished LEF file:  /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef
+[INFO ODB-0127] Reading DEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def
+[INFO ODB-0128] Design: cntr_example
+[INFO ODB-0130]     Created 42 pins.
+[INFO ODB-0131]     Created 58369 components and 117183 component-terminals.
+[INFO ODB-0132]     Created 2 special nets and 116738 connections.
+[INFO ODB-0133]     Created 111 nets and 445 connections.
+[INFO ODB-0134] Finished DEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def
+Using RCX ruleset '/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.nom.magic'...
+[INFO RCX-0431] Defined process_corner X with ext_model_index 0
+[INFO RCX-0029] Defined extraction corner X
+[INFO RCX-0008] extracting parasitics of cntr_example ...
+[INFO RCX-0435] Reading extraction model file /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.nom.magic ...
+[INFO RCX-0436] RC segment generation cntr_example (max_merge_res 50.0) ...
+[INFO RCX-0040] Final 808 rc segments
+[INFO RCX-0439] Coupling Cap extraction cntr_example ...
+[INFO RCX-0440] Coupling threshhold is 0.1000 fF, coupling capacitance less than 0.1000 fF will be grounded.
+[INFO RCX-0043] 1249 wires to be extracted
+[INFO RCX-0442] 14% completion -- 179 wires have been extracted
+[INFO RCX-0442] 65% completion -- 816 wires have been extracted
+[INFO RCX-0442] 76% completion -- 956 wires have been extracted
+[INFO RCX-0442] 100% completion -- 1249 wires have been extracted
+[INFO RCX-0045] Extract 111 nets, 919 rsegs, 919 caps, 708 ccs
+[INFO RCX-0015] Finished extracting cntr_example.
+Writing result to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.spef...
+Setting global connections for newly added cells...
+[WARNING] Did not save OpenROAD database!
+Writing extracted parasitics to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.spef...
+[INFO RCX-0016] Writing SPEF ...
+[INFO RCX-0443] 111 nets finished
+[INFO RCX-0017] Finished writing SPEF ...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/21-rcx_mcsta.nom.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/21-rcx_mcsta.nom.log
new file mode 100644
index 0000000..71dc7b9
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/21-rcx_mcsta.nom.log
@@ -0,0 +1,11503 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+min_report
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+
+======================= Slowest Corner ===================================
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  5.44    8.89   12.91 v _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.22                           net6 (net)
+                  5.45    0.06   12.97 v _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  1.91    4.04   17.01 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _042_ (net)
+                  1.91    0.00   17.01 ^ _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  6.07    4.35   21.37 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.08                           _017_ (net)
+                  6.07    0.01   21.38 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 21.38   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    4.69   clock uncertainty
+                         -0.42    4.27   clock reconvergence pessimism
+                         -1.19    3.07   library hold time
+                                  3.07   data required time
+-----------------------------------------------------------------------------
+                                  3.07   data required time
+                                -21.38   data arrival time
+-----------------------------------------------------------------------------
+                                 18.30   slack (MET)
+
+
+Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  5.45    8.33   12.34 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.11                           net7 (net)
+                  5.45    0.02   12.37 v _088_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  4.11    5.02   17.39 ^ _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.01                           _043_ (net)
+                  4.11    0.00   17.39 ^ _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  6.85    5.56   22.95 v _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.10                           _018_ (net)
+                  6.85    0.02   22.97 v _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 22.97   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    4.69   clock uncertainty
+                         -0.42    4.27   clock reconvergence pessimism
+                         -1.57    2.69   library hold time
+                                  2.69   data required time
+-----------------------------------------------------------------------------
+                                  2.69   data required time
+                                -22.97   data arrival time
+-----------------------------------------------------------------------------
+                                 20.27   slack (MET)
+
+
+Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67    3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    3.90 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  8.31    9.89   13.79 v _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.17                           net15 (net)
+                  8.31    0.04   13.83 v _065_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  2.79    4.83   18.67 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     1    0.01                           _031_ (net)
+                  2.79    0.00   18.67 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  6.27    4.77   23.44 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.09                           _007_ (net)
+                  6.27    0.02   23.46 v _101_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 23.46   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.31 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    4.56   clock uncertainty
+                         -0.41    4.15   clock reconvergence pessimism
+                         -1.47    2.69   library hold time
+                                  2.69   data required time
+-----------------------------------------------------------------------------
+                                  2.69   data required time
+                                -23.46   data arrival time
+-----------------------------------------------------------------------------
+                                 20.77   slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67    3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    3.90 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  5.03    8.59   12.50 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.20                           net21 (net)
+                  5.03    0.07   12.56 v _077_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  1.69    3.60   16.16 ^ _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.00                           _037_ (net)
+                  1.69    0.00   16.16 ^ _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                 10.35    6.71   22.87 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.13                           _013_ (net)
+                 10.35    0.04   22.91 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 22.91   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.31 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    4.56   clock uncertainty
+                         -0.41    4.15   clock reconvergence pessimism
+                         -2.35    1.80   library hold time
+                                  1.80   data required time
+-----------------------------------------------------------------------------
+                                  1.80   data required time
+                                -22.91   data arrival time
+-----------------------------------------------------------------------------
+                                 21.11   slack (MET)
+
+
+Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  8.52   10.07   14.09 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.17                           net18 (net)
+                  8.52    0.04   14.13 v _070_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  3.55    5.50   19.63 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _033_ (net)
+                  3.55    0.00   19.63 ^ _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  9.40    6.79   26.42 v _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.13                           _010_ (net)
+                  9.40    0.03   26.45 v _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 26.45   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    4.69   clock uncertainty
+                         -0.42    4.27   clock reconvergence pessimism
+                         -2.27    2.00   library hold time
+                                  2.00   data required time
+-----------------------------------------------------------------------------
+                                  2.00   data required time
+                                -26.45   data arrival time
+-----------------------------------------------------------------------------
+                                 24.45   slack (MET)
+
+
+Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  7.92   10.30   14.32 v _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.32                           net11 (net)
+                  7.93    0.10   14.41 v _052_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  4.62    6.13   20.54 ^ _052_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.02                           _023_ (net)
+                  4.62    0.00   20.54 ^ _055_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  8.06    6.47   27.01 v _055_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.12                           _002_ (net)
+                  8.06    0.03   27.04 v _096_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 27.04   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    4.69   clock uncertainty
+                         -0.42    4.27   clock reconvergence pessimism
+                         -1.73    2.54   library hold time
+                                  2.54   data required time
+-----------------------------------------------------------------------------
+                                  2.54   data required time
+                                -27.04   data arrival time
+-----------------------------------------------------------------------------
+                                 24.50   slack (MET)
+
+
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  5.77    9.08   13.10 v _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.23                           net2 (net)
+                  5.77    0.04   13.14 v _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  1.94    4.21   17.35 ^ _059_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _027_ (net)
+                  1.94    0.00   17.35 ^ _060_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                 14.19    9.01   26.36 v _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.19                           _005_ (net)
+                 14.19    0.04   26.40 v _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 26.40   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.32 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    4.57   clock uncertainty
+                         -0.24    4.33   clock reconvergence pessimism
+                         -3.24    1.09   library hold time
+                                  1.09   data required time
+-----------------------------------------------------------------------------
+                                  1.09   data required time
+                                -26.40   data arrival time
+-----------------------------------------------------------------------------
+                                 25.31   slack (MET)
+
+
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 14.64   14.99   19.01 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.23                           net2 (net)
+                 14.64    0.04   19.05 ^ _058_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  6.62    9.20   28.25 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.09                           _004_ (net)
+                  6.62    0.02   28.27 v _098_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 28.27   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    4.69   clock uncertainty
+                         -0.42    4.27   clock reconvergence pessimism
+                         -1.35    2.92   library hold time
+                                  2.92   data required time
+-----------------------------------------------------------------------------
+                                  2.92   data required time
+                                -28.27   data arrival time
+-----------------------------------------------------------------------------
+                                 25.35   slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67    3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    3.90 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  5.03    8.59   12.50 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.20                           net21 (net)
+                  5.03    0.06   12.56 v _079_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  4.01    4.81   17.37 ^ _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.01                           _038_ (net)
+                  4.01    0.00   17.37 ^ _082_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 13.20    9.16   26.54 v _082_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.19                           _014_ (net)
+                 13.20    0.06   26.59 v _108_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 26.59   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.31 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    4.56   clock uncertainty
+                         -0.41    4.15   clock reconvergence pessimism
+                         -3.02    1.14   library hold time
+                                  1.14   data required time
+-----------------------------------------------------------------------------
+                                  1.14   data required time
+                                -26.59   data arrival time
+-----------------------------------------------------------------------------
+                                 25.46   slack (MET)
+
+
+Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  4.94    8.60   12.62 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.20                           net14 (net)
+                  4.94    0.05   12.67 v _061_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  4.66    5.16   17.82 ^ _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.02                           _028_ (net)
+                  4.66    0.00   17.82 ^ _064_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 12.85    9.28   27.11 v _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.19                           _006_ (net)
+                 12.85    0.04   27.15 v _100_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 27.15   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    4.69   clock uncertainty
+                         -0.42    4.27   clock reconvergence pessimism
+                         -2.89    1.38   library hold time
+                                  1.38   data required time
+-----------------------------------------------------------------------------
+                                  1.38   data required time
+                                -27.15   data arrival time
+-----------------------------------------------------------------------------
+                                 25.77   slack (MET)
+
+
+Startpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  4.39    8.28   12.30 v _109_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     4    0.17                           net4 (net)
+                  4.39    0.05   12.35 v _083_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  4.21    4.29   16.63 ^ _083_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     2    0.01                           _041_ (net)
+                  4.21    0.00   16.63 ^ _084_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 14.71   10.69   27.32 v _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.23                           _015_ (net)
+                 14.71    0.07   27.39 v _109_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 27.39   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    4.69   clock uncertainty
+                         -0.42    4.27   clock reconvergence pessimism
+                         -3.30    0.96   library hold time
+                                  0.96   data required time
+-----------------------------------------------------------------------------
+                                  0.96   data required time
+                                -27.39   data arrival time
+-----------------------------------------------------------------------------
+                                 26.43   slack (MET)
+
+
+Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67    3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    3.90 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                 11.47   11.70   15.61 v _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.23                           net8 (net)
+                 11.47    0.04   15.64 v _092_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  4.49    7.14   22.78 ^ _092_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     1    0.01                           _046_ (net)
+                  4.49    0.00   22.78 ^ _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  9.32    7.33   30.11 v _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.14                           _019_ (net)
+                  9.32    0.03   30.14 v _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 30.14   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.32 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    4.57   clock uncertainty
+                         -0.41    4.15   clock reconvergence pessimism
+                         -2.30    1.86   library hold time
+                                  1.86   data required time
+-----------------------------------------------------------------------------
+                                  1.86   data required time
+                                -30.14   data arrival time
+-----------------------------------------------------------------------------
+                                 28.28   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 v input external delay
+                  0.41    0.14   13.14 v wb_rst_i (in)
+     2    0.01                           wb_rst_i (net)
+                  0.41    0.00   13.14 v input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  5.89    5.27   18.41 v input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  5.89    0.02   18.43 v _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  7.49    7.06   25.49 ^ _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.17                           _020_ (net)
+                  7.49    0.03   25.52 ^ _085_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  6.15    6.41   31.93 v _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.08                           _016_ (net)
+                  6.15    0.01   31.94 v _110_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 31.94   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.32 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    4.57   clock uncertainty
+                          0.00    4.57   clock reconvergence pessimism
+                         -1.27    3.30   library hold time
+                                  3.30   data required time
+-----------------------------------------------------------------------------
+                                  3.30   data required time
+                                -31.94   data arrival time
+-----------------------------------------------------------------------------
+                                 28.64   slack (MET)
+
+
+Startpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67    3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    3.90 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  7.80   10.12   14.03 v _097_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     4    0.32                           net12 (net)
+                  7.80    0.11   14.13 v _056_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  6.66    7.08   21.21 ^ _056_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     2    0.02                           _026_ (net)
+                  6.66    0.00   21.21 ^ _057_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 10.90    9.21   30.42 v _057_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.16                           _003_ (net)
+                 10.90    0.05   30.47 v _097_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 30.47   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.31 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    4.56   clock uncertainty
+                         -0.41    4.15   clock reconvergence pessimism
+                         -2.48    1.67   library hold time
+                                  1.67   data required time
+-----------------------------------------------------------------------------
+                                  1.67   data required time
+                                -30.47   data arrival time
+-----------------------------------------------------------------------------
+                                 28.79   slack (MET)
+
+
+Startpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[11] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  4.39    8.28   12.30 v _109_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     4    0.17                           net4 (net)
+                  4.39    0.03   12.33 v output4/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.80    4.37   16.71 v output4/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[11] (net)
+                  1.80    0.00   16.71 v io_out[11] (out)
+                                 16.71   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -16.71   data arrival time
+-----------------------------------------------------------------------------
+                                 29.46   slack (MET)
+
+
+Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  9.63   10.70   14.72 v _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.20                           net19 (net)
+                  9.63    0.04   14.76 v _074_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  4.72    6.66   21.42 ^ _074_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     1    0.01                           _036_ (net)
+                  4.72    0.00   21.42 ^ _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 12.33    9.37   30.79 v _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.19                           _011_ (net)
+                 12.33    0.05   30.84 v _105_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 30.84   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    4.69   clock uncertainty
+                         -0.42    4.27   clock reconvergence pessimism
+                         -2.99    1.28   library hold time
+                                  1.28   data required time
+-----------------------------------------------------------------------------
+                                  1.28   data required time
+                                -30.84   data arrival time
+-----------------------------------------------------------------------------
+                                 29.56   slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[9] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67    3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    3.90 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  5.03    8.59   12.50 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.20                           net21 (net)
+                  5.03    0.04   12.54 v output21/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.81    4.63   17.17 v output21/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[9] (net)
+                  1.81    0.00   17.17 v io_out[9] (out)
+                                 17.17   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -17.17   data arrival time
+-----------------------------------------------------------------------------
+                                 29.92   slack (MET)
+
+
+Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[14] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  5.45    8.33   12.34 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.11                           net7 (net)
+                  5.45    0.02   12.37 v output7/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.83    4.82   17.18 v output7/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[14] (net)
+                  1.83    0.00   17.19 v io_out[14] (out)
+                                 17.19   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -17.19   data arrival time
+-----------------------------------------------------------------------------
+                                 29.94   slack (MET)
+
+
+Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[2] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  4.94    8.60   12.62 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.20                           net14 (net)
+                  4.94    0.07   12.69 v output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.81    4.60   17.29 v output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[2] (net)
+                  1.81    0.00   17.29 v io_out[2] (out)
+                                 17.29   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -17.29   data arrival time
+-----------------------------------------------------------------------------
+                                 30.04   slack (MET)
+
+
+Startpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  9.92   11.40   15.42 v _103_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.41                           net17 (net)
+                  9.92    0.13   15.55 v _068_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  1.95    5.43   20.97 ^ _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _032_ (net)
+                  1.95    0.00   20.97 ^ _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                 15.90    9.98   30.95 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.21                           _009_ (net)
+                 15.90    0.05   31.01 v _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 31.01   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    4.69   clock uncertainty
+                         -0.42    4.27   clock reconvergence pessimism
+                         -3.56    0.71   library hold time
+                                  0.71   data required time
+-----------------------------------------------------------------------------
+                                  0.71   data required time
+                                -31.01   data arrival time
+-----------------------------------------------------------------------------
+                                 30.30   slack (MET)
+
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[13] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  5.44    8.89   12.91 v _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.22                           net6 (net)
+                  5.45    0.07   12.98 v output6/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.81    4.81   17.79 v output6/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[13] (net)
+                  1.81    0.00   17.79 v io_out[13] (out)
+                                 17.79   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -17.79   data arrival time
+-----------------------------------------------------------------------------
+                                 30.54   slack (MET)
+
+
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  5.77    9.08   13.10 v _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.23                           net2 (net)
+                  5.77    0.02   13.12 v output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.83    4.94   18.06 v output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[0] (net)
+                  1.83    0.00   18.06 v io_out[0] (out)
+                                 18.06   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -18.06   data arrival time
+-----------------------------------------------------------------------------
+                                 30.81   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 v input external delay
+                  0.41    0.14   13.14 v wb_rst_i (in)
+     2    0.01                           wb_rst_i (net)
+                  0.41    0.00   13.14 v input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  5.89    5.27   18.41 v input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  5.89    0.02   18.43 v _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  7.49    7.06   25.49 ^ _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.17                           _020_ (net)
+                  7.49    0.03   25.52 ^ _067_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  9.43    8.58   34.10 v _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.14                           _008_ (net)
+                  9.43    0.02   34.12 v _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 34.12   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.32 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    4.57   clock uncertainty
+                          0.00    4.57   clock reconvergence pessimism
+                         -2.13    2.43   library hold time
+                                  2.43   data required time
+-----------------------------------------------------------------------------
+                                  2.43   data required time
+                                -34.12   data arrival time
+-----------------------------------------------------------------------------
+                                 31.69   slack (MET)
+
+
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  8.84   10.81   14.83 v _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.36                           net9 (net)
+                  8.84    0.12   14.95 v _050_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  3.13    6.89   21.83 ^ _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     2    0.02                           _022_ (net)
+                  3.13    0.00   21.84 ^ _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                 16.97   11.05   32.88 v _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.22                           _001_ (net)
+                 16.97    0.06   32.94 v _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 32.94   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.31 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    4.56   clock uncertainty
+                         -0.24    4.33   clock reconvergence pessimism
+                         -3.83    0.50   library hold time
+                                  0.50   data required time
+-----------------------------------------------------------------------------
+                                  0.50   data required time
+                                -32.94   data arrival time
+-----------------------------------------------------------------------------
+                                 32.44   slack (MET)
+
+
+Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[3] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67    3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    3.90 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  8.31    9.89   13.79 v _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.17                           net15 (net)
+                  8.31    0.05   13.85 v output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.87    5.85   19.70 v output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[3] (net)
+                  1.87    0.00   19.70 v io_out[3] (out)
+                                 19.70   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -19.70   data arrival time
+-----------------------------------------------------------------------------
+                                 32.45   slack (MET)
+
+
+Startpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[19] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67    3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    3.90 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  7.80   10.12   14.03 v _097_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     4    0.32                           net12 (net)
+                  7.81    0.17   14.19 v output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.87    5.68   19.88 v output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[19] (net)
+                  1.87    0.00   19.88 v io_out[19] (out)
+                                 19.88   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -19.88   data arrival time
+-----------------------------------------------------------------------------
+                                 32.63   slack (MET)
+
+
+Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[6] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  8.52   10.07   14.09 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.17                           net18 (net)
+                  8.52    0.02   14.11 v output18/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.87    5.92   20.03 v output18/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[6] (net)
+                  1.87    0.00   20.03 v io_out[6] (out)
+                                 20.03   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -20.03   data arrival time
+-----------------------------------------------------------------------------
+                                 32.78   slack (MET)
+
+
+Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[18] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  7.92   10.30   14.32 v _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.32                           net11 (net)
+                  7.93    0.13   14.44 v output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.85    5.71   20.16 v output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[18] (net)
+                  1.85    0.00   20.16 v io_out[18] (out)
+                                 20.16   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -20.16   data arrival time
+-----------------------------------------------------------------------------
+                                 32.91   slack (MET)
+
+
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  8.84   10.81   14.83 v _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.36                           net9 (net)
+                  8.84    0.14   14.97 v output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.87    6.03   21.00 v output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[16] (net)
+                  1.87    0.00   21.00 v io_out[16] (out)
+                                 21.00   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -21.00   data arrival time
+-----------------------------------------------------------------------------
+                                 33.75   slack (MET)
+
+
+Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[7] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  9.63   10.70   14.72 v _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.20                           net19 (net)
+                  9.63    0.03   14.75 v output19/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.89    6.31   21.06 v output19/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[7] (net)
+                  1.89    0.00   21.07 v io_out[7] (out)
+                                 21.07   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -21.07   data arrival time
+-----------------------------------------------------------------------------
+                                 33.82   slack (MET)
+
+
+Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[8] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  9.12   10.97   14.99 v _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.37                           net20 (net)
+                  9.13    0.15   15.14 v output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.88    6.14   21.28 v output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[8] (net)
+                  1.88    0.00   21.28 v io_out[8] (out)
+                                 21.28   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -21.28   data arrival time
+-----------------------------------------------------------------------------
+                                 34.03   slack (MET)
+
+
+Startpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[5] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78    4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.02 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  9.92   11.40   15.42 v _103_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.41                           net17 (net)
+                  9.93    0.18   15.61 v output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.91    6.40   22.01 v output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[5] (net)
+                  1.91    0.00   22.01 v io_out[5] (out)
+                                 22.01   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -22.01   data arrival time
+-----------------------------------------------------------------------------
+                                 34.76   slack (MET)
+
+
+Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[15] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67    3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    3.90 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                 11.47   11.70   15.61 v _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.23                           net8 (net)
+                 11.47    0.00   15.61 v output8/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.93    6.86   22.47 v output8/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[15] (net)
+                  1.93    0.00   22.47 v io_out[15] (out)
+                                 22.47   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -22.47   data arrival time
+-----------------------------------------------------------------------------
+                                 35.22   slack (MET)
+
+
+Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[10] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67    3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    3.90 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 10.91   11.93   15.83 v _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.45                           net3 (net)
+                 10.91    0.17   16.00 v output3/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.94    6.71   22.71 v output3/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[10] (net)
+                  1.94    0.00   22.71 v io_out[10] (out)
+                                 22.71   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -22.71   data arrival time
+-----------------------------------------------------------------------------
+                                 35.46   slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[12] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67    3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    3.90 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 11.32   12.15   16.06 v _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.46                           net5 (net)
+                 11.33    0.21   16.26 v output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.93    6.82   23.08 v output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[12] (net)
+                  1.93    0.00   23.08 v io_out[12] (out)
+                                 23.08   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -23.08   data arrival time
+-----------------------------------------------------------------------------
+                                 35.83   slack (MET)
+
+
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[4] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67    3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    3.90 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 11.51   12.26   16.16 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.47                           net16 (net)
+                 11.52    0.20   16.36 v output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.92    6.87   23.23 v output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[4] (net)
+                  1.92    0.00   23.23 v io_out[4] (out)
+                                 23.23   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -23.23   data arrival time
+-----------------------------------------------------------------------------
+                                 35.98   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 v input external delay
+                  0.41    0.14   13.14 v wb_rst_i (in)
+     2    0.01                           wb_rst_i (net)
+                  0.41    0.00   13.14 v input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  5.89    5.27   18.41 v input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  5.89    0.02   18.43 v _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  7.49    7.06   25.49 ^ _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.17                           _020_ (net)
+                  7.49    0.02   25.52 ^ _048_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 14.79   12.08   37.60 v _048_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.23                           _000_ (net)
+                 14.79    0.05   37.65 v _094_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 37.65   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    4.69   clock uncertainty
+                          0.00    4.69   clock reconvergence pessimism
+                         -3.32    1.37   library hold time
+                                  1.37   data required time
+-----------------------------------------------------------------------------
+                                  1.37   data required time
+                                -37.65   data arrival time
+-----------------------------------------------------------------------------
+                                 36.27   slack (MET)
+
+
+Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67    3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    3.90 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 12.75   12.99   16.90 v _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.52                           net13 (net)
+                 12.75    0.06   16.96 v output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.96    7.24   24.20 v output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[1] (net)
+                  1.96    0.00   24.20 v io_out[1] (out)
+                                 24.20   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -24.20   data arrival time
+-----------------------------------------------------------------------------
+                                 36.95   slack (MET)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[17] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.49    0.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74    2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67    3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    3.90 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 12.80   13.00   16.90 v _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.53                           net10 (net)
+                 12.81    0.19   17.09 v output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  1.99    7.28   24.38 v output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[17] (net)
+                  1.99    0.00   24.38 v io_out[17] (out)
+                                 24.38   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                -24.38   data arrival time
+-----------------------------------------------------------------------------
+                                 37.13   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 v input external delay
+                  0.41    0.14   13.14 v wb_rst_i (in)
+     2    0.01                           wb_rst_i (net)
+                  0.41    0.00   13.14 v input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  5.89    5.27   18.41 v input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  5.89    0.02   18.43 v _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  7.49    7.06   25.49 ^ _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.17                           _020_ (net)
+                  7.49    0.02   25.51 ^ _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 27.34   20.23   45.74 v _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.43                           _012_ (net)
+                 27.34    0.10   45.85 v _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 45.85   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    4.69   clock uncertainty
+                          0.00    4.69   clock reconvergence pessimism
+                         -5.89   -1.20   library hold time
+                                 -1.20   data required time
+-----------------------------------------------------------------------------
+                                 -1.20   data required time
+                                -45.85   data arrival time
+-----------------------------------------------------------------------------
+                                 47.05   slack (MET)
+
+
+
+======================= Typical Corner ===================================
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.35    1.72    2.49 v _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.22                           net6 (net)
+                  1.36    0.06    2.55 v _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.47    0.58    3.13 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _042_ (net)
+                  0.47    0.00    3.13 ^ _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  1.55    1.04    4.17 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.08                           _017_ (net)
+                  1.55    0.01    4.19 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  4.19   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.10   clock uncertainty
+                         -0.08    1.02   clock reconvergence pessimism
+                         -0.29    0.73   library hold time
+                                  0.73   data required time
+-----------------------------------------------------------------------------
+                                  0.73   data required time
+                                 -4.19   data arrival time
+-----------------------------------------------------------------------------
+                                  3.46   slack (MET)
+
+
+Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.36    1.66    2.43 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.11                           net7 (net)
+                  1.36    0.03    2.46 v _088_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.81    0.74    3.19 ^ _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.02                           _043_ (net)
+                  0.81    0.00    3.19 ^ _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  1.70    1.19    4.38 v _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.10                           _018_ (net)
+                  1.70    0.02    4.40 v _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  4.40   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    1.10   clock uncertainty
+                         -0.08    1.02   clock reconvergence pessimism
+                         -0.35    0.67   library hold time
+                                  0.67   data required time
+-----------------------------------------------------------------------------
+                                  0.67   data required time
+                                 -4.40   data arrival time
+-----------------------------------------------------------------------------
+                                  3.73   slack (MET)
+
+
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.44    1.79    2.56 v _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.23                           net2 (net)
+                  1.44    0.04    2.60 v _058_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  4.10    2.67    5.27 ^ _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.09                           _004_ (net)
+                  4.10    0.02    5.29 ^ _098_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  5.29   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.10   clock uncertainty
+                         -0.08    1.02   clock reconvergence pessimism
+                          0.30    1.32   library hold time
+                                  1.32   data required time
+-----------------------------------------------------------------------------
+                                  1.32   data required time
+                                 -5.29   data arrival time
+-----------------------------------------------------------------------------
+                                  3.97   slack (MET)
+
+
+Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32    0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.75 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.08    2.05    2.81 v _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.17                           net15 (net)
+                  2.08    0.04    2.84 v _065_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  0.47    0.78    3.63 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     1    0.01                           _031_ (net)
+                  0.47    0.00    3.63 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  1.57    1.05    4.68 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.09                           _007_ (net)
+                  1.57    0.02    4.70 v _101_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  4.70   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    1.08   clock uncertainty
+                         -0.08    1.00   clock reconvergence pessimism
+                         -0.33    0.68   library hold time
+                                  0.68   data required time
+-----------------------------------------------------------------------------
+                                  0.68   data required time
+                                 -4.70   data arrival time
+-----------------------------------------------------------------------------
+                                  4.02   slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32    0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.75 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.24    1.65    2.41 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.20                           net21 (net)
+                  1.25    0.07    2.47 v _077_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.44    0.51    2.98 ^ _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _037_ (net)
+                  0.44    0.00    2.98 ^ _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  2.61    1.64    4.63 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.13                           _013_ (net)
+                  2.61    0.04    4.66 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  4.66   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.08   clock uncertainty
+                         -0.08    1.00   clock reconvergence pessimism
+                         -0.56    0.44   library hold time
+                                  0.44   data required time
+-----------------------------------------------------------------------------
+                                  0.44   data required time
+                                 -4.66   data arrival time
+-----------------------------------------------------------------------------
+                                  4.22   slack (MET)
+
+
+Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.97    2.05    2.83 v _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.32                           net11 (net)
+                  1.99    0.10    2.92 v _052_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.95    0.88    3.81 ^ _052_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.02                           _023_ (net)
+                  0.95    0.00    3.81 ^ _055_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  2.01    1.40    5.21 v _055_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.12                           _002_ (net)
+                  2.01    0.03    5.24 v _096_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  5.24   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.10   clock uncertainty
+                         -0.08    1.02   clock reconvergence pessimism
+                         -0.41    0.62   library hold time
+                                  0.62   data required time
+-----------------------------------------------------------------------------
+                                  0.62   data required time
+                                 -5.24   data arrival time
+-----------------------------------------------------------------------------
+                                  4.62   slack (MET)
+
+
+Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.13    2.09    2.87 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.17                           net18 (net)
+                  2.13    0.04    2.91 v _070_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.80    0.76    3.67 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _033_ (net)
+                  0.80    0.00    3.67 ^ _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  2.33    1.55    5.22 v _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.13                           _010_ (net)
+                  2.34    0.03    5.25 v _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  5.25   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.86 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    1.11   clock uncertainty
+                         -0.08    1.02   clock reconvergence pessimism
+                         -0.52    0.51   library hold time
+                                  0.51   data required time
+-----------------------------------------------------------------------------
+                                  0.51   data required time
+                                 -5.25   data arrival time
+-----------------------------------------------------------------------------
+                                  4.75   slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32    0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.75 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.83    2.50    3.25 v _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.47                           net5 (net)
+                  2.84    0.10    3.36 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  3.75    2.90    6.25 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.08                           _016_ (net)
+                  3.75    0.01    6.27 ^ _110_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  6.27   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.08   clock uncertainty
+                         -0.08    1.00   clock reconvergence pessimism
+                          0.25    1.26   library hold time
+                                  1.26   data required time
+-----------------------------------------------------------------------------
+                                  1.26   data required time
+                                 -6.27   data arrival time
+-----------------------------------------------------------------------------
+                                  5.01   slack (MET)
+
+
+Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.22    1.65    2.42 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.20                           net14 (net)
+                  1.22    0.05    2.47 v _061_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.86    0.76    3.23 ^ _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.02                           _028_ (net)
+                  0.86    0.00    3.23 ^ _064_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  3.24    2.09    5.32 v _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.19                           _006_ (net)
+                  3.24    0.04    5.36 v _100_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  5.36   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.10   clock uncertainty
+                         -0.08    1.02   clock reconvergence pessimism
+                         -0.70    0.32   library hold time
+                                  0.32   data required time
+-----------------------------------------------------------------------------
+                                  0.32   data required time
+                                 -5.36   data arrival time
+-----------------------------------------------------------------------------
+                                  5.04   slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32    0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.75 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.24    1.65    2.41 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.20                           net21 (net)
+                  1.25    0.06    2.47 v _079_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.84    0.79    3.26 ^ _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.01                           _038_ (net)
+                  0.84    0.00    3.26 ^ _082_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  3.29    2.10    5.36 v _082_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.19                           _014_ (net)
+                  3.30    0.06    5.42 v _108_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  5.42   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.08   clock uncertainty
+                         -0.08    1.00   clock reconvergence pessimism
+                         -0.72    0.28   library hold time
+                                  0.28   data required time
+-----------------------------------------------------------------------------
+                                  0.28   data required time
+                                 -5.42   data arrival time
+-----------------------------------------------------------------------------
+                                  5.14   slack (MET)
+
+
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.44    1.79    2.56 v _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.23                           net2 (net)
+                  1.44    0.04    2.60 v _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.48    0.68    3.28 ^ _059_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _027_ (net)
+                  0.48    0.00    3.28 ^ _060_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  3.58    2.22    5.50 v _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.19                           _005_ (net)
+                  3.59    0.04    5.54 v _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  5.54   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.08   clock uncertainty
+                         -0.05    1.04   clock reconvergence pessimism
+                         -0.78    0.25   library hold time
+                                  0.25   data required time
+-----------------------------------------------------------------------------
+                                  0.25   data required time
+                                 -5.54   data arrival time
+-----------------------------------------------------------------------------
+                                  5.28   slack (MET)
+
+
+Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.36    1.66    2.43 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.11                           net7 (net)
+                  1.36    0.03    2.46 v _089_/A3 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+                  1.06    1.02    3.47 ^ _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+     4    0.03                           _044_ (net)
+                  1.06    0.00    3.47 ^ _092_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  0.74    0.72    4.19 ^ _092_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     1    0.01                           _046_ (net)
+                  0.74    0.00    4.19 ^ _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  2.38    1.59    5.78 v _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.14                           _019_ (net)
+                  2.38    0.03    5.81 v _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  5.81   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    1.08   clock uncertainty
+                         -0.05    1.04   clock reconvergence pessimism
+                         -0.53    0.51   library hold time
+                                  0.51   data required time
+-----------------------------------------------------------------------------
+                                  0.51   data required time
+                                 -5.81   data arrival time
+-----------------------------------------------------------------------------
+                                  5.30   slack (MET)
+
+
+Startpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.08    1.58    2.35 v _109_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     4    0.17                           net4 (net)
+                  1.09    0.05    2.39 v _083_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  0.69    0.69    3.09 ^ _083_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     2    0.01                           _041_ (net)
+                  0.69    0.00    3.09 ^ _084_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  3.88    2.43    5.51 v _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.23                           _015_ (net)
+                  3.89    0.07    5.59 v _109_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  5.59   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.10   clock uncertainty
+                         -0.08    1.02   clock reconvergence pessimism
+                         -0.85    0.18   library hold time
+                                  0.18   data required time
+-----------------------------------------------------------------------------
+                                  0.18   data required time
+                                 -5.59   data arrival time
+-----------------------------------------------------------------------------
+                                  5.41   slack (MET)
+
+
+Startpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32    0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.75 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.93    1.99    2.74 v _097_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     4    0.32                           net12 (net)
+                  1.95    0.11    2.85 v _056_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  1.08    1.15    4.00 ^ _056_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     2    0.02                           _026_ (net)
+                  1.08    0.00    4.00 ^ _057_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  2.82    1.92    5.92 v _057_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.16                           _003_ (net)
+                  2.82    0.05    5.96 v _097_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  5.96   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.08   clock uncertainty
+                         -0.08    1.00   clock reconvergence pessimism
+                         -0.61    0.39   library hold time
+                                  0.39   data required time
+-----------------------------------------------------------------------------
+                                  0.39   data required time
+                                 -5.96   data arrival time
+-----------------------------------------------------------------------------
+                                  5.57   slack (MET)
+
+
+Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.40    2.25    3.03 v _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.20                           net19 (net)
+                  2.41    0.04    3.07 v _074_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  0.78    1.08    4.14 ^ _074_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     1    0.01                           _036_ (net)
+                  0.78    0.00    4.14 ^ _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  3.23    2.08    6.22 v _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.19                           _011_ (net)
+                  3.23    0.05    6.27 v _105_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  6.27   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    1.10   clock uncertainty
+                         -0.08    1.02   clock reconvergence pessimism
+                         -0.73    0.29   library hold time
+                                  0.29   data required time
+-----------------------------------------------------------------------------
+                                  0.29   data required time
+                                 -6.27   data arrival time
+-----------------------------------------------------------------------------
+                                  5.98   slack (MET)
+
+
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32    0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.75 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.88    2.52    3.27 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.47                           net16 (net)
+                  2.89    0.10    3.37 v _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  6.14    4.21    7.58 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.14                           _008_ (net)
+                  6.14    0.02    7.60 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  7.60   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.08   clock uncertainty
+                         -0.08    1.00   clock reconvergence pessimism
+                          0.54    1.54   library hold time
+                                  1.54   data required time
+-----------------------------------------------------------------------------
+                                  1.54   data required time
+                                 -7.60   data arrival time
+-----------------------------------------------------------------------------
+                                  6.06   slack (MET)
+
+
+Startpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.47    2.30    3.07 v _103_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.41                           net17 (net)
+                  2.50    0.13    3.20 v _068_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.48    0.78    3.98 ^ _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _032_ (net)
+                  0.48    0.00    3.98 ^ _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  4.01    2.45    6.43 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.21                           _009_ (net)
+                  4.01    0.05    6.48 v _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  6.48   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.86 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.11   clock uncertainty
+                         -0.08    1.02   clock reconvergence pessimism
+                         -0.87    0.15   library hold time
+                                  0.15   data required time
+-----------------------------------------------------------------------------
+                                  0.15   data required time
+                                 -6.48   data arrival time
+-----------------------------------------------------------------------------
+                                  6.33   slack (MET)
+
+
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.21    2.17    2.95 v _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.36                           net9 (net)
+                  2.23    0.12    3.06 v _050_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.66    1.12    4.19 ^ _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     2    0.02                           _022_ (net)
+                  0.66    0.00    4.19 ^ _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  4.27    2.65    6.84 v _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.22                           _001_ (net)
+                  4.28    0.06    6.90 v _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  6.90   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.08   clock uncertainty
+                         -0.05    1.04   clock reconvergence pessimism
+                         -0.94    0.10   library hold time
+                                  0.10   data required time
+-----------------------------------------------------------------------------
+                                  0.10   data required time
+                                 -6.90   data arrival time
+-----------------------------------------------------------------------------
+                                  6.80   slack (MET)
+
+
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.21    2.17    2.95 v _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.36                           net9 (net)
+                  2.22    0.10    3.04 v _048_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  9.99    6.13    9.18 ^ _048_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.23                           _000_ (net)
+                  9.99    0.05    9.22 ^ _094_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  9.22   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.10   clock uncertainty
+                         -0.08    1.02   clock reconvergence pessimism
+                          1.05    2.07   library hold time
+                                  2.07   data required time
+-----------------------------------------------------------------------------
+                                  2.07   data required time
+                                 -9.22   data arrival time
+-----------------------------------------------------------------------------
+                                  7.15   slack (MET)
+
+
+Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  4.32    3.34    4.12 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.37                           net20 (net)
+                  4.33    0.11    4.23 ^ _076_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  7.15    5.58    9.81 v _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.43                           _012_ (net)
+                  7.15    0.10    9.91 v _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  9.91   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.86 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.11   clock uncertainty
+                         -0.08    1.02   clock reconvergence pessimism
+                         -1.55   -0.53   library hold time
+                                 -0.53   data required time
+-----------------------------------------------------------------------------
+                                 -0.53   data required time
+                                 -9.91   data arrival time
+-----------------------------------------------------------------------------
+                                 10.44   slack (MET)
+
+
+Startpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[11] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.08    1.58    2.35 v _109_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     4    0.17                           net4 (net)
+                  1.09    0.03    2.38 v output4/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.45    0.77    3.15 v output4/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[11] (net)
+                  0.45    0.00    3.15 v io_out[11] (out)
+                                  3.15   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -3.15   data arrival time
+-----------------------------------------------------------------------------
+                                 15.90   slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[9] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32    0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.75 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.24    1.65    2.41 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.20                           net21 (net)
+                  1.25    0.04    2.45 v output21/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.45    0.81    3.25 v output21/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[9] (net)
+                  0.45    0.00    3.26 v io_out[9] (out)
+                                  3.26   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -3.26   data arrival time
+-----------------------------------------------------------------------------
+                                 16.01   slack (MET)
+
+
+Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[14] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.36    1.66    2.43 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.11                           net7 (net)
+                  1.36    0.02    2.45 v output7/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.46    0.83    3.28 v output7/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[14] (net)
+                  0.46    0.00    3.28 v io_out[14] (out)
+                                  3.28   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -3.28   data arrival time
+-----------------------------------------------------------------------------
+                                 16.03   slack (MET)
+
+
+Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[2] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.22    1.65    2.42 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.20                           net14 (net)
+                  1.23    0.07    2.49 v output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.45    0.80    3.29 v output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[2] (net)
+                  0.45    0.00    3.29 v io_out[2] (out)
+                                  3.29   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -3.29   data arrival time
+-----------------------------------------------------------------------------
+                                 16.04   slack (MET)
+
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[13] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.35    1.72    2.49 v _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.22                           net6 (net)
+                  1.36    0.07    2.56 v output6/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.46    0.83    3.39 v output6/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[13] (net)
+                  0.46    0.00    3.39 v io_out[13] (out)
+                                  3.39   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -3.39   data arrival time
+-----------------------------------------------------------------------------
+                                 16.14   slack (MET)
+
+
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.44    1.79    2.56 v _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.23                           net2 (net)
+                  1.44    0.02    2.58 v output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.46    0.84    3.42 v output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[0] (net)
+                  0.46    0.00    3.42 v io_out[0] (out)
+                                  3.42   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -3.42   data arrival time
+-----------------------------------------------------------------------------
+                                 16.17   slack (MET)
+
+
+Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[3] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32    0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.75 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.08    2.05    2.81 v _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.17                           net15 (net)
+                  2.09    0.05    2.86 v output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.47    0.95    3.81 v output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[3] (net)
+                  0.47    0.00    3.81 v io_out[3] (out)
+                                  3.81   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -3.81   data arrival time
+-----------------------------------------------------------------------------
+                                 16.56   slack (MET)
+
+
+Startpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[19] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32    0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.75 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.93    1.99    2.74 v _097_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     4    0.32                           net12 (net)
+                  1.98    0.16    2.90 v output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.47    0.93    3.84 v output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[19] (net)
+                  0.47    0.00    3.84 v io_out[19] (out)
+                                  3.84   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -3.84   data arrival time
+-----------------------------------------------------------------------------
+                                 16.59   slack (MET)
+
+
+Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[6] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.13    2.09    2.87 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.17                           net18 (net)
+                  2.13    0.02    2.89 v output18/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.47    0.96    3.85 v output18/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[6] (net)
+                  0.47    0.00    3.85 v io_out[6] (out)
+                                  3.85   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -3.85   data arrival time
+-----------------------------------------------------------------------------
+                                 16.60   slack (MET)
+
+
+Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[18] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.97    2.05    2.83 v _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.32                           net11 (net)
+                  2.00    0.13    2.95 v output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.47    0.94    3.89 v output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[18] (net)
+                  0.47    0.00    3.89 v io_out[18] (out)
+                                  3.89   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -3.89   data arrival time
+-----------------------------------------------------------------------------
+                                 16.64   slack (MET)
+
+
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.21    2.17    2.95 v _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.36                           net9 (net)
+                  2.24    0.14    3.09 v output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.47    0.97    4.06 v output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[16] (net)
+                  0.47    0.00    4.06 v io_out[16] (out)
+                                  4.06   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -4.06   data arrival time
+-----------------------------------------------------------------------------
+                                 16.81   slack (MET)
+
+
+Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[7] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.40    2.25    3.03 v _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.20                           net19 (net)
+                  2.41    0.03    3.06 v output19/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    1.00    4.06 v output19/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[7] (net)
+                  0.48    0.00    4.06 v io_out[7] (out)
+                                  4.06   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -4.06   data arrival time
+-----------------------------------------------------------------------------
+                                 16.81   slack (MET)
+
+
+Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[8] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.28    2.21    2.98 v _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.37                           net20 (net)
+                  2.31    0.15    3.13 v output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    0.99    4.12 v output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[8] (net)
+                  0.48    0.00    4.12 v io_out[8] (out)
+                                  4.12   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -4.12   data arrival time
+-----------------------------------------------------------------------------
+                                 16.87   slack (MET)
+
+
+Startpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[5] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.47    2.30    3.07 v _103_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.41                           net17 (net)
+                  2.52    0.18    3.25 v output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.48    1.02    4.27 v output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[5] (net)
+                  0.48    0.00    4.27 v io_out[5] (out)
+                                  4.27   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -4.27   data arrival time
+-----------------------------------------------------------------------------
+                                 17.02   slack (MET)
+
+
+Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[15] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32    0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.75 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.88    2.52    3.27 v _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.23                           net8 (net)
+                  2.88    0.00    3.28 v output8/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.49    1.07    4.34 v output8/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[15] (net)
+                  0.49    0.00    4.34 v io_out[15] (out)
+                                  4.34   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -4.34   data arrival time
+-----------------------------------------------------------------------------
+                                 17.09   slack (MET)
+
+
+Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[10] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32    0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.75 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.72    2.46    3.21 v _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.45                           net3 (net)
+                  2.76    0.17    3.38 v output3/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.49    1.05    4.43 v output3/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[10] (net)
+                  0.49    0.00    4.43 v io_out[10] (out)
+                                  4.43   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -4.43   data arrival time
+-----------------------------------------------------------------------------
+                                 17.18   slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[12] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32    0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.75 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.83    2.50    3.25 v _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.47                           net5 (net)
+                  2.88    0.21    3.46 v output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.49    1.07    4.53 v output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[12] (net)
+                  0.49    0.00    4.53 v io_out[12] (out)
+                                  4.53   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -4.53   data arrival time
+-----------------------------------------------------------------------------
+                                 17.28   slack (MET)
+
+
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[4] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32    0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.75 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.88    2.52    3.27 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.47                           net16 (net)
+                  2.92    0.20    3.47 v output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.49    1.07    4.54 v output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[4] (net)
+                  0.49    0.00    4.54 v io_out[4] (out)
+                                  4.54   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -4.54   data arrival time
+-----------------------------------------------------------------------------
+                                 17.29   slack (MET)
+
+
+Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32    0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.75 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  3.19    2.78    3.53 v _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.52                           net13 (net)
+                  3.19    0.06    3.59 v output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.50    1.11    4.70 v output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[1] (net)
+                  0.50    0.00    4.70 v io_out[1] (out)
+                                  4.70   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -4.70   data arrival time
+-----------------------------------------------------------------------------
+                                 17.45   slack (MET)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[17] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32    0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.75 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  3.20    2.72    3.47 v _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.53                           net10 (net)
+                  3.24    0.19    3.66 v output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.50    1.12    4.79 v output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[17] (net)
+                  0.50    0.00    4.79 v io_out[17] (out)
+                                  4.79   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -4.79   data arrival time
+-----------------------------------------------------------------------------
+                                 17.54   slack (MET)
+
+
+
+======================= Fastest Corner ===================================
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.37 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.17    1.04    1.40 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.22                           net6 (net)
+                  1.18    0.06    1.46 ^ _087_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.80    0.52    1.98 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.08                           _017_ (net)
+                  0.80    0.01    2.00 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.00   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    0.65   clock uncertainty
+                         -0.04    0.62   clock reconvergence pessimism
+                         -0.12    0.50   library hold time
+                                  0.50   data required time
+-----------------------------------------------------------------------------
+                                  0.50   data required time
+                                 -2.00   data arrival time
+-----------------------------------------------------------------------------
+                                  1.50   slack (MET)
+
+
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.37 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.75    0.83    1.20 v _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.23                           net2 (net)
+                  0.76    0.04    1.24 v _058_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  1.71    1.11    2.35 ^ _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.09                           _004_ (net)
+                  1.71    0.02    2.37 ^ _098_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.37   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    0.65   clock uncertainty
+                         -0.04    0.62   clock reconvergence pessimism
+                          0.17    0.78   library hold time
+                                  0.78   data required time
+-----------------------------------------------------------------------------
+                                  0.78   data required time
+                                 -2.37   data arrival time
+-----------------------------------------------------------------------------
+                                  1.58   slack (MET)
+
+
+Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.36 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  0.72    0.78    1.15 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.11                           net7 (net)
+                  0.73    0.02    1.17 v _088_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.39    0.32    1.49 ^ _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.02                           _043_ (net)
+                  0.39    0.00    1.49 ^ _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  0.89    0.59    2.08 v _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.10                           _018_ (net)
+                  0.89    0.02    2.10 v _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  2.10   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    0.65   clock uncertainty
+                         -0.04    0.61   clock reconvergence pessimism
+                         -0.16    0.46   library hold time
+                                  0.46   data required time
+-----------------------------------------------------------------------------
+                                  0.46   data required time
+                                 -2.10   data arrival time
+-----------------------------------------------------------------------------
+                                  1.64   slack (MET)
+
+
+Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.36 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.64    0.75    1.11 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.20                           net14 (net)
+                  0.66    0.05    1.16 v _062_/A3 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+                  0.43    0.40    1.57 ^ _062_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+     4    0.02                           _029_ (net)
+                  0.43    0.00    1.57 ^ _065_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  0.15    0.08    1.65 v _065_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     1    0.01                           _031_ (net)
+                  0.15    0.00    1.65 v _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  1.65    0.94    2.59 ^ _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.09                           _007_ (net)
+                  1.65    0.02    2.61 ^ _101_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  2.61   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.17    0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.39 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    0.64   clock uncertainty
+                         -0.02    0.62   clock reconvergence pessimism
+                          0.16    0.78   library hold time
+                                  0.78   data required time
+-----------------------------------------------------------------------------
+                                  0.78   data required time
+                                 -2.61   data arrival time
+-----------------------------------------------------------------------------
+                                  1.83   slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15    0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.36 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.08    0.99    1.34 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.20                           net21 (net)
+                  1.09    0.07    1.41 ^ _077_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.22    0.11    1.52 v _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _037_ (net)
+                  0.22    0.00    1.52 v _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  1.91    1.09    2.61 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.13                           _013_ (net)
+                  1.91    0.04    2.65 ^ _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.65   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.17    0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.39 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    0.64   clock uncertainty
+                         -0.04    0.61   clock reconvergence pessimism
+                          0.19    0.80   library hold time
+                                  0.80   data required time
+-----------------------------------------------------------------------------
+                                  0.80   data required time
+                                 -2.65   data arrival time
+-----------------------------------------------------------------------------
+                                  1.85   slack (MET)
+
+
+Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.36 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.04    0.95    1.31 v _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.32                           net11 (net)
+                  1.07    0.10    1.41 v _052_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.48    0.39    1.80 ^ _052_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.02                           _023_ (net)
+                  0.48    0.00    1.80 ^ _055_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  1.05    0.69    2.50 v _055_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.12                           _002_ (net)
+                  1.05    0.03    2.53 v _096_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.53   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    0.65   clock uncertainty
+                         -0.04    0.61   clock reconvergence pessimism
+                         -0.18    0.43   library hold time
+                                  0.43   data required time
+-----------------------------------------------------------------------------
+                                  0.43   data required time
+                                 -2.53   data arrival time
+-----------------------------------------------------------------------------
+                                  2.09   slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15    0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.36 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.49    1.17    1.52 v _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.47                           net5 (net)
+                  1.51    0.10    1.63 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  1.56    1.26    2.89 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.08                           _016_ (net)
+                  1.56    0.01    2.90 ^ _110_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.90   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.17    0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.39 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    0.64   clock uncertainty
+                         -0.04    0.61   clock reconvergence pessimism
+                          0.15    0.75   library hold time
+                                  0.75   data required time
+-----------------------------------------------------------------------------
+                                  0.75   data required time
+                                 -2.90   data arrival time
+-----------------------------------------------------------------------------
+                                  2.15   slack (MET)
+
+
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.37 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.24    1.10    1.46 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.23                           net2 (net)
+                  1.25    0.04    1.50 ^ _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.24    0.08    1.58 v _059_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _027_ (net)
+                  0.24    0.00    1.58 v _060_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  2.62    1.48    3.06 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.19                           _005_ (net)
+                  2.62    0.04    3.10 ^ _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  3.10   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.17    0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.39 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    0.64   clock uncertainty
+                         -0.02    0.62   clock reconvergence pessimism
+                          0.29    0.91   library hold time
+                                  0.91   data required time
+-----------------------------------------------------------------------------
+                                  0.91   data required time
+                                 -3.10   data arrival time
+-----------------------------------------------------------------------------
+                                  2.19   slack (MET)
+
+
+Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.37 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.14    1.01    1.38 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.17                           net18 (net)
+                  1.14    0.04    1.42 v _070_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.43    0.34    1.76 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _033_ (net)
+                  0.43    0.00    1.76 ^ _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  1.22    0.78    2.54 v _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.13                           _010_ (net)
+                  1.22    0.03    2.58 v _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  2.58   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    0.65   clock uncertainty
+                         -0.04    0.62   clock reconvergence pessimism
+                         -0.24    0.38   library hold time
+                                  0.38   data required time
+-----------------------------------------------------------------------------
+                                  0.38   data required time
+                                 -2.58   data arrival time
+-----------------------------------------------------------------------------
+                                  2.20   slack (MET)
+
+
+Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.36 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.64    0.75    1.11 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.20                           net14 (net)
+                  0.66    0.05    1.16 v _061_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.40    0.33    1.49 ^ _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.02                           _028_ (net)
+                  0.40    0.00    1.50 ^ _064_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  1.69    1.05    2.54 v _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.19                           _006_ (net)
+                  1.69    0.04    2.58 v _100_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.58   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    0.65   clock uncertainty
+                         -0.04    0.61   clock reconvergence pessimism
+                         -0.32    0.29   library hold time
+                                  0.29   data required time
+-----------------------------------------------------------------------------
+                                  0.29   data required time
+                                 -2.58   data arrival time
+-----------------------------------------------------------------------------
+                                  2.29   slack (MET)
+
+
+Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.36 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  0.72    0.78    1.15 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.11                           net7 (net)
+                  0.73    0.02    1.17 v _089_/A3 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+                  0.50    0.47    1.64 ^ _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+     4    0.03                           _044_ (net)
+                  0.50    0.00    1.64 ^ _092_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  0.19    0.12    1.77 v _092_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     1    0.01                           _046_ (net)
+                  0.19    0.00    1.77 v _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  2.53    1.42    3.19 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.14                           _019_ (net)
+                  2.53    0.03    3.22 ^ _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  3.22   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.17    0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.39 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    0.64   clock uncertainty
+                         -0.02    0.62   clock reconvergence pessimism
+                          0.28    0.90   library hold time
+                                  0.90   data required time
+-----------------------------------------------------------------------------
+                                  0.90   data required time
+                                 -3.22   data arrival time
+-----------------------------------------------------------------------------
+                                  2.32   slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15    0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.36 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.66    0.75    1.11 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.20                           net21 (net)
+                  0.68    0.06    1.17 v _079_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.38    0.37    1.54 ^ _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.01                           _038_ (net)
+                  0.38    0.00    1.54 ^ _082_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  1.72    1.05    2.59 v _082_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.19                           _014_ (net)
+                  1.72    0.06    2.65 v _108_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.65   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.17    0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.39 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    0.64   clock uncertainty
+                         -0.04    0.61   clock reconvergence pessimism
+                         -0.33    0.27   library hold time
+                                  0.27   data required time
+-----------------------------------------------------------------------------
+                                  0.27   data required time
+                                 -2.65   data arrival time
+-----------------------------------------------------------------------------
+                                  2.38   slack (MET)
+
+
+Startpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.36 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.57    0.72    1.08 v _109_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     4    0.17                           net4 (net)
+                  0.58    0.04    1.13 v _083_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  0.29    0.32    1.45 ^ _083_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     2    0.01                           _041_ (net)
+                  0.29    0.00    1.45 ^ _084_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  2.01    1.22    2.66 v _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.23                           _015_ (net)
+                  2.01    0.07    2.74 v _109_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.74   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    0.65   clock uncertainty
+                         -0.04    0.62   clock reconvergence pessimism
+                         -0.40    0.22   library hold time
+                                  0.22   data required time
+-----------------------------------------------------------------------------
+                                  0.22   data required time
+                                 -2.74   data arrival time
+-----------------------------------------------------------------------------
+                                  2.52   slack (MET)
+
+
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15    0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.36 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.51    1.17    1.53 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.47                           net16 (net)
+                  1.53    0.10    1.62 v _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  2.55    1.78    3.40 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.14                           _008_ (net)
+                  2.56    0.02    3.42 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  3.42   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.17    0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.39 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    0.64   clock uncertainty
+                         -0.04    0.61   clock reconvergence pessimism
+                          0.28    0.89   library hold time
+                                  0.89   data required time
+-----------------------------------------------------------------------------
+                                  0.89   data required time
+                                 -3.42   data arrival time
+-----------------------------------------------------------------------------
+                                  2.53   slack (MET)
+
+
+Startpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15    0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.36 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.01    0.89    1.25 v _097_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     4    0.32                           net12 (net)
+                  1.05    0.10    1.35 v _056_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  0.45    0.54    1.89 ^ _056_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     2    0.02                           _026_ (net)
+                  0.45    0.00    1.89 ^ _057_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  1.46    0.94    2.83 v _057_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.16                           _003_ (net)
+                  1.47    0.05    2.88 v _097_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  2.88   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.17    0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.39 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    0.64   clock uncertainty
+                         -0.04    0.61   clock reconvergence pessimism
+                         -0.27    0.33   library hold time
+                                  0.33   data required time
+-----------------------------------------------------------------------------
+                                  0.33   data required time
+                                 -2.88   data arrival time
+-----------------------------------------------------------------------------
+                                  2.54   slack (MET)
+
+
+Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.37 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.28    1.10    1.46 v _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.20                           net19 (net)
+                  1.29    0.04    1.50 v _074_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  0.33    0.52    2.03 ^ _074_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     1    0.01                           _036_ (net)
+                  0.33    0.00    2.03 ^ _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  1.67    1.04    3.06 v _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.19                           _011_ (net)
+                  1.68    0.05    3.11 v _105_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  3.11   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    0.65   clock uncertainty
+                         -0.04    0.62   clock reconvergence pessimism
+                         -0.34    0.27   library hold time
+                                  0.27   data required time
+-----------------------------------------------------------------------------
+                                  0.27   data required time
+                                 -3.11   data arrival time
+-----------------------------------------------------------------------------
+                                  2.84   slack (MET)
+
+
+Startpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.37 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.15    1.52    1.89 ^ _103_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.41                           net17 (net)
+                  2.17    0.13    2.02 ^ _068_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.24    0.11    2.12 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _032_ (net)
+                  0.24    0.00    2.12 v _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  2.93    1.64    3.77 ^ _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.21                           _009_ (net)
+                  2.94    0.05    3.82 ^ _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  3.82   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    0.65   clock uncertainty
+                         -0.04    0.62   clock reconvergence pessimism
+                          0.34    0.95   library hold time
+                                  0.95   data required time
+-----------------------------------------------------------------------------
+                                  0.95   data required time
+                                 -3.82   data arrival time
+-----------------------------------------------------------------------------
+                                  2.87   slack (MET)
+
+
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.37 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.91    1.42    1.79 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.36                           net9 (net)
+                  1.94    0.12    1.90 ^ _050_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.30    0.15    2.05 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     2    0.02                           _022_ (net)
+                  0.30    0.00    2.05 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  3.13    1.76    3.81 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.22                           _001_ (net)
+                  3.14    0.06    3.87 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  3.87   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.17    0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.39 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    0.64   clock uncertainty
+                         -0.02    0.62   clock reconvergence pessimism
+                          0.36    0.98   library hold time
+                                  0.98   data required time
+-----------------------------------------------------------------------------
+                                  0.98   data required time
+                                 -3.87   data arrival time
+-----------------------------------------------------------------------------
+                                  2.88   slack (MET)
+
+
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.37 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.16    1.01    1.37 v _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.36                           net9 (net)
+                  1.19    0.09    1.47 v _048_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  4.15    2.51    3.98 ^ _048_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.23                           _000_ (net)
+                  4.15    0.05    4.03 ^ _094_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  4.03   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    0.65   clock uncertainty
+                         -0.04    0.62   clock reconvergence pessimism
+                          0.50    1.12   library hold time
+                                  1.12   data required time
+-----------------------------------------------------------------------------
+                                  1.12   data required time
+                                 -4.03   data arrival time
+-----------------------------------------------------------------------------
+                                  2.91   slack (MET)
+
+
+Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.37 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.20    1.02    1.38 v _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.37                           net20 (net)
+                  1.23    0.11    1.49 v _076_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  7.84    4.46    5.95 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.43                           _012_ (net)
+                  7.84    0.10    6.05 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  6.05   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    0.65   clock uncertainty
+                         -0.04    0.62   clock reconvergence pessimism
+                          1.01    1.63   library hold time
+                                  1.63   data required time
+-----------------------------------------------------------------------------
+                                  1.63   data required time
+                                 -6.05   data arrival time
+-----------------------------------------------------------------------------
+                                  4.43   slack (MET)
+
+
+Startpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[11] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.36 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.57    0.72    1.08 v _109_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     4    0.17                           net4 (net)
+                  0.57    0.03    1.11 v output4/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.23    0.35    1.47 v output4/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[11] (net)
+                  0.23    0.00    1.47 v io_out[11] (out)
+                                  1.47   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -1.47   data arrival time
+-----------------------------------------------------------------------------
+                                 14.22   slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[9] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15    0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.36 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.66    0.75    1.11 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.20                           net21 (net)
+                  0.66    0.04    1.15 v output21/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.23    0.37    1.52 v output21/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[9] (net)
+                  0.23    0.00    1.52 v io_out[9] (out)
+                                  1.52   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -1.52   data arrival time
+-----------------------------------------------------------------------------
+                                 14.27   slack (MET)
+
+
+Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[14] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.36 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  0.72    0.78    1.15 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.11                           net7 (net)
+                  0.72    0.02    1.17 v output7/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.23    0.38    1.55 v output7/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[14] (net)
+                  0.23    0.00    1.55 v io_out[14] (out)
+                                  1.55   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -1.55   data arrival time
+-----------------------------------------------------------------------------
+                                 14.30   slack (MET)
+
+
+Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[2] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.36 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.64    0.75    1.11 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.20                           net14 (net)
+                  0.67    0.07    1.18 v output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.23    0.37    1.55 v output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[2] (net)
+                  0.23    0.00    1.55 v io_out[2] (out)
+                                  1.55   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -1.55   data arrival time
+-----------------------------------------------------------------------------
+                                 14.30   slack (MET)
+
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[13] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.37 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.71    0.78    1.15 v _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.22                           net6 (net)
+                  0.73    0.07    1.22 v output6/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.23    0.38    1.60 v output6/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[13] (net)
+                  0.23    0.00    1.60 v io_out[13] (out)
+                                  1.60   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -1.60   data arrival time
+-----------------------------------------------------------------------------
+                                 14.35   slack (MET)
+
+
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.37 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.75    0.83    1.20 v _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.23                           net2 (net)
+                  0.76    0.02    1.22 v output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.23    0.38    1.60 v output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[0] (net)
+                  0.23    0.00    1.60 v io_out[0] (out)
+                                  1.60   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -1.60   data arrival time
+-----------------------------------------------------------------------------
+                                 14.35   slack (MET)
+
+
+Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[3] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15    0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.36 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.11    0.99    1.34 v _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.17                           net15 (net)
+                  1.11    0.05    1.40 v output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.24    0.43    1.83 v output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[3] (net)
+                  0.24    0.00    1.83 v io_out[3] (out)
+                                  1.83   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -1.83   data arrival time
+-----------------------------------------------------------------------------
+                                 14.58   slack (MET)
+
+
+Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[6] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.37 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.14    1.01    1.38 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.17                           net18 (net)
+                  1.14    0.02    1.40 v output18/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.24    0.43    1.83 v output18/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[6] (net)
+                  0.24    0.00    1.83 v io_out[6] (out)
+                                  1.83   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -1.83   data arrival time
+-----------------------------------------------------------------------------
+                                 14.58   slack (MET)
+
+
+Startpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[19] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15    0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.36 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.01    0.89    1.25 v _097_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     4    0.32                           net12 (net)
+                  1.10    0.16    1.41 v output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.24    0.43    1.83 v output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[19] (net)
+                  0.24    0.00    1.84 v io_out[19] (out)
+                                  1.84   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -1.84   data arrival time
+-----------------------------------------------------------------------------
+                                 14.59   slack (MET)
+
+
+Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[18] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.36 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.04    0.95    1.31 v _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.32                           net11 (net)
+                  1.09    0.12    1.44 v output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.24    0.43    1.86 v output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[18] (net)
+                  0.24    0.00    1.87 v io_out[18] (out)
+                                  1.87   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -1.87   data arrival time
+-----------------------------------------------------------------------------
+                                 14.62   slack (MET)
+
+
+Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[7] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.37 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.28    1.10    1.46 v _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.20                           net19 (net)
+                  1.29    0.03    1.50 v output19/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.25    0.45    1.95 v output19/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[7] (net)
+                  0.25    0.00    1.95 v io_out[7] (out)
+                                  1.95   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -1.95   data arrival time
+-----------------------------------------------------------------------------
+                                 14.70   slack (MET)
+
+
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.37 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.16    1.01    1.37 v _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.36                           net9 (net)
+                  1.22    0.14    1.51 v output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.24    0.44    1.95 v output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[16] (net)
+                  0.24    0.00    1.95 v io_out[16] (out)
+                                  1.95   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -1.95   data arrival time
+-----------------------------------------------------------------------------
+                                 14.70   slack (MET)
+
+
+Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[8] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.37 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.20    1.02    1.38 v _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.37                           net20 (net)
+                  1.26    0.15    1.53 v output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.25    0.45    1.98 v output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[8] (net)
+                  0.25    0.00    1.98 v io_out[8] (out)
+                                  1.98   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -1.98   data arrival time
+-----------------------------------------------------------------------------
+                                 14.73   slack (MET)
+
+
+Startpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[5] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16    0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.37 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.30    1.05    1.42 v _103_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.41                           net17 (net)
+                  1.38    0.18    1.60 v output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.25    0.46    2.06 v output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[5] (net)
+                  0.25    0.00    2.06 v io_out[5] (out)
+                                  2.06   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -2.06   data arrival time
+-----------------------------------------------------------------------------
+                                 14.81   slack (MET)
+
+
+Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[15] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15    0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.36 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.53    1.25    1.60 v _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.23                           net8 (net)
+                  1.53    0.00    1.60 v output8/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.25    0.48    2.08 v output8/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[15] (net)
+                  0.25    0.00    2.08 v io_out[15] (out)
+                                  2.08   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -2.08   data arrival time
+-----------------------------------------------------------------------------
+                                 14.83   slack (MET)
+
+
+Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[10] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15    0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.36 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.44    1.16    1.51 v _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.45                           net3 (net)
+                  1.50    0.17    1.68 v output3/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.25    0.47    2.15 v output3/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[10] (net)
+                  0.25    0.00    2.16 v io_out[10] (out)
+                                  2.16   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -2.16   data arrival time
+-----------------------------------------------------------------------------
+                                 14.91   slack (MET)
+
+
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[4] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15    0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.36 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.51    1.17    1.53 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.47                           net16 (net)
+                  1.60    0.19    1.72 v output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.25    0.48    2.20 v output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[4] (net)
+                  0.25    0.00    2.20 v io_out[4] (out)
+                                  2.20   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -2.20   data arrival time
+-----------------------------------------------------------------------------
+                                 14.95   slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[12] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15    0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.36 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.49    1.17    1.52 v _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.47                           net5 (net)
+                  1.58    0.20    1.73 v output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.25    0.48    2.21 v output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[12] (net)
+                  0.25    0.00    2.21 v io_out[12] (out)
+                                  2.21   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -2.21   data arrival time
+-----------------------------------------------------------------------------
+                                 14.96   slack (MET)
+
+
+Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15    0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.36 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.69    1.36    1.71 v _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.52                           net13 (net)
+                  1.70    0.06    1.77 v output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.26    0.49    2.27 v output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[1] (net)
+                  0.26    0.00    2.27 v io_out[1] (out)
+                                  2.27   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -2.27   data arrival time
+-----------------------------------------------------------------------------
+                                 15.02   slack (MET)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[17] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15    0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15    0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.36 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.69    1.29    1.64 v _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.53                           net10 (net)
+                  1.76    0.19    1.83 v output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.26    0.50    2.33 v output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[17] (net)
+                  0.26    0.00    2.33 v io_out[17] (out)
+                                  2.33   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                        -13.00  -12.75   output external delay
+                                -12.75   data required time
+-----------------------------------------------------------------------------
+                                -12.75   data required time
+                                 -2.33   data arrival time
+-----------------------------------------------------------------------------
+                                 15.08   slack (MET)
+
+
+min_report_end
+max_report
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+
+======================= Slowest Corner ===================================
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  1.05    0.40   13.40 ^ wb_rst_i (in)
+     2    0.01                           wb_rst_i (net)
+                  1.05    0.00   13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                 15.05   10.77   24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                 15.05    0.03   24.20 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  7.05    8.58   32.77 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.17                           _020_ (net)
+                  7.05    0.02   32.79 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                115.68   78.45  111.25 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.43                           _012_ (net)
+                115.68    0.12  111.36 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                111.36   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78   69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00   69.02 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   68.77   clock uncertainty
+                          0.00   68.77   clock reconvergence pessimism
+                         -5.79   62.98   library setup time
+                                 62.98   data required time
+-----------------------------------------------------------------------------
+                                 62.98   data required time
+                               -111.36   data arrival time
+-----------------------------------------------------------------------------
+                                -48.38   slack (VIOLATED)
+
+
+Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.31 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 28.12   25.04   29.35 ^ _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.45                           net3 (net)
+                 28.12    0.13   29.48 ^ _080_/A3 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+                  8.98    9.01   38.49 v _080_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+     4    0.03                           _039_ (net)
+                  8.98    0.00   38.49 v _083_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  3.35    8.55   47.04 v _083_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     2    0.01                           _041_ (net)
+                  3.35    0.00   47.04 v _084_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 60.94   41.50   88.53 ^ _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.23                           _015_ (net)
+                 60.94    0.08   88.61 ^ _109_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 88.61   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78   69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00   69.02 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   68.77   clock uncertainty
+                          0.24   69.00   clock reconvergence pessimism
+                         -5.13   63.87   library setup time
+                                 63.87   data required time
+-----------------------------------------------------------------------------
+                                 63.87   data required time
+                                -88.61   data arrival time
+-----------------------------------------------------------------------------
+                                -24.75   slack (VIOLATED)
+
+
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.32 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 29.73   26.04   30.35 ^ _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.47                           net16 (net)
+                 29.73    0.14   30.49 ^ _071_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+                  9.32    9.68   40.17 v _071_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+     2    0.03                           _034_ (net)
+                  9.32    0.00   40.17 v _074_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  5.61    8.80   48.97 v _074_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     1    0.01                           _036_ (net)
+                  5.61    0.00   48.97 v _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 50.53   35.59   84.55 ^ _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.19                           _011_ (net)
+                 50.53    0.05   84.61 ^ _105_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 84.61   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78   69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00   69.02 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.25   68.77   clock uncertainty
+                          0.24   69.00   clock reconvergence pessimism
+                         -4.87   64.13   library setup time
+                                 64.13   data required time
+-----------------------------------------------------------------------------
+                                 64.13   data required time
+                                -84.61   data arrival time
+-----------------------------------------------------------------------------
+                                -20.47   slack (VIOLATED)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.31 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 33.05   28.16   32.48 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.53                           net10 (net)
+                 33.05    0.17   32.65 ^ _050_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  7.05    7.55   40.20 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     2    0.02                           _022_ (net)
+                  7.05    0.00   40.20 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                 60.98   43.38   83.58 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.22                           _001_ (net)
+                 60.98    0.07   83.65 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 83.65   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67   68.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00   68.90 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   68.65   clock uncertainty
+                          0.41   69.06   clock reconvergence pessimism
+                         -5.18   63.88   library setup time
+                                 63.88   data required time
+-----------------------------------------------------------------------------
+                                 63.88   data required time
+                                -83.65   data arrival time
+-----------------------------------------------------------------------------
+                                -19.76   slack (VIOLATED)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.31 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 33.05   28.16   32.48 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.53                           net10 (net)
+                 33.05    0.17   32.65 ^ _053_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+                  6.70    7.54   40.19 v _053_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+     2    0.01                           _024_ (net)
+                  6.70    0.00   40.19 v _056_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  5.75    7.97   48.15 v _056_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     2    0.02                           _026_ (net)
+                  5.75    0.00   48.15 v _057_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 44.17   31.50   79.65 ^ _057_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.16                           _003_ (net)
+                 44.17    0.05   79.71 ^ _097_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 79.71   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67   68.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00   68.90 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   68.65   clock uncertainty
+                          0.41   69.06   clock reconvergence pessimism
+                         -4.98   64.08   library setup time
+                                 64.08   data required time
+-----------------------------------------------------------------------------
+                                 64.08   data required time
+                                -79.71   data arrival time
+-----------------------------------------------------------------------------
+                                -15.63   slack (VIOLATED)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  1.05    0.40   13.40 ^ wb_rst_i (in)
+     2    0.01                           wb_rst_i (net)
+                  1.05    0.00   13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                 15.05   10.77   24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                 15.05    0.03   24.20 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  8.71    9.44   33.63 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  8.71    0.01   33.64 ^ _068_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  5.32    3.36   37.00 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _032_ (net)
+                  5.32    0.00   37.00 v _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                 57.10   40.20   77.20 ^ _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.21                           _009_ (net)
+                 57.10    0.06   77.26 ^ _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 77.26   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78   69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00   69.02 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   68.77   clock uncertainty
+                          0.00   68.77   clock reconvergence pessimism
+                         -5.09   63.68   library setup time
+                                 63.68   data required time
+-----------------------------------------------------------------------------
+                                 63.68   data required time
+                                -77.26   data arrival time
+-----------------------------------------------------------------------------
+                                -13.58   slack (VIOLATED)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  1.05    0.40   13.40 ^ wb_rst_i (in)
+     2    0.01                           wb_rst_i (net)
+                  1.05    0.00   13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                 15.05   10.77   24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                 15.05    0.03   24.20 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  7.05    8.58   32.77 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.17                           _020_ (net)
+                  7.05    0.02   32.79 v _048_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 60.93   42.88   75.68 ^ _048_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.23                           _000_ (net)
+                 60.93    0.05   75.73 ^ _094_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 75.73   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78   69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00   69.02 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   68.77   clock uncertainty
+                          0.00   68.77   clock reconvergence pessimism
+                         -5.13   63.63   library setup time
+                                 63.63   data required time
+-----------------------------------------------------------------------------
+                                 63.63   data required time
+                                -75.73   data arrival time
+-----------------------------------------------------------------------------
+                                -12.10   slack (VIOLATED)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.32 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 29.21   25.72   30.03 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.46                           net5 (net)
+                 29.21    0.14   30.17 ^ _089_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+                  9.48    9.92   40.10 v _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+     4    0.03                           _044_ (net)
+                  9.48    0.00   40.10 v _092_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  6.14    8.82   48.92 v _092_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     1    0.01                           _046_ (net)
+                  6.14    0.00   48.92 v _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 37.15   27.08   76.00 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.14                           _019_ (net)
+                 37.15    0.04   76.04 ^ _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 76.04   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67   68.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00   68.90 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.25   68.65   clock uncertainty
+                          0.41   69.07   clock reconvergence pessimism
+                         -4.76   64.30   library setup time
+                                 64.30   data required time
+-----------------------------------------------------------------------------
+                                 64.30   data required time
+                                -76.04   data arrival time
+-----------------------------------------------------------------------------
+                                -11.73   slack (VIOLATED)
+
+
+Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.32 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 32.73   28.04   32.35 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.52                           net13 (net)
+                 32.73    0.08   32.43 ^ _061_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  6.02    7.06   39.49 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.02                           _028_ (net)
+                  6.02    0.00   39.49 v _064_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 50.62   35.83   75.33 ^ _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.19                           _006_ (net)
+                 50.62    0.04   75.37 ^ _100_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 75.37   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78   69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00   69.02 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   68.77   clock uncertainty
+                          0.24   69.00   clock reconvergence pessimism
+                         -5.01   63.99   library setup time
+                                 63.99   data required time
+-----------------------------------------------------------------------------
+                                 63.99   data required time
+                                -75.37   data arrival time
+-----------------------------------------------------------------------------
+                                -11.38   slack (VIOLATED)
+
+
+Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.32 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 32.73   28.04   32.35 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.52                           net13 (net)
+                 32.73    0.08   32.43 ^ _059_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  5.40    5.49   37.92 v _059_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _027_ (net)
+                  5.40    0.00   37.92 v _060_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                 50.93   36.24   74.16 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.19                           _005_ (net)
+                 50.93    0.04   74.20 ^ _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 74.20   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67   68.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00   68.90 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   68.65   clock uncertainty
+                          0.41   69.06   clock reconvergence pessimism
+                         -5.06   64.00   library setup time
+                                 64.00   data required time
+-----------------------------------------------------------------------------
+                                 64.00   data required time
+                                -74.20   data arrival time
+-----------------------------------------------------------------------------
+                                -10.20   slack (VIOLATED)
+
+
+Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.31 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 28.12   25.04   29.35 ^ _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.45                           net3 (net)
+                 28.12    0.14   29.49 ^ _079_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  5.77    6.39   35.88 v _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.01                           _038_ (net)
+                  5.77    0.00   35.88 v _082_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 51.57   36.33   72.20 ^ _082_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.19                           _014_ (net)
+                 51.57    0.06   72.27 ^ _108_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 72.27   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67   68.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00   68.90 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   68.65   clock uncertainty
+                          0.41   69.06   clock reconvergence pessimism
+                         -5.07   63.99   library setup time
+                                 63.99   data required time
+-----------------------------------------------------------------------------
+                                 63.99   data required time
+                                -72.27   data arrival time
+-----------------------------------------------------------------------------
+                                 -8.27   slack (VIOLATED)
+
+
+Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.32 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 32.73   28.04   32.35 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.52                           net13 (net)
+                 32.73    0.08   32.43 ^ _062_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+                  7.78    9.04   41.48 v _062_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+     4    0.02                           _029_ (net)
+                  7.78    0.00   41.48 v _065_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  4.11    7.73   49.21 v _065_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     1    0.01                           _031_ (net)
+                  4.11    0.00   49.21 v _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 24.15   17.86   67.07 ^ _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.09                           _007_ (net)
+                 24.15    0.02   67.09 ^ _101_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 67.09   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67   68.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00   68.90 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.25   68.65   clock uncertainty
+                          0.41   69.06   clock reconvergence pessimism
+                         -4.62   64.45   library setup time
+                                 64.45   data required time
+-----------------------------------------------------------------------------
+                                 64.45   data required time
+                                -67.09   data arrival time
+-----------------------------------------------------------------------------
+                                 -2.64   slack (VIOLATED)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  1.05    0.40   13.40 ^ wb_rst_i (in)
+     2    0.01                           wb_rst_i (net)
+                  1.05    0.00   13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                 15.05   10.77   24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                 15.05    0.03   24.20 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  8.71    9.44   33.63 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  8.71    0.01   33.64 ^ _077_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  4.19    3.14   36.78 v _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.00                           _037_ (net)
+                  4.19    0.00   36.78 v _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                 37.02   26.77   63.54 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.13                           _013_ (net)
+                 37.02    0.04   63.58 ^ _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 63.58   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67   68.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00   68.90 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   68.65   clock uncertainty
+                          0.00   68.65   clock reconvergence pessimism
+                         -4.90   63.75   library setup time
+                                 63.75   data required time
+-----------------------------------------------------------------------------
+                                 63.75   data required time
+                                -63.58   data arrival time
+-----------------------------------------------------------------------------
+                                  0.17   slack (MET)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.31 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 33.05   28.16   32.48 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.53                           net10 (net)
+                 33.05    0.16   32.64 ^ _052_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  5.92    6.89   39.53 v _052_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.02                           _023_ (net)
+                  5.92    0.00   39.53 v _055_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 31.46   23.31   62.85 ^ _055_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.12                           _002_ (net)
+                 31.46    0.03   62.88 ^ _096_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 62.88   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78   69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00   69.02 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   68.77   clock uncertainty
+                          0.24   69.00   clock reconvergence pessimism
+                         -4.78   64.22   library setup time
+                                 64.22   data required time
+-----------------------------------------------------------------------------
+                                 64.22   data required time
+                                -62.88   data arrival time
+-----------------------------------------------------------------------------
+                                  1.34   slack (MET)
+
+
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.32 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 29.73   26.04   30.35 ^ _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.47                           net16 (net)
+                 29.73    0.14   30.49 ^ _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  5.82    5.37   35.87 v _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.01                           _033_ (net)
+                  5.82    0.00   35.87 v _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 36.53   26.57   62.44 ^ _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.13                           _010_ (net)
+                 36.53    0.04   62.48 ^ _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 62.48   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78   69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00   69.02 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.25   68.77   clock uncertainty
+                          0.24   69.00   clock reconvergence pessimism
+                         -4.71   64.29   library setup time
+                                 64.29   data required time
+-----------------------------------------------------------------------------
+                                 64.29   data required time
+                                -62.48   data arrival time
+-----------------------------------------------------------------------------
+                                  1.82   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  1.05    0.40   13.40 ^ wb_rst_i (in)
+     2    0.01                           wb_rst_i (net)
+                  1.05    0.00   13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                 15.05   10.77   24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                 15.05    0.03   24.20 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  7.05    8.58   32.77 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.17                           _020_ (net)
+                  7.05    0.03   32.80 v _067_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 37.40   27.60   60.40 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.14                           _008_ (net)
+                 37.40    0.02   60.42 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 60.42   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67   68.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00   68.90 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   68.65   clock uncertainty
+                          0.00   68.65   clock reconvergence pessimism
+                         -4.90   63.75   library setup time
+                                 63.75   data required time
+-----------------------------------------------------------------------------
+                                 63.75   data required time
+                                -60.42   data arrival time
+-----------------------------------------------------------------------------
+                                  3.33   slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.32 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 29.21   25.72   30.03 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.46                           net5 (net)
+                 29.21    0.15   30.18 ^ _088_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  6.51    6.41   36.59 v _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.01                           _043_ (net)
+                  6.51    0.00   36.59 v _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 26.61   20.41   57.00 ^ _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.10                           _018_ (net)
+                 26.61    0.02   57.02 ^ _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 57.02   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78   69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00   69.02 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.25   68.77   clock uncertainty
+                          0.24   69.00   clock reconvergence pessimism
+                         -4.60   64.41   library setup time
+                                 64.41   data required time
+-----------------------------------------------------------------------------
+                                 64.41   data required time
+                                -57.02   data arrival time
+-----------------------------------------------------------------------------
+                                  7.39   slack (MET)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[17] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.31 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 33.05   28.16   32.48 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.53                           net10 (net)
+                 33.05    0.21   32.69 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.90    9.24   41.93 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[17] (net)
+                  2.90    0.00   41.93 ^ io_out[17] (out)
+                                 41.93   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -41.93   data arrival time
+-----------------------------------------------------------------------------
+                                  9.82   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  1.05    0.40   13.40 ^ wb_rst_i (in)
+     2    0.01                           wb_rst_i (net)
+                  1.05    0.00   13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                 15.05   10.77   24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                 15.05    0.03   24.20 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  8.71    9.44   33.63 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  8.71    0.01   33.64 ^ _086_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  5.19    3.32   36.96 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _042_ (net)
+                  5.19    0.00   36.96 v _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                 21.59   17.15   54.11 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.08                           _017_ (net)
+                 21.59    0.02   54.13 ^ _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 54.13   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78   69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00   69.02 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   68.77   clock uncertainty
+                          0.00   68.77   clock reconvergence pessimism
+                         -4.66   64.10   library setup time
+                                 64.10   data required time
+-----------------------------------------------------------------------------
+                                 64.10   data required time
+                                -54.13   data arrival time
+-----------------------------------------------------------------------------
+                                  9.97   slack (MET)
+
+
+Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.32 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 32.73   28.04   32.35 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.52                           net13 (net)
+                 32.73    0.07   32.42 ^ output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.86    9.16   41.58 ^ output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[1] (net)
+                  2.86    0.00   41.58 ^ io_out[1] (out)
+                                 41.58   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -41.58   data arrival time
+-----------------------------------------------------------------------------
+                                 10.17   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  1.05    0.40   13.40 ^ wb_rst_i (in)
+     2    0.01                           wb_rst_i (net)
+                  1.05    0.00   13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                 15.05   10.77   24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                 15.05    0.03   24.20 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  7.05    8.58   32.77 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.17                           _020_ (net)
+                  7.05    0.03   32.80 v _058_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 24.96   19.50   52.30 ^ _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.09                           _004_ (net)
+                 24.96    0.02   52.32 ^ _098_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 52.32   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78   69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00   69.02 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   68.77   clock uncertainty
+                          0.00   68.77   clock reconvergence pessimism
+                         -4.70   64.06   library setup time
+                                 64.06   data required time
+-----------------------------------------------------------------------------
+                                 64.06   data required time
+                                -52.32   data arrival time
+-----------------------------------------------------------------------------
+                                 11.74   slack (MET)
+
+
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[4] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.32 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 29.73   26.04   30.35 ^ _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.47                           net16 (net)
+                 29.73    0.22   30.57 ^ output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.90    8.77   39.34 ^ output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[4] (net)
+                  2.90    0.00   39.34 ^ io_out[4] (out)
+                                 39.34   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -39.34   data arrival time
+-----------------------------------------------------------------------------
+                                 12.41   slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[12] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.32 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 29.21   25.72   30.03 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.46                           net5 (net)
+                 29.22    0.23   30.26 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.82    8.72   38.98 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[12] (net)
+                  2.82    0.00   38.99 ^ io_out[12] (out)
+                                 38.99   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -38.99   data arrival time
+-----------------------------------------------------------------------------
+                                 12.76   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  1.05    0.40   13.40 ^ wb_rst_i (in)
+     2    0.01                           wb_rst_i (net)
+                  1.05    0.00   13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                 15.05   10.77   24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                 15.05    0.03   24.20 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  7.05    8.58   32.77 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.17                           _020_ (net)
+                  7.05    0.03   32.80 v _085_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 22.83   18.12   50.92 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.08                           _016_ (net)
+                 22.83    0.01   50.94 ^ _110_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 50.94   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.67   68.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00   68.90 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   68.65   clock uncertainty
+                          0.00   68.65   clock reconvergence pessimism
+                         -4.73   63.92   library setup time
+                                 63.92   data required time
+-----------------------------------------------------------------------------
+                                 63.92   data required time
+                                -50.94   data arrival time
+-----------------------------------------------------------------------------
+                                 12.99   slack (MET)
+
+
+Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[15] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.32 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                 29.50   25.54   29.85 ^ _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.23                           net8 (net)
+                 29.50    0.00   29.86 ^ output8/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.91    8.76   38.61 ^ output8/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[15] (net)
+                  2.91    0.00   38.61 ^ io_out[15] (out)
+                                 38.61   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -38.61   data arrival time
+-----------------------------------------------------------------------------
+                                 13.14   slack (MET)
+
+
+Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[10] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.31 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 28.12   25.04   29.35 ^ _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.45                           net3 (net)
+                 28.12    0.19   29.54 ^ output3/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.84    8.60   38.15 ^ output3/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[10] (net)
+                  2.84    0.00   38.15 ^ io_out[10] (out)
+                                 38.15   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -38.15   data arrival time
+-----------------------------------------------------------------------------
+                                 13.60   slack (MET)
+
+
+Startpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[5] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 25.58   23.46   27.90 ^ _103_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.41                           net17 (net)
+                 25.59    0.20   28.11 ^ output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.79    8.27   36.38 ^ output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[5] (net)
+                  2.79    0.00   36.38 ^ io_out[5] (out)
+                                 36.38   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -36.38   data arrival time
+-----------------------------------------------------------------------------
+                                 15.37   slack (MET)
+
+
+Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[7] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                 24.78   22.56   27.00 ^ _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.20                           net19 (net)
+                 24.78    0.04   27.04 ^ output19/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.87    8.16   35.20 ^ output19/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[7] (net)
+                  2.87    0.00   35.20 ^ io_out[7] (out)
+                                 35.20   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -35.20   data arrival time
+-----------------------------------------------------------------------------
+                                 16.55   slack (MET)
+
+
+Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[8] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 23.49   22.15   26.60 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.37                           net20 (net)
+                 23.50    0.17   26.76 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.86    8.00   34.77 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[8] (net)
+                  2.86    0.00   34.77 ^ io_out[8] (out)
+                                 34.77   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -34.77   data arrival time
+-----------------------------------------------------------------------------
+                                 16.98   slack (MET)
+
+
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 22.74   21.68   26.12 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.36                           net9 (net)
+                 22.74    0.15   26.28 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.83    7.90   34.18 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[16] (net)
+                  2.83    0.00   34.18 ^ io_out[16] (out)
+                                 34.18   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -34.18   data arrival time
+-----------------------------------------------------------------------------
+                                 17.57   slack (MET)
+
+
+Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[6] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                 21.90   20.72   25.16 ^ _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.17                           net18 (net)
+                 21.90    0.03   25.19 ^ output18/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.84    7.80   32.99 ^ output18/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[6] (net)
+                  2.84    0.00   32.99 ^ io_out[6] (out)
+                                 32.99   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -32.99   data arrival time
+-----------------------------------------------------------------------------
+                                 18.76   slack (MET)
+
+
+Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[3] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.31 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                 21.37   20.31   24.63 ^ _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.17                           net15 (net)
+                 21.37    0.06   24.69 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.83    7.74   32.42 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[3] (net)
+                  2.83    0.00   32.42 ^ io_out[3] (out)
+                                 32.42   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -32.42   data arrival time
+-----------------------------------------------------------------------------
+                                 19.33   slack (MET)
+
+
+Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[18] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 20.37   20.18   24.62 ^ _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.32                           net11 (net)
+                 20.37    0.14   24.76 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.81    7.60   32.36 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[18] (net)
+                  2.81    0.00   32.36 ^ io_out[18] (out)
+                                 32.36   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -32.36   data arrival time
+-----------------------------------------------------------------------------
+                                 19.39   slack (MET)
+
+
+Startpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[19] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.31 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 19.98   19.84   24.16 ^ _097_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     4    0.32                           net12 (net)
+                 19.99    0.18   24.34 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.74    7.57   31.91 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[19] (net)
+                  2.74    0.00   31.91 ^ io_out[19] (out)
+                                 31.91   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -31.91   data arrival time
+-----------------------------------------------------------------------------
+                                 19.84   slack (MET)
+
+
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 14.64   16.57   21.01 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.23                           net2 (net)
+                 14.64    0.02   21.03 ^ output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.78    6.79   27.82 ^ output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[0] (net)
+                  2.78    0.00   27.82 ^ io_out[0] (out)
+                                 27.82   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -27.82   data arrival time
+-----------------------------------------------------------------------------
+                                 23.93   slack (MET)
+
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[13] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 13.88   16.06   20.50 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.22                           net6 (net)
+                 13.88    0.08   20.57 ^ output6/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.75    6.66   27.23 ^ output6/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[13] (net)
+                  2.75    0.00   27.24 ^ io_out[13] (out)
+                                 27.24   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -27.24   data arrival time
+-----------------------------------------------------------------------------
+                                 24.51   slack (MET)
+
+
+Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[14] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                 13.98   15.67   20.11 ^ _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.11                           net7 (net)
+                 13.98    0.02   20.13 ^ output7/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.70    6.70   26.83 ^ output7/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[14] (net)
+                  2.70    0.00   26.83 ^ io_out[14] (out)
+                                 26.83   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -26.83   data arrival time
+-----------------------------------------------------------------------------
+                                 24.92   slack (MET)
+
+
+Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[2] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 12.52   15.20   19.64 ^ _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.20                           net14 (net)
+                 12.53    0.08   19.72 ^ output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.75    6.42   26.14 ^ output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[2] (net)
+                  2.75    0.00   26.14 ^ io_out[2] (out)
+                                 26.14   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -26.14   data arrival time
+-----------------------------------------------------------------------------
+                                 25.61   slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[9] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.83    1.84    4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.83    0.00    4.31 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 12.76   15.29   19.60 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.20                           net21 (net)
+                 12.76    0.05   19.65 ^ output21/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.74    6.45   26.10 ^ output21/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[9] (net)
+                  2.74    0.00   26.10 ^ io_out[9] (out)
+                                 26.10   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -26.10   data arrival time
+-----------------------------------------------------------------------------
+                                 25.65   slack (MET)
+
+
+Startpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[11] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  1.13    0.55    0.55 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00    0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.92    2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00    2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.97    4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00    4.44 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                 11.06   14.27   18.71 ^ _109_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     4    0.17                           net4 (net)
+                 11.06    0.03   18.75 ^ output4/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  2.73    6.14   24.89 ^ output4/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[11] (net)
+                  2.73    0.00   24.89 ^ io_out[11] (out)
+                                 24.89   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                -24.89   data arrival time
+-----------------------------------------------------------------------------
+                                 26.86   slack (MET)
+
+
+
+======================= Typical Corner ===================================
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  1.62    1.40   16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  1.63    0.02   16.44 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 18.95   11.96   28.41 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.43                           _012_ (net)
+                 18.95    0.12   28.52 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 28.52   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34   65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00   65.77 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.52   clock uncertainty
+                          0.00   65.52   clock reconvergence pessimism
+                          1.23   66.75   library setup time
+                                 66.75   data required time
+-----------------------------------------------------------------------------
+                                 66.75   data required time
+                                -28.52   data arrival time
+-----------------------------------------------------------------------------
+                                 38.23   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  1.63    1.30   16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  1.63    0.00   16.32 ^ _050_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  1.44    0.51   16.84 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     2    0.02                           _022_ (net)
+                  1.44    0.00   16.84 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                 10.03    6.54   23.38 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.22                           _001_ (net)
+                 10.03    0.07   23.45 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 23.45   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32   65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00   65.75 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.50   clock uncertainty
+                          0.00   65.50   clock reconvergence pessimism
+                          0.26   65.77   library setup time
+                                 65.77   data required time
+-----------------------------------------------------------------------------
+                                 65.77   data required time
+                                -23.45   data arrival time
+-----------------------------------------------------------------------------
+                                 42.32   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  1.62    1.40   16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  1.62    0.02   16.44 v _084_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 10.00    6.59   23.02 ^ _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.23                           _015_ (net)
+                 10.00    0.08   23.10 ^ _109_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 23.10   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34   65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00   65.77 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.52   clock uncertainty
+                          0.00   65.52   clock reconvergence pessimism
+                          0.27   65.79   library setup time
+                                 65.79   data required time
+-----------------------------------------------------------------------------
+                                 65.79   data required time
+                                -23.10   data arrival time
+-----------------------------------------------------------------------------
+                                 42.69   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  1.62    1.40   16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  1.63    0.02   16.45 v _048_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  9.99    6.50   22.95 ^ _048_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.23                           _000_ (net)
+                  9.99    0.05   23.00 ^ _094_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 23.00   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34   65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00   65.77 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.52   clock uncertainty
+                          0.00   65.52   clock reconvergence pessimism
+                          0.27   65.79   library setup time
+                                 65.79   data required time
+-----------------------------------------------------------------------------
+                                 65.79   data required time
+                                -23.00   data arrival time
+-----------------------------------------------------------------------------
+                                 42.79   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  1.63    1.30   16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  1.63    0.01   16.33 ^ _068_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  1.03    0.36   16.69 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _032_ (net)
+                  1.03    0.00   16.69 v _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  9.40    6.08   22.77 ^ _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.21                           _009_ (net)
+                  9.40    0.06   22.83 ^ _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 22.83   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34   65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00   65.77 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.52   clock uncertainty
+                          0.00   65.52   clock reconvergence pessimism
+                          0.20   65.73   library setup time
+                                 65.73   data required time
+-----------------------------------------------------------------------------
+                                 65.73   data required time
+                                -22.83   data arrival time
+-----------------------------------------------------------------------------
+                                 42.90   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  1.63    1.30   16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  1.63    0.01   16.33 ^ _059_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  1.17    0.36   16.69 v _059_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _027_ (net)
+                  1.17    0.00   16.69 v _060_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  8.39    5.50   22.18 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.19                           _005_ (net)
+                  8.39    0.04   22.22 ^ _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 22.22   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32   65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00   65.75 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.50   clock uncertainty
+                          0.00   65.50   clock reconvergence pessimism
+                          0.09   65.59   library setup time
+                                 65.59   data required time
+-----------------------------------------------------------------------------
+                                 65.59   data required time
+                                -22.22   data arrival time
+-----------------------------------------------------------------------------
+                                 43.37   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  1.63    1.30   16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  1.63    0.01   16.33 ^ _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+                  0.67    0.50   16.82 v _063_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+     2    0.02                           _030_ (net)
+                  0.67    0.00   16.82 v _064_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  8.31    5.29   22.12 ^ _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.19                           _006_ (net)
+                  8.31    0.04   22.16 ^ _100_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 22.16   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34   65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00   65.77 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.52   clock uncertainty
+                          0.00   65.52   clock reconvergence pessimism
+                          0.09   65.61   library setup time
+                                 65.61   data required time
+-----------------------------------------------------------------------------
+                                 65.61   data required time
+                                -22.16   data arrival time
+-----------------------------------------------------------------------------
+                                 43.45   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  1.63    1.30   16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  1.63    0.00   16.32 ^ _081_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+                  0.48    0.29   16.61 v _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+     1    0.01                           _040_ (net)
+                  0.48    0.00   16.62 v _082_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  8.46    5.34   21.95 ^ _082_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.19                           _014_ (net)
+                  8.47    0.06   22.02 ^ _108_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 22.02   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32   65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00   65.75 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.50   clock uncertainty
+                          0.00   65.50   clock reconvergence pessimism
+                          0.10   65.60   library setup time
+                                 65.60   data required time
+-----------------------------------------------------------------------------
+                                 65.60   data required time
+                                -22.02   data arrival time
+-----------------------------------------------------------------------------
+                                 43.58   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  1.62    1.40   16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  1.63    0.03   16.45 v _075_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  8.29    5.56   22.00 ^ _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.19                           _011_ (net)
+                  8.29    0.05   22.06 ^ _105_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 22.06   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34   65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00   65.77 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.25   65.52   clock uncertainty
+                          0.00   65.52   clock reconvergence pessimism
+                          0.12   65.64   library setup time
+                                 65.64   data required time
+-----------------------------------------------------------------------------
+                                 65.64   data required time
+                                -22.06   data arrival time
+-----------------------------------------------------------------------------
+                                 43.58   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  1.62    1.40   16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  1.62    0.02   16.44 v _057_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  7.25    4.92   21.36 ^ _057_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.16                           _003_ (net)
+                  7.25    0.05   21.41 ^ _097_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 21.41   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32   65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00   65.75 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.50   clock uncertainty
+                          0.00   65.50   clock reconvergence pessimism
+                         -0.03   65.47   library setup time
+                                 65.47   data required time
+-----------------------------------------------------------------------------
+                                 65.47   data required time
+                                -21.41   data arrival time
+-----------------------------------------------------------------------------
+                                 44.06   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  1.63    1.30   16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  1.63    0.01   16.33 ^ _077_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.82    0.31   16.64 v _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _037_ (net)
+                  0.82    0.00   16.64 v _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  6.11    4.03   20.67 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.13                           _013_ (net)
+                  6.11    0.04   20.71 ^ _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 20.71   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32   65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00   65.75 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.50   clock uncertainty
+                          0.00   65.50   clock reconvergence pessimism
+                         -0.15   65.35   library setup time
+                                 65.35   data required time
+-----------------------------------------------------------------------------
+                                 65.35   data required time
+                                -20.71   data arrival time
+-----------------------------------------------------------------------------
+                                 44.64   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  1.62    1.40   16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  1.63    0.03   16.45 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  6.10    4.22   20.67 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.14                           _019_ (net)
+                  6.10    0.04   20.71 ^ _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 20.71   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32   65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00   65.75 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.25   65.50   clock uncertainty
+                          0.00   65.50   clock reconvergence pessimism
+                         -0.12   65.38   library setup time
+                                 65.38   data required time
+-----------------------------------------------------------------------------
+                                 65.38   data required time
+                                -20.71   data arrival time
+-----------------------------------------------------------------------------
+                                 44.68   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  1.62    1.40   16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  1.63    0.03   16.45 v _067_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  6.14    4.15   20.60 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.14                           _008_ (net)
+                  6.14    0.02   20.63 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 20.63   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32   65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00   65.75 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.50   clock uncertainty
+                          0.00   65.50   clock reconvergence pessimism
+                         -0.15   65.36   library setup time
+                                 65.36   data required time
+-----------------------------------------------------------------------------
+                                 65.36   data required time
+                                -20.63   data arrival time
+-----------------------------------------------------------------------------
+                                 44.73   slack (MET)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[17] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  6.07    4.75    5.58 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.53                           net10 (net)
+                  6.09    0.21    5.79 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.58    1.09    6.88 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[17] (net)
+                  0.58    0.00    6.88 ^ io_out[17] (out)
+                                  6.88   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -6.88   data arrival time
+-----------------------------------------------------------------------------
+                                 44.87   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  1.63    1.30   16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  1.63    0.01   16.33 ^ _072_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+                  0.46    0.26   16.59 v _072_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+     1    0.01                           _035_ (net)
+                  0.46    0.00   16.59 v _073_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  6.00    3.84   20.43 ^ _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.13                           _010_ (net)
+                  6.00    0.04   20.46 ^ _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 20.46   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34   65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00   65.77 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.25   65.52   clock uncertainty
+                          0.00   65.52   clock reconvergence pessimism
+                         -0.12   65.40   library setup time
+                                 65.40   data required time
+-----------------------------------------------------------------------------
+                                 65.40   data required time
+                                -20.46   data arrival time
+-----------------------------------------------------------------------------
+                                 44.94   slack (MET)
+
+
+Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  6.02    4.79    5.62 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.52                           net13 (net)
+                  6.02    0.07    5.69 ^ output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.57    1.08    6.77 ^ output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[1] (net)
+                  0.57    0.00    6.77 ^ io_out[1] (out)
+                                  6.77   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -6.77   data arrival time
+-----------------------------------------------------------------------------
+                                 44.98   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  1.63    1.30   16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  1.63    0.00   16.32 ^ _054_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+                  0.62    0.44   16.77 v _054_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+     2    0.01                           _025_ (net)
+                  0.62    0.00   16.77 v _055_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  5.17    3.36   20.12 ^ _055_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.12                           _002_ (net)
+                  5.17    0.03   20.16 ^ _096_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 20.16   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34   65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00   65.77 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.52   clock uncertainty
+                          0.00   65.52   clock reconvergence pessimism
+                         -0.23   65.29   library setup time
+                                 65.29   data required time
+-----------------------------------------------------------------------------
+                                 65.29   data required time
+                                -20.16   data arrival time
+-----------------------------------------------------------------------------
+                                 45.13   slack (MET)
+
+
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[4] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  5.45    4.36    5.19 ^ _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.47                           net16 (net)
+                  5.48    0.22    5.41 ^ output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.56    1.06    6.47 ^ output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[4] (net)
+                  0.56    0.00    6.47 ^ io_out[4] (out)
+                                  6.47   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -6.47   data arrival time
+-----------------------------------------------------------------------------
+                                 45.28   slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[12] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  5.36    4.31    5.14 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.47                           net5 (net)
+                  5.39    0.23    5.37 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.56    1.06    6.43 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[12] (net)
+                  0.56    0.00    6.43 ^ io_out[12] (out)
+                                  6.43   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -6.43   data arrival time
+-----------------------------------------------------------------------------
+                                 45.32   slack (MET)
+
+
+Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[10] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  5.16    4.20    5.03 ^ _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.45                           net3 (net)
+                  5.18    0.19    5.23 ^ output3/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.56    1.05    6.28 ^ output3/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[10] (net)
+                  0.56    0.00    6.28 ^ io_out[10] (out)
+                                  6.28   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -6.28   data arrival time
+-----------------------------------------------------------------------------
+                                 45.47   slack (MET)
+
+
+Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[15] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  5.46    4.35    5.18 ^ _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.23                           net8 (net)
+                  5.46    0.00    5.18 ^ output8/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.56    1.06    6.24 ^ output8/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[15] (net)
+                  0.56    0.00    6.24 ^ io_out[15] (out)
+                                  6.24   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -6.24   data arrival time
+-----------------------------------------------------------------------------
+                                 45.51   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  1.63    1.30   16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  1.63    0.01   16.33 ^ _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+                  0.56    0.38   16.71 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+     2    0.01                           _045_ (net)
+                  0.56    0.00   16.71 v _091_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  4.37    2.86   19.57 ^ _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.10                           _018_ (net)
+                  4.37    0.02   19.59 ^ _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 19.59   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34   65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00   65.77 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.25   65.52   clock uncertainty
+                          0.00   65.52   clock reconvergence pessimism
+                         -0.27   65.25   library setup time
+                                 65.25   data required time
+-----------------------------------------------------------------------------
+                                 65.25   data required time
+                                -19.59   data arrival time
+-----------------------------------------------------------------------------
+                                 45.66   slack (MET)
+
+
+Startpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[5] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.86 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  4.69    3.90    4.76 ^ _103_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.41                           net17 (net)
+                  4.72    0.20    4.96 ^ output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.55    1.04    6.00 ^ output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[5] (net)
+                  0.55    0.00    6.00 ^ io_out[5] (out)
+                                  6.00   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -6.00   data arrival time
+-----------------------------------------------------------------------------
+                                 45.75   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  1.62    1.40   16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  1.63    0.02   16.44 v _066_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  3.97    2.93   19.38 ^ _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.09                           _007_ (net)
+                  3.97    0.02   19.40 ^ _101_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 19.40   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32   65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00   65.75 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.25   65.50   clock uncertainty
+                          0.00   65.50   clock reconvergence pessimism
+                         -0.31   65.19   library setup time
+                                 65.19   data required time
+-----------------------------------------------------------------------------
+                                 65.19   data required time
+                                -19.40   data arrival time
+-----------------------------------------------------------------------------
+                                 45.79   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  1.62    1.40   16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  1.63    0.03   16.45 v _058_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  4.10    2.91   19.35 ^ _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.09                           _004_ (net)
+                  4.10    0.02   19.37 ^ _098_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 19.37   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34   65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00   65.77 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.52   clock uncertainty
+                          0.00   65.52   clock reconvergence pessimism
+                         -0.32   65.20   library setup time
+                                 65.20   data required time
+-----------------------------------------------------------------------------
+                                 65.20   data required time
+                                -19.37   data arrival time
+-----------------------------------------------------------------------------
+                                 45.83   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  1.63    1.30   16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  1.63    0.01   16.33 ^ _086_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  1.01    0.35   16.68 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _042_ (net)
+                  1.01    0.00   16.68 v _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  3.59    2.52   19.20 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.08                           _017_ (net)
+                  3.59    0.02   19.22 ^ _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 19.22   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34   65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00   65.77 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.52   clock uncertainty
+                          0.00   65.52   clock reconvergence pessimism
+                         -0.36   65.16   library setup time
+                                 65.16   data required time
+-----------------------------------------------------------------------------
+                                 65.16   data required time
+                                -19.22   data arrival time
+-----------------------------------------------------------------------------
+                                 45.94   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  1.62    1.40   16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  1.63    0.03   16.45 v _085_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  3.78    2.70   19.15 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.08                           _016_ (net)
+                  3.78    0.01   19.16 ^ _110_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 19.16   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32   65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00   65.75 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.50   clock uncertainty
+                          0.00   65.50   clock reconvergence pessimism
+                         -0.36   65.15   library setup time
+                                 65.15   data required time
+-----------------------------------------------------------------------------
+                                 65.15   data required time
+                                -19.16   data arrival time
+-----------------------------------------------------------------------------
+                                 45.98   slack (MET)
+
+
+Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[7] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  4.57    3.82    4.67 ^ _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.20                           net19 (net)
+                  4.57    0.04    4.71 ^ output19/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.55    1.03    5.73 ^ output19/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[7] (net)
+                  0.55    0.00    5.74 ^ io_out[7] (out)
+                                  5.74   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -5.74   data arrival time
+-----------------------------------------------------------------------------
+                                 46.01   slack (MET)
+
+
+Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[8] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.86 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  4.32    3.69    4.55 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.37                           net20 (net)
+                  4.33    0.17    4.72 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.54    1.02    5.73 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[8] (net)
+                  0.54    0.00    5.73 ^ io_out[8] (out)
+                                  5.73   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -5.73   data arrival time
+-----------------------------------------------------------------------------
+                                 46.02   slack (MET)
+
+
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  4.18    3.62    4.47 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.36                           net9 (net)
+                  4.20    0.15    4.63 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.54    1.01    5.63 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[16] (net)
+                  0.54    0.00    5.63 ^ io_out[16] (out)
+                                  5.63   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -5.63   data arrival time
+-----------------------------------------------------------------------------
+                                 46.12   slack (MET)
+
+
+Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[6] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.86 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  4.04    3.49    4.35 ^ _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.17                           net18 (net)
+                  4.04    0.03    4.37 ^ output18/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.54    1.00    5.37 ^ output18/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[6] (net)
+                  0.54    0.00    5.37 ^ io_out[6] (out)
+                                  5.37   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -5.37   data arrival time
+-----------------------------------------------------------------------------
+                                 46.38   slack (MET)
+
+
+Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[18] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  3.74    3.36    4.21 ^ _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.32                           net11 (net)
+                  3.75    0.14    4.35 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.53    0.99    5.34 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[18] (net)
+                  0.53    0.00    5.34 ^ io_out[18] (out)
+                                  5.34   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -5.34   data arrival time
+-----------------------------------------------------------------------------
+                                 46.41   slack (MET)
+
+
+Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[3] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  3.95    3.42    4.25 ^ _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.17                           net15 (net)
+                  3.95    0.06    4.31 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.54    1.00    5.31 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[3] (net)
+                  0.54    0.00    5.31 ^ io_out[3] (out)
+                                  5.31   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -5.31   data arrival time
+-----------------------------------------------------------------------------
+                                 46.44   slack (MET)
+
+
+Startpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[19] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  3.65    3.27    4.10 ^ _097_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     4    0.32                           net12 (net)
+                  3.68    0.18    4.28 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.53    0.99    5.27 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[19] (net)
+                  0.53    0.00    5.27 ^ io_out[19] (out)
+                                  5.27   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -5.27   data arrival time
+-----------------------------------------------------------------------------
+                                 46.48   slack (MET)
+
+
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.71    2.77    3.62 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.23                           net2 (net)
+                  2.71    0.02    3.64 ^ output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.52    0.93    4.57 ^ output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[0] (net)
+                  0.52    0.00    4.57 ^ io_out[0] (out)
+                                  4.57   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -4.57   data arrival time
+-----------------------------------------------------------------------------
+                                 47.18   slack (MET)
+
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[13] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.55    2.66    3.51 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.22                           net6 (net)
+                  2.56    0.08    3.59 ^ output6/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.51    0.91    4.50 ^ output6/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[13] (net)
+                  0.51    0.00    4.50 ^ io_out[13] (out)
+                                  4.50   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -4.50   data arrival time
+-----------------------------------------------------------------------------
+                                 47.25   slack (MET)
+
+
+Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[14] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.59    2.60    3.46 ^ _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.11                           net7 (net)
+                  2.59    0.02    3.48 ^ output7/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.52    0.92    4.40 ^ output7/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[14] (net)
+                  0.52    0.00    4.40 ^ io_out[14] (out)
+                                  4.40   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -4.40   data arrival time
+-----------------------------------------------------------------------------
+                                 47.35   slack (MET)
+
+
+Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[2] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.30    2.51    3.36 ^ _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.20                           net14 (net)
+                  2.31    0.08    3.44 ^ output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.51    0.90    4.34 ^ output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[2] (net)
+                  0.51    0.00    4.34 ^ io_out[2] (out)
+                                  4.34   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -4.34   data arrival time
+-----------------------------------------------------------------------------
+                                 47.41   slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[9] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.35    2.53    3.36 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.20                           net21 (net)
+                  2.35    0.05    3.41 ^ output21/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.51    0.90    4.31 ^ output21/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[9] (net)
+                  0.51    0.00    4.31 ^ io_out[9] (out)
+                                  4.31   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -4.31   data arrival time
+-----------------------------------------------------------------------------
+                                 47.44   slack (MET)
+
+
+Startpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[11] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.03    2.35    3.21 ^ _109_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     4    0.17                           net4 (net)
+                  2.04    0.03    3.24 ^ output4/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.50    0.87    4.11 ^ output4/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[11] (net)
+                  0.50    0.00    4.11 ^ io_out[11] (out)
+                                  4.11   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -4.11   data arrival time
+-----------------------------------------------------------------------------
+                                 47.64   slack (MET)
+
+
+
+======================= Fastest Corner ===================================
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  0.79    0.66   14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  0.79    0.02   14.62 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  7.86    4.79   19.41 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.43                           _012_ (net)
+                  7.87    0.12   19.53 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 19.53   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16   65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00   65.37 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.12   clock uncertainty
+                          0.00   65.12   clock reconvergence pessimism
+                          0.62   65.73   library setup time
+                                 65.73   data required time
+-----------------------------------------------------------------------------
+                                 65.73   data required time
+                                -19.53   data arrival time
+-----------------------------------------------------------------------------
+                                 46.20   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  0.75    0.58   14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  0.75    0.00   14.53 ^ _050_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.83    0.21   14.75 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     2    0.02                           _022_ (net)
+                  0.83    0.00   14.75 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  4.18    2.63   17.38 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.22                           _001_ (net)
+                  4.18    0.07   17.45 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 17.45   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15   65.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00   65.36 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.11   clock uncertainty
+                          0.00   65.11   clock reconvergence pessimism
+                          0.20   65.31   library setup time
+                                 65.31   data required time
+-----------------------------------------------------------------------------
+                                 65.31   data required time
+                                -17.45   data arrival time
+-----------------------------------------------------------------------------
+                                 47.86   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  0.79    0.66   14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  0.79    0.02   14.62 v _084_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  4.16    2.66   17.27 ^ _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.23                           _015_ (net)
+                  4.17    0.08   17.35 ^ _109_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 17.35   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16   65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00   65.36 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.11   clock uncertainty
+                          0.00   65.11   clock reconvergence pessimism
+                          0.21   65.32   library setup time
+                                 65.32   data required time
+-----------------------------------------------------------------------------
+                                 65.32   data required time
+                                -17.35   data arrival time
+-----------------------------------------------------------------------------
+                                 47.97   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  0.79    0.66   14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  0.79    0.02   14.63 v _048_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  4.15    2.61   17.24 ^ _048_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.23                           _000_ (net)
+                  4.15    0.05   17.29 ^ _094_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 17.29   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16   65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00   65.37 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.12   clock uncertainty
+                          0.00   65.12   clock reconvergence pessimism
+                          0.20   65.32   library setup time
+                                 65.32   data required time
+-----------------------------------------------------------------------------
+                                 65.32   data required time
+                                -17.29   data arrival time
+-----------------------------------------------------------------------------
+                                 48.03   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  0.75    0.58   14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  0.75    0.01   14.54 ^ _068_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.59    0.14   14.68 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _032_ (net)
+                  0.59    0.00   14.68 v _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  3.92    2.45   17.13 ^ _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.21                           _009_ (net)
+                  3.92    0.06   17.19 ^ _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 17.19   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16   65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00   65.37 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.12   clock uncertainty
+                          0.00   65.12   clock reconvergence pessimism
+                          0.18   65.29   library setup time
+                                 65.29   data required time
+-----------------------------------------------------------------------------
+                                 65.29   data required time
+                                -17.19   data arrival time
+-----------------------------------------------------------------------------
+                                 48.10   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  0.75    0.58   14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  0.75    0.01   14.54 ^ _059_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.70    0.14   14.68 v _059_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _027_ (net)
+                  0.70    0.00   14.68 v _060_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  3.50    2.23   16.91 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.19                           _005_ (net)
+                  3.50    0.04   16.95 ^ _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 16.95   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15   65.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00   65.36 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.11   clock uncertainty
+                          0.00   65.11   clock reconvergence pessimism
+                          0.13   65.23   library setup time
+                                 65.23   data required time
+-----------------------------------------------------------------------------
+                                 65.23   data required time
+                                -16.95   data arrival time
+-----------------------------------------------------------------------------
+                                 48.28   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  0.75    0.58   14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  0.75    0.01   14.53 ^ _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+                  0.33    0.22   14.76 v _063_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+     2    0.02                           _030_ (net)
+                  0.33    0.00   14.76 v _064_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  3.46    2.14   16.90 ^ _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.19                           _006_ (net)
+                  3.46    0.04   16.94 ^ _100_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 16.94   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16   65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00   65.36 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.11   clock uncertainty
+                          0.00   65.11   clock reconvergence pessimism
+                          0.13   65.24   library setup time
+                                 65.24   data required time
+-----------------------------------------------------------------------------
+                                 65.24   data required time
+                                -16.94   data arrival time
+-----------------------------------------------------------------------------
+                                 48.30   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  0.79    0.66   14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  0.79    0.03   14.63 v _075_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  3.45    2.25   16.88 ^ _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.19                           _011_ (net)
+                  3.45    0.05   16.93 ^ _105_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 16.93   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16   65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00   65.37 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.25   65.12   clock uncertainty
+                          0.00   65.12   clock reconvergence pessimism
+                          0.15   65.26   library setup time
+                                 65.26   data required time
+-----------------------------------------------------------------------------
+                                 65.26   data required time
+                                -16.93   data arrival time
+-----------------------------------------------------------------------------
+                                 48.33   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  0.75    0.58   14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  0.75    0.00   14.53 ^ _081_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+                  0.24    0.13   14.66 v _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+     1    0.01                           _040_ (net)
+                  0.24    0.00   14.66 v _082_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  3.52    2.16   16.82 ^ _082_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.19                           _014_ (net)
+                  3.53    0.06   16.88 ^ _108_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 16.88   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15   65.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00   65.36 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.11   clock uncertainty
+                          0.00   65.11   clock reconvergence pessimism
+                          0.13   65.24   library setup time
+                                 65.24   data required time
+-----------------------------------------------------------------------------
+                                 65.24   data required time
+                                -16.88   data arrival time
+-----------------------------------------------------------------------------
+                                 48.35   slack (MET)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[17] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.17    0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.39 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.79    2.08    2.48 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.53                           net10 (net)
+                  2.83    0.21    2.69 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.28    0.58    3.27 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[17] (net)
+                  0.28    0.00    3.27 ^ io_out[17] (out)
+                                  3.27   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.27   data arrival time
+-----------------------------------------------------------------------------
+                                 48.48   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  0.79    0.66   14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  0.79    0.02   14.62 v _057_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  3.02    2.00   16.62 ^ _057_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.16                           _003_ (net)
+                  3.02    0.05   16.67 ^ _097_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 16.67   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15   65.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00   65.36 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.11   clock uncertainty
+                          0.00   65.11   clock reconvergence pessimism
+                          0.07   65.18   library setup time
+                                 65.18   data required time
+-----------------------------------------------------------------------------
+                                 65.18   data required time
+                                -16.67   data arrival time
+-----------------------------------------------------------------------------
+                                 48.51   slack (MET)
+
+
+Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.17    0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.39 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.78    2.15    2.54 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.52                           net13 (net)
+                  2.79    0.07    2.61 ^ output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.27    0.58    3.19 ^ output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[1] (net)
+                  0.27    0.00    3.19 ^ io_out[1] (out)
+                                  3.19   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.19   data arrival time
+-----------------------------------------------------------------------------
+                                 48.56   slack (MET)
+
+
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[4] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.17    0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.39 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.50    1.89    2.29 ^ _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.47                           net16 (net)
+                  2.55    0.22    2.50 ^ output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.26    0.56    3.06 ^ output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[4] (net)
+                  0.26    0.00    3.06 ^ io_out[4] (out)
+                                  3.06   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.06   data arrival time
+-----------------------------------------------------------------------------
+                                 48.69   slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[12] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.17    0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.39 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.45    1.88    2.27 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.47                           net5 (net)
+                  2.51    0.23    2.50 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.27    0.56    3.06 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[12] (net)
+                  0.27    0.00    3.06 ^ io_out[12] (out)
+                                  3.06   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -3.06   data arrival time
+-----------------------------------------------------------------------------
+                                 48.69   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  0.79    0.66   14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  0.79    0.03   14.63 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  2.54    1.72   16.35 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.14                           _019_ (net)
+                  2.54    0.04   16.38 ^ _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 16.38   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15   65.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00   65.36 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.25   65.11   clock uncertainty
+                          0.00   65.11   clock reconvergence pessimism
+                          0.03   65.14   library setup time
+                                 65.14   data required time
+-----------------------------------------------------------------------------
+                                 65.14   data required time
+                                -16.38   data arrival time
+-----------------------------------------------------------------------------
+                                 48.76   slack (MET)
+
+
+Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[10] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.17    0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.39 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.37    1.84    2.23 ^ _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.45                           net3 (net)
+                  2.41    0.19    2.42 ^ output3/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.26    0.55    2.97 ^ output3/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[10] (net)
+                  0.26    0.00    2.98 ^ io_out[10] (out)
+                                  2.98   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.98   data arrival time
+-----------------------------------------------------------------------------
+                                 48.77   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  0.79    0.66   14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  0.79    0.03   14.63 v _067_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  2.56    1.68   16.31 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.14                           _008_ (net)
+                  2.56    0.02   16.33 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 16.33   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15   65.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00   65.36 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.11   clock uncertainty
+                          0.00   65.11   clock reconvergence pessimism
+                          0.02   65.13   library setup time
+                                 65.13   data required time
+-----------------------------------------------------------------------------
+                                 65.13   data required time
+                                -16.33   data arrival time
+-----------------------------------------------------------------------------
+                                 48.80   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  0.75    0.58   14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  0.75    0.01   14.53 ^ _077_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.43    0.13   14.66 v _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _037_ (net)
+                  0.43    0.00   14.66 v _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  2.55    1.62   16.28 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.13                           _013_ (net)
+                  2.55    0.04   16.32 ^ _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 16.32   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15   65.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00   65.36 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.11   clock uncertainty
+                          0.00   65.11   clock reconvergence pessimism
+                          0.02   65.13   library setup time
+                                 65.13   data required time
+-----------------------------------------------------------------------------
+                                 65.13   data required time
+                                -16.32   data arrival time
+-----------------------------------------------------------------------------
+                                 48.81   slack (MET)
+
+
+Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[15] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.17    0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.39 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.51    1.97    2.36 ^ _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.23                           net8 (net)
+                  2.51    0.00    2.36 ^ output8/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.26    0.56    2.92 ^ output8/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[15] (net)
+                  0.26    0.00    2.92 ^ io_out[15] (out)
+                                  2.92   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.92   data arrival time
+-----------------------------------------------------------------------------
+                                 48.83   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  0.75    0.58   14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  0.75    0.01   14.54 ^ _072_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+                  0.22    0.11   14.65 v _072_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+     1    0.01                           _035_ (net)
+                  0.22    0.00   14.65 v _073_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  2.50    1.55   16.20 ^ _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.13                           _010_ (net)
+                  2.50    0.04   16.24 ^ _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 16.24   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16   65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00   65.37 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.25   65.12   clock uncertainty
+                          0.00   65.12   clock reconvergence pessimism
+                          0.03   65.15   library setup time
+                                 65.15   data required time
+-----------------------------------------------------------------------------
+                                 65.15   data required time
+                                -16.24   data arrival time
+-----------------------------------------------------------------------------
+                                 48.91   slack (MET)
+
+
+Startpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[5] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  2.15    1.68    2.09 ^ _103_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.41                           net17 (net)
+                  2.20    0.20    2.29 ^ output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.26    0.54    2.83 ^ output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[5] (net)
+                  0.26    0.00    2.83 ^ io_out[5] (out)
+                                  2.83   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.83   data arrival time
+-----------------------------------------------------------------------------
+                                 48.92   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  0.75    0.58   14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  0.75    0.00   14.53 ^ _054_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+                  0.30    0.19   14.73 v _054_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+     2    0.01                           _025_ (net)
+                  0.30    0.00   14.73 v _055_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  2.15    1.35   16.08 ^ _055_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.12                           _002_ (net)
+                  2.15    0.03   16.11 ^ _096_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 16.11   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16   65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00   65.36 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.11   clock uncertainty
+                          0.00   65.11   clock reconvergence pessimism
+                         -0.02   65.10   library setup time
+                                 65.10   data required time
+-----------------------------------------------------------------------------
+                                 65.10   data required time
+                                -16.11   data arrival time
+-----------------------------------------------------------------------------
+                                 48.98   slack (MET)
+
+
+Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[8] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.98    1.60    2.01 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.37                           net20 (net)
+                  2.01    0.17    2.17 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.25    0.52    2.70 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[8] (net)
+                  0.25    0.00    2.70 ^ io_out[8] (out)
+                                  2.70   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.70   data arrival time
+-----------------------------------------------------------------------------
+                                 49.05   slack (MET)
+
+
+Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[7] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.11    1.71    2.11 ^ _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.20                           net19 (net)
+                  2.12    0.04    2.15 ^ output19/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.26    0.53    2.68 ^ output19/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[7] (net)
+                  0.26    0.00    2.68 ^ io_out[7] (out)
+                                  2.68   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.68   data arrival time
+-----------------------------------------------------------------------------
+                                 49.07   slack (MET)
+
+
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.91    1.57    1.98 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.36                           net9 (net)
+                  1.95    0.15    2.13 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.25    0.52    2.65 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[16] (net)
+                  0.25    0.00    2.65 ^ io_out[16] (out)
+                                  2.65   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.65   data arrival time
+-----------------------------------------------------------------------------
+                                 49.10   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  0.79    0.66   14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  0.79    0.02   14.62 v _066_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  1.65    1.21   15.83 ^ _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.09                           _007_ (net)
+                  1.65    0.02   15.85 ^ _101_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 15.85   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15   65.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00   65.36 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.25   65.11   clock uncertainty
+                          0.00   65.11   clock reconvergence pessimism
+                         -0.07   65.04   library setup time
+                                 65.04   data required time
+-----------------------------------------------------------------------------
+                                 65.04   data required time
+                                -15.85   data arrival time
+-----------------------------------------------------------------------------
+                                 49.19   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  0.75    0.58   14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  0.75    0.01   14.54 ^ _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+                  0.27    0.16   14.70 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+     2    0.01                           _045_ (net)
+                  0.27    0.00   14.70 v _091_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  1.82    1.16   15.86 ^ _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.10                           _018_ (net)
+                  1.82    0.02   15.88 ^ _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                 15.88   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16   65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00   65.36 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                         -0.25   65.11   clock uncertainty
+                          0.00   65.11   clock reconvergence pessimism
+                         -0.05   65.07   library setup time
+                                 65.07   data required time
+-----------------------------------------------------------------------------
+                                 65.07   data required time
+                                -15.88   data arrival time
+-----------------------------------------------------------------------------
+                                 49.19   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  0.79    0.66   14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  0.79    0.03   14.63 v _058_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  1.71    1.18   15.80 ^ _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.09                           _004_ (net)
+                  1.71    0.02   15.82 ^ _098_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 15.82   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16   65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00   65.37 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.12   clock uncertainty
+                          0.00   65.12   clock reconvergence pessimism
+                         -0.07   65.05   library setup time
+                                 65.05   data required time
+-----------------------------------------------------------------------------
+                                 65.05   data required time
+                                -15.82   data arrival time
+-----------------------------------------------------------------------------
+                                 49.22   slack (MET)
+
+
+Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[18] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.72    1.46    1.86 ^ _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.32                           net11 (net)
+                  1.75    0.14    2.00 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.25    0.50    2.50 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[18] (net)
+                  0.25    0.00    2.50 ^ io_out[18] (out)
+                                  2.50   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.50   data arrival time
+-----------------------------------------------------------------------------
+                                 49.25   slack (MET)
+
+
+Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[6] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.87    1.55    1.96 ^ _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.17                           net18 (net)
+                  1.87    0.03    1.98 ^ output18/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.25    0.51    2.50 ^ output18/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[6] (net)
+                  0.25    0.00    2.50 ^ io_out[6] (out)
+                                  2.50   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.50   data arrival time
+-----------------------------------------------------------------------------
+                                 49.25   slack (MET)
+
+
+Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[3] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.17    0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.39 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.82    1.52    1.91 ^ _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.17                           net15 (net)
+                  1.83    0.06    1.97 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.25    0.51    2.48 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[3] (net)
+                  0.25    0.00    2.48 ^ io_out[3] (out)
+                                  2.48   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.48   data arrival time
+-----------------------------------------------------------------------------
+                                 49.27   slack (MET)
+
+
+Startpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[19] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.17    0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.39 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.66    1.39    1.79 ^ _097_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     4    0.32                           net12 (net)
+                  1.72    0.18    1.97 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.25    0.50    2.47 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[19] (net)
+                  0.25    0.00    2.47 ^ io_out[19] (out)
+                                  2.47   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.47   data arrival time
+-----------------------------------------------------------------------------
+                                 49.28   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  0.79    0.66   14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  0.79    0.03   14.63 v _085_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  1.60    1.09   15.72 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.08                           _016_ (net)
+                  1.60    0.01   15.74 ^ _110_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 15.74   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.15   65.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00   65.36 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.11   clock uncertainty
+                          0.00   65.11   clock reconvergence pessimism
+                         -0.08   65.02   library setup time
+                                 65.02   data required time
+-----------------------------------------------------------------------------
+                                 65.02   data required time
+                                -15.74   data arrival time
+-----------------------------------------------------------------------------
+                                 49.29   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  0.75    0.58   14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  0.75    0.01   14.54 ^ _086_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.53    0.14   14.68 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _042_ (net)
+                  0.53    0.00   14.68 v _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  1.51    1.02   15.70 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.08                           _017_ (net)
+                  1.51    0.02   15.71 ^ _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 15.71   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16   65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00   65.36 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.11   clock uncertainty
+                          0.00   65.11   clock reconvergence pessimism
+                         -0.09   65.03   library setup time
+                                 65.03   data required time
+-----------------------------------------------------------------------------
+                                 65.03   data required time
+                                -15.71   data arrival time
+-----------------------------------------------------------------------------
+                                 49.31   slack (MET)
+
+
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.24    1.21    1.62 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.23                           net2 (net)
+                  1.25    0.02    1.64 ^ output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.24    0.46    2.09 ^ output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[0] (net)
+                  0.24    0.00    2.10 ^ io_out[0] (out)
+                                  2.10   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.10   data arrival time
+-----------------------------------------------------------------------------
+                                 49.65   slack (MET)
+
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[13] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.17    1.15    1.55 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.22                           net6 (net)
+                  1.18    0.08    1.63 ^ output6/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.24    0.45    2.08 ^ output6/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[13] (net)
+                  0.24    0.00    2.08 ^ io_out[13] (out)
+                                  2.08   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.08   data arrival time
+-----------------------------------------------------------------------------
+                                 49.67   slack (MET)
+
+
+Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[14] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.19    1.14    1.55 ^ _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.11                           net7 (net)
+                  1.19    0.02    1.57 ^ output7/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.24    0.45    2.02 ^ output7/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[14] (net)
+                  0.24    0.00    2.02 ^ io_out[14] (out)
+                                  2.02   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.02   data arrival time
+-----------------------------------------------------------------------------
+                                 49.73   slack (MET)
+
+
+Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[2] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.05    1.08    1.48 ^ _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     6    0.20                           net14 (net)
+                  1.07    0.08    1.56 ^ output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.23    0.44    2.00 ^ output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[2] (net)
+                  0.23    0.00    2.00 ^ io_out[2] (out)
+                                  2.00   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.00   data arrival time
+-----------------------------------------------------------------------------
+                                 49.75   slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[9] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.08    0.17    0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.08    0.00    0.39 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.08    1.09    1.48 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.20                           net21 (net)
+                  1.08    0.05    1.53 ^ output21/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.23    0.44    1.97 ^ output21/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[9] (net)
+                  0.23    0.00    1.97 ^ io_out[9] (out)
+                                  1.97   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -1.97   data arrival time
+-----------------------------------------------------------------------------
+                                 49.78   slack (MET)
+
+
+Startpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[11] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.10    0.05    0.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00    0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.17    0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00    0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.18    0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00    0.40 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  0.93    1.02    1.42 ^ _109_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+     4    0.17                           net4 (net)
+                  0.94    0.03    1.45 ^ output4/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+                  0.23    0.42    1.88 ^ output4/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+     1    0.07                           io_out[11] (net)
+                  0.23    0.00    1.88 ^ io_out[11] (out)
+                                  1.88   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (propagated)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -1.88   data arrival time
+-----------------------------------------------------------------------------
+                                 49.87   slack (MET)
+
+
+max_report_end
+check_report
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+
+======================= Slowest Corner ===================================
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  1.05    0.40   13.40 ^ wb_rst_i (in)
+     2    0.01                           wb_rst_i (net)
+                  1.05    0.00   13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                 15.05   10.77   24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                 15.05    0.03   24.20 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  7.05    8.58   32.77 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.17                           _020_ (net)
+                  7.05    0.02   32.79 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                115.68   78.45  111.25 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.43                           _012_ (net)
+                115.68    0.12  111.36 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                111.36   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78   69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00   69.02 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   68.77   clock uncertainty
+                          0.00   68.77   clock reconvergence pessimism
+                         -5.79   62.98   library setup time
+                                 62.98   data required time
+-----------------------------------------------------------------------------
+                                 62.98   data required time
+                               -111.36   data arrival time
+-----------------------------------------------------------------------------
+                                -48.38   slack (VIOLATED)
+
+
+
+======================= Typical Corner ===================================
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  1.62    1.40   16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  1.63    0.02   16.44 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 18.95   11.96   28.41 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.43                           _012_ (net)
+                 18.95    0.12   28.52 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 28.52   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34   65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00   65.77 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.52   clock uncertainty
+                          0.00   65.52   clock reconvergence pessimism
+                          1.23   66.75   library setup time
+                                 66.75   data required time
+-----------------------------------------------------------------------------
+                                 66.75   data required time
+                                -28.52   data arrival time
+-----------------------------------------------------------------------------
+                                 38.23   slack (MET)
+
+
+
+======================= Fastest Corner ===================================
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.08    0.03   13.03 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.08    0.00   13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  1.29    0.88   13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  1.29    0.03   13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  0.79    0.66   14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  0.79    0.02   14.62 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  7.86    4.79   19.41 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.43                           _012_ (net)
+                  7.87    0.12   19.53 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 19.53   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.10    0.05   65.05 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.10    0.00   65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.07    0.15   65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.07    0.00   65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.09    0.16   65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.09    0.00   65.37 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.12   clock uncertainty
+                          0.00   65.12   clock reconvergence pessimism
+                          0.62   65.73   library setup time
+                                 65.73   data required time
+-----------------------------------------------------------------------------
+                                 65.73   data required time
+                                -19.53   data arrival time
+-----------------------------------------------------------------------------
+                                 46.20   slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+
+======================= Slowest Corner ===================================
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  1.05    0.40   13.40 ^ wb_rst_i (in)
+     2    0.01                           wb_rst_i (net)
+                  1.05    0.00   13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                 15.05   10.77   24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                 15.05    0.03   24.20 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  7.05    8.58   32.77 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.17                           _020_ (net)
+                  7.05    0.02   32.79 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                115.68   78.45  111.25 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.43                           _012_ (net)
+                115.68    0.12  111.36 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                111.36   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  1.13    0.49   65.49 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  1.13    0.00   65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.74    1.74   67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.04                           clknet_0_wb_clk_i (net)
+                  0.74    0.00   67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.98    1.78   69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.98    0.00   69.02 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   68.77   clock uncertainty
+                          0.00   68.77   clock reconvergence pessimism
+                         -5.79   62.98   library setup time
+                                 62.98   data required time
+-----------------------------------------------------------------------------
+                                 62.98   data required time
+                               -111.36   data arrival time
+-----------------------------------------------------------------------------
+                                -48.38   slack (VIOLATED)
+
+
+
+======================= Typical Corner ===================================
+
+No paths found.
+
+======================= Fastest Corner ===================================
+
+No paths found.
+check_report_end
+check_slew
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+======================= Slowest Corner ===================================
+
+max slew
+
+Pin                                    Limit    Slew   Slack
+------------------------------------------------------------
+ANTENNA__106__D/I                      25.00  115.68  -90.68 (VIOLATED)
+_076_/ZN                               25.00  115.68  -90.68 (VIOLATED)
+_106_/D                                25.00  115.68  -90.68 (VIOLATED)
+ANTENNA__095__D/I                      25.00   60.98  -35.98 (VIOLATED)
+_095_/D                                25.00   60.98  -35.98 (VIOLATED)
+_051_/ZN                               25.00   60.98  -35.98 (VIOLATED)
+ANTENNA__109__D/I                      25.00   60.94  -35.94 (VIOLATED)
+_109_/D                                25.00   60.94  -35.94 (VIOLATED)
+_084_/ZN                               25.00   60.94  -35.94 (VIOLATED)
+ANTENNA__094__D/I                      25.00   60.93  -35.93 (VIOLATED)
+_048_/ZN                               25.00   60.93  -35.93 (VIOLATED)
+_094_/D                                25.00   60.93  -35.93 (VIOLATED)
+ANTENNA__103__D/I                      25.00   57.10  -32.10 (VIOLATED)
+_103_/D                                25.00   57.10  -32.10 (VIOLATED)
+_069_/ZN                               25.00   57.10  -32.10 (VIOLATED)
+ANTENNA__108__D/I                      25.00   51.57  -26.57 (VIOLATED)
+_108_/D                                25.00   51.57  -26.57 (VIOLATED)
+_082_/ZN                               25.00   51.57  -26.57 (VIOLATED)
+ANTENNA__099__D/I                      25.00   50.93  -25.93 (VIOLATED)
+_060_/ZN                               25.00   50.93  -25.93 (VIOLATED)
+_099_/D                                25.00   50.93  -25.93 (VIOLATED)
+ANTENNA__100__D/I                      25.00   50.62  -25.62 (VIOLATED)
+_064_/ZN                               25.00   50.62  -25.62 (VIOLATED)
+_100_/D                                25.00   50.62  -25.62 (VIOLATED)
+ANTENNA__105__D/I                      25.00   50.53  -25.53 (VIOLATED)
+_105_/D                                25.00   50.53  -25.53 (VIOLATED)
+_075_/ZN                               25.00   50.53  -25.53 (VIOLATED)
+ANTENNA__097__D/I                      25.00   44.17  -19.17 (VIOLATED)
+_097_/D                                25.00   44.17  -19.17 (VIOLATED)
+_057_/ZN                               25.00   44.17  -19.17 (VIOLATED)
+ANTENNA__102__D/I                      25.00   37.40  -12.40 (VIOLATED)
+_067_/ZN                               25.00   37.40  -12.40 (VIOLATED)
+_102_/D                                25.00   37.40  -12.40 (VIOLATED)
+ANTENNA__113__D/I                      25.00   37.15  -12.15 (VIOLATED)
+_093_/ZN                               25.00   37.15  -12.15 (VIOLATED)
+_113_/D                                25.00   37.15  -12.15 (VIOLATED)
+ANTENNA__107__D/I                      25.00   37.02  -12.02 (VIOLATED)
+_107_/D                                25.00   37.02  -12.02 (VIOLATED)
+_078_/ZN                               25.00   37.02  -12.02 (VIOLATED)
+ANTENNA__104__D/I                      25.00   36.53  -11.53 (VIOLATED)
+_073_/ZN                               25.00   36.53  -11.53 (VIOLATED)
+_104_/D                                25.00   36.53  -11.53 (VIOLATED)
+ANTENNA_output10_I/I                   25.00   33.05   -8.05 (VIOLATED)
+output10/I                             25.00   33.05   -8.05 (VIOLATED)
+_053_/A2                               25.00   33.05   -8.05 (VIOLATED)
+_050_/A2                               25.00   33.05   -8.05 (VIOLATED)
+ANTENNA__053__A2/I                     25.00   33.05   -8.05 (VIOLATED)
+ANTENNA__050__A2/I                     25.00   33.05   -8.05 (VIOLATED)
+_052_/A2                               25.00   33.05   -8.05 (VIOLATED)
+ANTENNA__052__A2/I                     25.00   33.05   -8.05 (VIOLATED)
+_051_/A2                               25.00   33.05   -8.05 (VIOLATED)
+ANTENNA__051__A2/I                     25.00   33.05   -8.05 (VIOLATED)
+_095_/Q                                25.00   33.05   -8.05 (VIOLATED)
+ANTENNA__061__A2/I                     25.00   32.73   -7.73 (VIOLATED)
+ANTENNA__062__A2/I                     25.00   32.73   -7.73 (VIOLATED)
+_061_/A2                               25.00   32.73   -7.73 (VIOLATED)
+_062_/A2                               25.00   32.73   -7.73 (VIOLATED)
+ANTENNA__059__A2/I                     25.00   32.73   -7.73 (VIOLATED)
+_059_/A2                               25.00   32.73   -7.73 (VIOLATED)
+ANTENNA__060__A2/I                     25.00   32.73   -7.73 (VIOLATED)
+_060_/A2                               25.00   32.73   -7.73 (VIOLATED)
+ANTENNA_output13_I/I                   25.00   32.73   -7.73 (VIOLATED)
+output13/I                             25.00   32.73   -7.73 (VIOLATED)
+_099_/Q                                25.00   32.73   -7.73 (VIOLATED)
+ANTENNA__096__D/I                      25.00   31.46   -6.46 (VIOLATED)
+_096_/D                                25.00   31.46   -6.46 (VIOLATED)
+_055_/ZN                               25.00   31.46   -6.46 (VIOLATED)
+ANTENNA_output16_I/I                   25.00   29.73   -4.73 (VIOLATED)
+output16/I                             25.00   29.73   -4.73 (VIOLATED)
+_069_/A1                               25.00   29.73   -4.73 (VIOLATED)
+ANTENNA__069__A1/I                     25.00   29.73   -4.73 (VIOLATED)
+_068_/A1                               25.00   29.73   -4.73 (VIOLATED)
+ANTENNA__068__A1/I                     25.00   29.73   -4.73 (VIOLATED)
+ANTENNA__070__A1/I                     25.00   29.73   -4.73 (VIOLATED)
+_070_/A1                               25.00   29.73   -4.73 (VIOLATED)
+_071_/A1                               25.00   29.73   -4.73 (VIOLATED)
+ANTENNA__071__A1/I                     25.00   29.73   -4.73 (VIOLATED)
+_067_/A1                               25.00   29.73   -4.73 (VIOLATED)
+ANTENNA__067__A1/I                     25.00   29.73   -4.73 (VIOLATED)
+_102_/Q                                25.00   29.73   -4.73 (VIOLATED)
+ANTENNA__092__A1/I                     25.00   29.50   -4.50 (VIOLATED)
+_092_/A1                               25.00   29.50   -4.50 (VIOLATED)
+ANTENNA_output8_I/I                    25.00   29.50   -4.50 (VIOLATED)
+_113_/Q                                25.00   29.50   -4.50 (VIOLATED)
+output8/I                              25.00   29.50   -4.50 (VIOLATED)
+ANTENNA_output5_I/I                    25.00   29.22   -4.22 (VIOLATED)
+output5/I                              25.00   29.22   -4.22 (VIOLATED)
+ANTENNA__086__A1/I                     25.00   29.21   -4.21 (VIOLATED)
+ANTENNA__087__A1/I                     25.00   29.21   -4.21 (VIOLATED)
+_086_/A1                               25.00   29.21   -4.21 (VIOLATED)
+_087_/A1                               25.00   29.21   -4.21 (VIOLATED)
+_088_/A1                               25.00   29.21   -4.21 (VIOLATED)
+ANTENNA__088__A1/I                     25.00   29.21   -4.21 (VIOLATED)
+_089_/A1                               25.00   29.21   -4.21 (VIOLATED)
+ANTENNA__089__A1/I                     25.00   29.21   -4.21 (VIOLATED)
+_085_/A1                               25.00   29.21   -4.21 (VIOLATED)
+ANTENNA__085__A1/I                     25.00   29.21   -4.21 (VIOLATED)
+_110_/Q                                25.00   29.21   -4.21 (VIOLATED)
+ANTENNA_output3_I/I                    25.00   28.12   -3.12 (VIOLATED)
+output3/I                              25.00   28.12   -3.12 (VIOLATED)
+ANTENNA__079__B/I                      25.00   28.12   -3.12 (VIOLATED)
+_079_/B                                25.00   28.12   -3.12 (VIOLATED)
+_080_/A3                               25.00   28.12   -3.12 (VIOLATED)
+ANTENNA__080__A3/I                     25.00   28.12   -3.12 (VIOLATED)
+_108_/Q                                25.00   28.12   -3.12 (VIOLATED)
+ANTENNA__112__D/I                      25.00   26.61   -1.61 (VIOLATED)
+_091_/ZN                               25.00   26.61   -1.61 (VIOLATED)
+_112_/D                                25.00   26.61   -1.61 (VIOLATED)
+output17/I                             25.00   25.59   -0.59 (VIOLATED)
+ANTENNA_output17_I/I                   25.00   25.59   -0.59 (VIOLATED)
+_069_/A2                               25.00   25.58   -0.58 (VIOLATED)
+_068_/A2                               25.00   25.58   -0.58 (VIOLATED)
+ANTENNA__069__A2/I                     25.00   25.58   -0.58 (VIOLATED)
+ANTENNA__068__A2/I                     25.00   25.58   -0.58 (VIOLATED)
+_070_/A2                               25.00   25.58   -0.58 (VIOLATED)
+ANTENNA__070__A2/I                     25.00   25.58   -0.58 (VIOLATED)
+_071_/A2                               25.00   25.58   -0.58 (VIOLATED)
+ANTENNA__071__A2/I                     25.00   25.58   -0.58 (VIOLATED)
+_103_/Q                                25.00   25.58   -0.58 (VIOLATED)
+
+max capacitance
+
+Pin                                    Limit     Cap   Slack
+------------------------------------------------------------
+_076_/ZN                                0.09    0.43   -0.35 (VIOLATED)
+_095_/Q                                 0.39    0.53   -0.14 (VIOLATED)
+_084_/ZN                                0.09    0.23   -0.14 (VIOLATED)
+_048_/ZN                                0.09    0.23   -0.14 (VIOLATED)
+_051_/ZN                                0.09    0.22   -0.14 (VIOLATED)
+_099_/Q                                 0.39    0.52   -0.13 (VIOLATED)
+_069_/ZN                                0.09    0.21   -0.12 (VIOLATED)
+_082_/ZN                                0.09    0.19   -0.10 (VIOLATED)
+_064_/ZN                                0.09    0.19   -0.10 (VIOLATED)
+_060_/ZN                                0.09    0.19   -0.10 (VIOLATED)
+_075_/ZN                                0.09    0.19   -0.10 (VIOLATED)
+_102_/Q                                 0.39    0.47   -0.09 (VIOLATED)
+_110_/Q                                 0.39    0.46   -0.08 (VIOLATED)
+_057_/ZN                                0.09    0.16   -0.08 (VIOLATED)
+_108_/Q                                 0.39    0.45   -0.06 (VIOLATED)
+_067_/ZN                                0.09    0.14   -0.05 (VIOLATED)
+_093_/ZN                                0.09    0.14   -0.05 (VIOLATED)
+_078_/ZN                                0.09    0.13   -0.05 (VIOLATED)
+_073_/ZN                                0.09    0.13   -0.05 (VIOLATED)
+_113_/Q                                 0.19    0.23   -0.04 (VIOLATED)
+_055_/ZN                                0.09    0.12   -0.03 (VIOLATED)
+_103_/Q                                 0.39    0.41   -0.02 (VIOLATED)
+_091_/ZN                                0.09    0.10   -0.01 (VIOLATED)
+_105_/Q                                 0.19    0.20   -0.00 (VIOLATED)
+_058_/ZN                                0.09    0.09   -0.00 (VIOLATED)
+
+
+======================= Typical Corner ===================================
+
+max slew
+
+Pin                                    Limit    Slew   Slack
+------------------------------------------------------------
+ANTENNA__106__D/I                       8.60   18.95  -10.35 (VIOLATED)
+_106_/D                                 8.60   18.95  -10.35 (VIOLATED)
+_076_/ZN                                8.60   18.95  -10.35 (VIOLATED)
+_095_/D                                 8.60   10.03   -1.43 (VIOLATED)
+ANTENNA__095__D/I                       8.60   10.03   -1.43 (VIOLATED)
+_051_/ZN                                8.60   10.03   -1.43 (VIOLATED)
+_109_/D                                 8.60   10.00   -1.40 (VIOLATED)
+ANTENNA__109__D/I                       8.60   10.00   -1.40 (VIOLATED)
+_084_/ZN                                8.60   10.00   -1.40 (VIOLATED)
+_094_/D                                 8.60    9.99   -1.39 (VIOLATED)
+ANTENNA__094__D/I                       8.60    9.99   -1.39 (VIOLATED)
+_048_/ZN                                8.60    9.99   -1.39 (VIOLATED)
+_103_/D                                 8.60    9.40   -0.80 (VIOLATED)
+ANTENNA__103__D/I                       8.60    9.40   -0.80 (VIOLATED)
+_069_/ZN                                8.60    9.40   -0.80 (VIOLATED)
+
+max capacitance
+
+Pin                                    Limit     Cap   Slack
+------------------------------------------------------------
+_076_/ZN                                0.18    0.43   -0.25 (VIOLATED)
+_084_/ZN                                0.18    0.23   -0.04 (VIOLATED)
+_048_/ZN                                0.18    0.23   -0.04 (VIOLATED)
+_051_/ZN                                0.18    0.22   -0.04 (VIOLATED)
+_069_/ZN                                0.18    0.21   -0.03 (VIOLATED)
+_082_/ZN                                0.18    0.19   -0.01 (VIOLATED)
+_060_/ZN                                0.18    0.19   -0.01 (VIOLATED)
+_064_/ZN                                0.18    0.19   -0.01 (VIOLATED)
+_075_/ZN                                0.18    0.19   -0.00 (VIOLATED)
+
+
+======================= Fastest Corner ===================================
+
+max slew
+
+Pin                                    Limit    Slew   Slack
+------------------------------------------------------------
+_106_/D                                 2.60    7.87   -5.27 (VIOLATED)
+ANTENNA__106__D/I                       2.60    7.87   -5.27 (VIOLATED)
+_076_/ZN                                2.60    7.86   -5.26 (VIOLATED)
+_095_/D                                 2.60    4.18   -1.58 (VIOLATED)
+ANTENNA__095__D/I                       2.60    4.18   -1.58 (VIOLATED)
+_051_/ZN                                2.60    4.18   -1.58 (VIOLATED)
+_109_/D                                 2.60    4.17   -1.57 (VIOLATED)
+ANTENNA__109__D/I                       2.60    4.17   -1.57 (VIOLATED)
+_084_/ZN                                2.60    4.16   -1.56 (VIOLATED)
+_094_/D                                 2.60    4.15   -1.55 (VIOLATED)
+ANTENNA__094__D/I                       2.60    4.15   -1.55 (VIOLATED)
+_048_/ZN                                2.60    4.15   -1.55 (VIOLATED)
+_103_/D                                 2.60    3.92   -1.32 (VIOLATED)
+ANTENNA__103__D/I                       2.60    3.92   -1.32 (VIOLATED)
+_069_/ZN                                2.60    3.92   -1.32 (VIOLATED)
+_108_/D                                 2.60    3.53   -0.93 (VIOLATED)
+ANTENNA__108__D/I                       2.60    3.53   -0.93 (VIOLATED)
+_082_/ZN                                2.60    3.52   -0.92 (VIOLATED)
+_099_/D                                 2.60    3.50   -0.90 (VIOLATED)
+ANTENNA__099__D/I                       2.60    3.50   -0.90 (VIOLATED)
+_060_/ZN                                2.60    3.50   -0.90 (VIOLATED)
+_100_/D                                 2.60    3.46   -0.86 (VIOLATED)
+ANTENNA__100__D/I                       2.60    3.46   -0.86 (VIOLATED)
+_064_/ZN                                2.60    3.46   -0.86 (VIOLATED)
+_105_/D                                 2.60    3.45   -0.85 (VIOLATED)
+ANTENNA__105__D/I                       2.60    3.45   -0.85 (VIOLATED)
+_075_/ZN                                2.60    3.45   -0.85 (VIOLATED)
+_097_/D                                 2.60    3.02   -0.42 (VIOLATED)
+ANTENNA__097__D/I                       2.60    3.02   -0.42 (VIOLATED)
+_057_/ZN                                2.60    3.02   -0.42 (VIOLATED)
+output10/I                              2.60    2.83   -0.23 (VIOLATED)
+ANTENNA_output10_I/I                    2.60    2.83   -0.23 (VIOLATED)
+_053_/A2                                2.60    2.81   -0.21 (VIOLATED)
+_050_/A2                                2.60    2.81   -0.21 (VIOLATED)
+ANTENNA__053__A2/I                      2.60    2.81   -0.21 (VIOLATED)
+ANTENNA__050__A2/I                      2.60    2.81   -0.21 (VIOLATED)
+_052_/A2                                2.60    2.81   -0.21 (VIOLATED)
+ANTENNA__052__A2/I                      2.60    2.81   -0.21 (VIOLATED)
+_051_/A2                                2.60    2.81   -0.21 (VIOLATED)
+ANTENNA__051__A2/I                      2.60    2.81   -0.21 (VIOLATED)
+_062_/A2                                2.60    2.79   -0.19 (VIOLATED)
+ANTENNA__062__A2/I                      2.60    2.79   -0.19 (VIOLATED)
+_061_/A2                                2.60    2.79   -0.19 (VIOLATED)
+ANTENNA__061__A2/I                      2.60    2.79   -0.19 (VIOLATED)
+_059_/A2                                2.60    2.79   -0.19 (VIOLATED)
+ANTENNA__059__A2/I                      2.60    2.79   -0.19 (VIOLATED)
+ANTENNA__060__A2/I                      2.60    2.79   -0.19 (VIOLATED)
+_060_/A2                                2.60    2.79   -0.19 (VIOLATED)
+output13/I                              2.60    2.79   -0.19 (VIOLATED)
+ANTENNA_output13_I/I                    2.60    2.79   -0.19 (VIOLATED)
+_095_/Q                                 2.60    2.79   -0.19 (VIOLATED)
+_099_/Q                                 2.60    2.78   -0.18 (VIOLATED)
+
+max capacitance
+
+Pin                                    Limit     Cap   Slack
+------------------------------------------------------------
+_076_/ZN                                0.13    0.43   -0.30 (VIOLATED)
+_084_/ZN                                0.13    0.23   -0.10 (VIOLATED)
+_048_/ZN                                0.13    0.23   -0.10 (VIOLATED)
+_051_/ZN                                0.13    0.22   -0.09 (VIOLATED)
+_069_/ZN                                0.13    0.21   -0.08 (VIOLATED)
+_082_/ZN                                0.13    0.19   -0.06 (VIOLATED)
+_095_/Q                                 0.47    0.53   -0.06 (VIOLATED)
+_064_/ZN                                0.13    0.19   -0.06 (VIOLATED)
+_060_/ZN                                0.13    0.19   -0.06 (VIOLATED)
+_075_/ZN                                0.13    0.19   -0.06 (VIOLATED)
+_099_/Q                                 0.47    0.52   -0.05 (VIOLATED)
+_057_/ZN                                0.13    0.16   -0.03 (VIOLATED)
+_067_/ZN                                0.13    0.14   -0.01 (VIOLATED)
+_102_/Q                                 0.47    0.47   -0.01 (VIOLATED)
+_093_/ZN                                0.13    0.14   -0.01 (VIOLATED)
+_078_/ZN                                0.13    0.13   -0.00 (VIOLATED)
+_073_/ZN                                0.13    0.13   -0.00 (VIOLATED)
+_113_/Q                                 0.23    0.23   -0.00 (VIOLATED)
+
+
+===========================================================================
+max slew violation count 119
+max fanout violation count 0
+max cap violation count 25
+============================================================================
+check_slew_end
+tns_report
+
+===========================================================================
+ report_tns
+============================================================================
+tns -198.89
+tns_report_end
+wns_report
+
+===========================================================================
+ report_wns
+============================================================================
+wns -48.38
+wns_report_end
+worst_slack
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack -48.38
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 1.50
+worst_slack_end
+clock_skew
+
+===========================================================================
+ report_clock_skew
+============================================================================
+
+======================== Slowest Corner ==================================
+
+Clock wb_clk_i
+Latency      CRPR       Skew
+_106_/CLK ^
+   4.44
+_107_/CLK ^
+   3.90     -0.24       0.30
+
+
+======================= Typical Corner ===================================
+
+Clock wb_clk_i
+Latency      CRPR       Skew
+_106_/CLK ^
+   0.86
+_107_/CLK ^
+   0.75     -0.05       0.06
+
+
+======================= Fastest Corner ===================================
+
+Clock wb_clk_i
+Latency      CRPR       Skew
+_106_/CLK ^
+   0.40
+_107_/CLK ^
+   0.36     -0.02       0.03
+
+clock_skew_end
+power_report
+
+===========================================================================
+ report_power
+============================================================================
+
+
+======================= Slowest Corner =================================
+
+Group                  Internal  Switching    Leakage      Total
+                          Power      Power      Power      Power (Watts)
+----------------------------------------------------------------
+Sequential             1.91e-05   1.41e-05   3.38e-09   3.32e-05  39.7%
+Combinational          1.73e-05   2.04e-05   1.27e-05   5.04e-05  60.3%
+Macro                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+----------------------------------------------------------------
+Total                  3.64e-05   3.45e-05   1.27e-05   8.36e-05 100.0%
+                          43.5%      41.3%      15.2%
+
+======================= Typical Corner ===================================
+
+Group                  Internal  Switching    Leakage      Total
+                          Power      Power      Power      Power (Watts)
+----------------------------------------------------------------
+Sequential             7.17e-05   5.86e-05   1.98e-09   1.30e-04  44.9%
+Combinational          7.29e-05   8.57e-05   1.28e-06   1.60e-04  55.1%
+Macro                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+----------------------------------------------------------------
+Total                  1.45e-04   1.44e-04   1.28e-06   2.90e-04 100.0%
+                          49.8%      49.7%       0.4%
+
+
+======================= Fastest Corner =================================
+
+Group                  Internal  Switching    Leakage      Total
+                          Power      Power      Power      Power (Watts)
+----------------------------------------------------------------
+Sequential             2.09e-04   1.63e-04   4.84e-09   3.72e-04  42.6%
+Combinational          2.61e-04   2.37e-04   3.55e-06   5.02e-04  57.4%
+Macro                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+----------------------------------------------------------------
+Total                  4.70e-04   4.00e-04   3.56e-06   8.74e-04 100.0%
+                          53.8%      45.8%       0.4%
+power_report_end
+area_report
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 68288 u^2 3% utilization.
+area_report_end
+Setting global connections for newly added cells...
+[WARNING] Did not save OpenROAD database!
+Writing SDF files for all corners...
+Writing SDF for the ff corner to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.ff.sdf...
+Writing SDF for the ss corner to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.ss.sdf...
+Writing SDF for the tt corner to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.tt.sdf...
+Writing timing models for all corners...
+Writing timing models for the ff corner to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.ff.lib...
+Writing timing models for the ss corner to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.ss.lib...
+Writing timing models for the tt corner to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.tt.lib...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/22-rcx_sta.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/22-rcx_sta.log
new file mode 100644
index 0000000..a52a107
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/22-rcx_sta.log
@@ -0,0 +1,672 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+min_report
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.35    1.72    2.49 v _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.22                           net6 (net)
+                  1.36    0.06    2.55 v _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.47    0.58    3.13 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _042_ (net)
+                  0.47    0.00    3.13 ^ _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  1.55    1.04    4.17 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.08                           _017_ (net)
+                  1.55    0.01    4.19 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  4.19   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.10   clock uncertainty
+                         -0.08    1.02   clock reconvergence pessimism
+                         -0.29    0.73   library hold time
+                                  0.73   data required time
+-----------------------------------------------------------------------------
+                                  0.73   data required time
+                                 -4.19   data arrival time
+-----------------------------------------------------------------------------
+                                  3.46   slack (MET)
+
+
+Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.36    1.66    2.43 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.11                           net7 (net)
+                  1.36    0.03    2.46 v _088_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.81    0.74    3.19 ^ _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.02                           _043_ (net)
+                  0.81    0.00    3.19 ^ _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  1.70    1.19    4.38 v _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.10                           _018_ (net)
+                  1.70    0.02    4.40 v _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  4.40   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    1.10   clock uncertainty
+                         -0.08    1.02   clock reconvergence pessimism
+                         -0.35    0.67   library hold time
+                                  0.67   data required time
+-----------------------------------------------------------------------------
+                                  0.67   data required time
+                                 -4.40   data arrival time
+-----------------------------------------------------------------------------
+                                  3.73   slack (MET)
+
+
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34    0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.77 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.44    1.79    2.56 v _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    12    0.23                           net2 (net)
+                  1.44    0.04    2.60 v _058_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  4.10    2.67    5.27 ^ _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.09                           _004_ (net)
+                  4.10    0.02    5.29 ^ _098_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  5.29   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.38    0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00    0.85 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.10   clock uncertainty
+                         -0.08    1.02   clock reconvergence pessimism
+                          0.30    1.32   library hold time
+                                  1.32   data required time
+-----------------------------------------------------------------------------
+                                  1.32   data required time
+                                 -5.29   data arrival time
+-----------------------------------------------------------------------------
+                                  3.97   slack (MET)
+
+
+Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32    0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.75 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.08    2.05    2.81 v _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     4    0.17                           net15 (net)
+                  2.08    0.04    2.84 v _065_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+                  0.47    0.78    3.63 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+     1    0.01                           _031_ (net)
+                  0.47    0.00    3.63 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  1.57    1.05    4.68 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.09                           _007_ (net)
+                  1.57    0.02    4.70 v _101_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  4.70   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.25    1.08   clock uncertainty
+                         -0.08    1.00   clock reconvergence pessimism
+                         -0.33    0.68   library hold time
+                                  0.68   data required time
+-----------------------------------------------------------------------------
+                                  0.68   data required time
+                                 -4.70   data arrival time
+-----------------------------------------------------------------------------
+                                  4.02   slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.10    0.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33    0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32    0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.75 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                  1.24    1.65    2.41 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+    10    0.20                           net21 (net)
+                  1.25    0.07    2.47 v _077_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  0.44    0.51    2.98 ^ _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _037_ (net)
+                  0.44    0.00    2.98 ^ _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  2.61    1.64    4.63 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.13                           _013_ (net)
+                  2.61    0.04    4.66 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                  4.66   data arrival time
+
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock source latency
+                  0.22    0.11    0.11 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00    0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.37    0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00    0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.36    0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00    0.83 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                          0.25    1.08   clock uncertainty
+                         -0.08    1.00   clock reconvergence pessimism
+                         -0.56    0.44   library hold time
+                                  0.44   data required time
+-----------------------------------------------------------------------------
+                                  0.44   data required time
+                                 -4.66   data arrival time
+-----------------------------------------------------------------------------
+                                  4.22   slack (MET)
+
+
+min_report_end
+max_report
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  1.62    1.40   16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  1.63    0.02   16.44 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 18.95   11.96   28.41 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.43                           _012_ (net)
+                 18.95    0.12   28.52 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 28.52   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34   65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00   65.77 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.52   clock uncertainty
+                          0.00   65.52   clock reconvergence pessimism
+                          1.23   66.75   library setup time
+                                 66.75   data required time
+-----------------------------------------------------------------------------
+                                 66.75   data required time
+                                -28.52   data arrival time
+-----------------------------------------------------------------------------
+                                 38.23   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  1.63    1.30   16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  1.63    0.00   16.32 ^ _050_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  1.44    0.51   16.84 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     2    0.02                           _022_ (net)
+                  1.44    0.00   16.84 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                 10.03    6.54   23.38 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.22                           _001_ (net)
+                 10.03    0.07   23.45 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 23.45   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.17    0.32   65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    18    0.06                           clknet_1_1__leaf_wb_clk_i (net)
+                  0.17    0.00   65.75 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.50   clock uncertainty
+                          0.00   65.50   clock reconvergence pessimism
+                          0.26   65.77   library setup time
+                                 65.77   data required time
+-----------------------------------------------------------------------------
+                                 65.77   data required time
+                                -23.45   data arrival time
+-----------------------------------------------------------------------------
+                                 42.32   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  1.62    1.40   16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  1.62    0.02   16.44 v _084_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 10.00    6.59   23.02 ^ _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.23                           _015_ (net)
+                 10.00    0.08   23.10 ^ _109_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 23.10   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34   65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00   65.77 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.52   clock uncertainty
+                          0.00   65.52   clock reconvergence pessimism
+                          0.27   65.79   library setup time
+                                 65.79   data required time
+-----------------------------------------------------------------------------
+                                 65.79   data required time
+                                -23.10   data arrival time
+-----------------------------------------------------------------------------
+                                 42.69   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  1.62    1.40   16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  1.63    0.02   16.45 v _048_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  9.99    6.50   22.95 ^ _048_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.23                           _000_ (net)
+                  9.99    0.05   23.00 ^ _094_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 23.00   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34   65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00   65.77 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.52   clock uncertainty
+                          0.00   65.52   clock reconvergence pessimism
+                          0.27   65.79   library setup time
+                                 65.79   data required time
+-----------------------------------------------------------------------------
+                                 65.79   data required time
+                                -23.00   data arrival time
+-----------------------------------------------------------------------------
+                                 42.79   slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+                  1.63    1.30   16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+    20    0.14                           _021_ (net)
+                  1.63    0.01   16.33 ^ _068_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+                  1.03    0.36   16.69 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+     1    0.01                           _032_ (net)
+                  1.03    0.00   16.69 v _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  9.40    6.08   22.77 ^ _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     2    0.21                           _009_ (net)
+                  9.40    0.06   22.83 ^ _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 22.83   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34   65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00   65.77 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.52   clock uncertainty
+                          0.00   65.52   clock reconvergence pessimism
+                          0.20   65.73   library setup time
+                                 65.73   data required time
+-----------------------------------------------------------------------------
+                                 65.73   data required time
+                                -22.83   data arrival time
+-----------------------------------------------------------------------------
+                                 42.90   slack (MET)
+
+
+max_report_end
+check_report
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                          0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (propagated)
+                         13.00   13.00 ^ input external delay
+                  0.19    0.07   13.07 ^ wb_rst_i (in)
+     2    0.00                           wb_rst_i (net)
+                  0.19    0.00   13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+                  2.79    1.92   14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+     4    0.12                           net1 (net)
+                  2.79    0.03   15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+                  1.62    1.40   16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+    20    0.18                           _020_ (net)
+                  1.63    0.02   16.44 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                 18.95   11.96   28.41 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     2    0.43                           _012_ (net)
+                 18.95    0.12   28.52 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                                 28.52   data arrival time
+
+                         65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock source latency
+                  0.22    0.10   65.10 ^ wb_clk_i (in)
+     2    0.03                           wb_clk_i (net)
+                  0.22    0.00   65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.15    0.33   65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+     2    0.05                           clknet_0_wb_clk_i (net)
+                  0.15    0.00   65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+                  0.19    0.34   65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+    22    0.08                           clknet_1_0__leaf_wb_clk_i (net)
+                  0.19    0.00   65.77 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+                         -0.25   65.52   clock uncertainty
+                          0.00   65.52   clock reconvergence pessimism
+                          1.23   66.75   library setup time
+                                 66.75   data required time
+-----------------------------------------------------------------------------
+                                 66.75   data required time
+                                -28.52   data arrival time
+-----------------------------------------------------------------------------
+                                 38.23   slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
+check_report_end
+check_slew
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+max slew
+
+Pin                                    Limit    Slew   Slack
+------------------------------------------------------------
+ANTENNA__106__D/I                       8.60   18.95  -10.35 (VIOLATED)
+_106_/D                                 8.60   18.95  -10.35 (VIOLATED)
+_076_/ZN                                8.60   18.95  -10.35 (VIOLATED)
+_095_/D                                 8.60   10.03   -1.43 (VIOLATED)
+ANTENNA__095__D/I                       8.60   10.03   -1.43 (VIOLATED)
+_051_/ZN                                8.60   10.03   -1.43 (VIOLATED)
+_109_/D                                 8.60   10.00   -1.40 (VIOLATED)
+ANTENNA__109__D/I                       8.60   10.00   -1.40 (VIOLATED)
+_084_/ZN                                8.60   10.00   -1.40 (VIOLATED)
+_094_/D                                 8.60    9.99   -1.39 (VIOLATED)
+ANTENNA__094__D/I                       8.60    9.99   -1.39 (VIOLATED)
+_048_/ZN                                8.60    9.99   -1.39 (VIOLATED)
+_103_/D                                 8.60    9.40   -0.80 (VIOLATED)
+ANTENNA__103__D/I                       8.60    9.40   -0.80 (VIOLATED)
+_069_/ZN                                8.60    9.40   -0.80 (VIOLATED)
+
+max capacitance
+
+Pin                                    Limit     Cap   Slack
+------------------------------------------------------------
+_076_/ZN                                0.18    0.43   -0.25 (VIOLATED)
+_084_/ZN                                0.18    0.23   -0.04 (VIOLATED)
+_048_/ZN                                0.18    0.23   -0.04 (VIOLATED)
+_051_/ZN                                0.18    0.22   -0.04 (VIOLATED)
+_069_/ZN                                0.18    0.21   -0.03 (VIOLATED)
+_082_/ZN                                0.18    0.19   -0.01 (VIOLATED)
+_060_/ZN                                0.18    0.19   -0.01 (VIOLATED)
+_064_/ZN                                0.18    0.19   -0.01 (VIOLATED)
+_075_/ZN                                0.18    0.19   -0.00 (VIOLATED)
+
+
+===========================================================================
+max slew violation count 15
+max fanout violation count 0
+max cap violation count 9
+============================================================================
+check_slew_end
+tns_report
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
+tns_report_end
+wns_report
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
+wns_report_end
+worst_slack
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 38.23
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 3.46
+worst_slack_end
+clock_skew
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency      CRPR       Skew
+_106_/CLK ^
+   0.86
+_107_/CLK ^
+   0.75     -0.05       0.06
+
+clock_skew_end
+power_report
+
+===========================================================================
+ report_power
+============================================================================
+Group                  Internal  Switching    Leakage      Total
+                          Power      Power      Power      Power (Watts)
+----------------------------------------------------------------
+Sequential             7.17e-05   5.86e-05   1.98e-09   1.30e-04  44.9%
+Combinational          7.29e-05   8.57e-05   1.28e-06   1.60e-04  55.1%
+Macro                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+----------------------------------------------------------------
+Total                  1.45e-04   1.44e-04   1.28e-06   2.90e-04 100.0%
+                          49.8%      49.7%       0.4%
+power_report_end
+area_report
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 68288 u^2 3% utilization.
+area_report_end
+Setting global connections for newly added cells...
+[WARNING] Did not save OpenROAD database!
+Writing SDF to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.sdf...
+Writing timing model to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.lib...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/23-gds_ptrs.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/23-gds_ptrs.log
new file mode 100644
index 0000000..026aa90
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/23-gds_ptrs.log
@@ -0,0 +1,150 @@
+
+Magic 8.3 revision 331 - Compiled on Sat Oct 22 18:40:56 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology gf180mcuC ...
+10 Magic internal units = 1 Lambda
+Input style import: scaleFactor=10, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    obsactive mvobsactive filldiff fillpoly m1hole obsm1 fillm1 obsv1 m2hole obsm2 fillm2 obsv2 m3hole obsm3 fillm3 m4hole obsm4 fillm4 m5hole obsm5 fillm5 glass fillblock lvstext obscomment 
+Scaled tech values by 10 / 1 to match internal grid scaling
+Loading gf180mcuC Device Generator Menu ...
+Using technology "gf180mcuC", version 1.0.349-0-g0059588
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: cntr_example
+Reading "gf180mcu_fd_sc_mcu7t5v0__tiel".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Reading "gf180mcu_fd_sc_mcu7t5v0__endcap".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_16".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_8".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fill_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__filltie".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_64".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_32".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fill_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__antenna".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_3".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi21_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand3_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai21_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__xor2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__xor2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__xor2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__xor2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__xor2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffq_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffq_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Reading "cntr_example".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+[INFO]: Wrote /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/gds_ptrs.mag including GDS pointers.
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/23-gdsii.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/23-gdsii.log
new file mode 100644
index 0000000..e0c066d
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/23-gdsii.log
@@ -0,0 +1,95 @@
+
+Magic 8.3 revision 331 - Compiled on Sat Oct 22 18:40:56 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology gf180mcuC ...
+10 Magic internal units = 1 Lambda
+Input style import: scaleFactor=10, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    obsactive mvobsactive filldiff fillpoly m1hole obsm1 fillm1 obsv1 m2hole obsm2 fillm2 obsv2 m3hole obsm3 fillm3 m4hole obsm4 fillm4 m5hole obsm5 fillm5 glass fillblock lvstext obscomment 
+Scaled tech values by 10 / 1 to match internal grid scaling
+Loading gf180mcuC Device Generator Menu ...
+Using technology "gf180mcuC", version 1.0.349-0-g0059588
+Reading LEF data from file /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef.
+This action cannot be undone.
+LEF read, Line 78 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 85 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 95 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 96 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 110 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 114 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 126 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 133 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 134 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 135 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 144 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 145 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 161 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 165 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 177 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 184 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 185 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 186 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 195 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 196 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 212 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 216 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 228 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 235 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 236 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 237 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 246 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 247 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 264 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 268 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 282 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 294 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 295 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 296 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 301 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 302 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read: Processed 1366 lines.
+Reading DEF data from file /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def.
+This action cannot be undone.
+  Processed 3 vias total.
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_1 geometry by factor of 2
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_2 geometry by factor of 2
+  Processed 58369 subcell instances total.
+  Processed 42 pins total.
+  Processed 2 special nets total.
+  Processed 111 nets total.
+DEF read: Processed 72758 lines.
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  1500.000 x 1500.000  ( 0.000,  0.000), ( 1500.000,  1500.000)  2250000.000
+lambda:   30000.00 x 30000.00  (  0.00,  0.00 ), ( 30000.00,  30000.00)  900000064.00
+internal: 300000 x 300000  (     0,  0    ), ( 300000,  300000)  90000000000
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__tiel
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__endcap
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fill_1
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__filltie
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fill_2
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__antenna
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__buf_1
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nand2_1
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nand3_1
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nor2_1
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__oai21_1
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__xor2_1
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__buf_2
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffq_1
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffq_2
+   Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16
+   Generating output for cell cntr_example
+[INFO]: GDS Write Complete
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/23-lef.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/23-lef.log
new file mode 100644
index 0000000..90f5135
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/23-lef.log
@@ -0,0 +1,148 @@
+
+Magic 8.3 revision 331 - Compiled on Sat Oct 22 18:40:56 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology gf180mcuC ...
+10 Magic internal units = 1 Lambda
+Input style import: scaleFactor=10, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    obsactive mvobsactive filldiff fillpoly m1hole obsm1 fillm1 obsv1 m2hole obsm2 fillm2 obsv2 m3hole obsm3 fillm3 m4hole obsm4 fillm4 m5hole obsm5 fillm5 glass fillblock lvstext obscomment 
+Scaled tech values by 10 / 1 to match internal grid scaling
+Loading gf180mcuC Device Generator Menu ...
+Using technology "gf180mcuC", version 1.0.349-0-g0059588
+Reading LEF data from file /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef.
+This action cannot be undone.
+LEF read, Line 78 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 85 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 95 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 96 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 110 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 114 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 126 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 133 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 134 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 135 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 144 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 145 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 161 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 165 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 177 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 184 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 185 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 186 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 195 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 196 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 212 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 216 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 228 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 235 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 236 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 237 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 246 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 247 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 264 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 268 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 282 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 294 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 295 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 296 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 301 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 302 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read: Processed 1366 lines.
+cntr_example: 10000 rects
+cntr_example: 20000 rects
+cntr_example: 30000 rects
+cntr_example: 40000 rects
+cntr_example: 50000 rects
+cntr_example: 60000 rects
+cntr_example: 70000 rects
+cntr_example: 80000 rects
+cntr_example: 90000 rects
+cntr_example: 100000 rects
+cntr_example: 110000 rects
+cntr_example: 120000 rects
+cntr_example: 130000 rects
+cntr_example: 140000 rects
+[INFO]: Writing abstract LEF
+Generating LEF output /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/cntr_example.lef for cell cntr_example:
+Diagnostic:  Write LEF header for cell cntr_example
+Diagnostic:  Writing LEF output for cell cntr_example
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_4" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__buf_1" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__buf_1.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__buf_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__tiel" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__tiel.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__tiel.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffq_1" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__dffq_1.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__dffq_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffq_2" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__dffq_2.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__dffq_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nor2_1" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__nor2_1.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__nor2_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__xor2_1" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__xor2_1.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__xor2_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nand2_1" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__nand2_1.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__nand2_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nand3_1" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__nand3_1.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__nand3_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__aoi21_1" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__aoi21_1.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__aoi21_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai21_1" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__oai21_1.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__oai21_1.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__buf_2" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__buf_2.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__buf_2.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkinv_3" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__clkinv_3.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__clkinv_3.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__filltie" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__filltie.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__filltie.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__endcap" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__endcap.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__endcap.mag.
+The discovered version will be used.
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__endcap geometry by factor of 2
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fill_1" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fill_1.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fill_1.mag.
+The discovered version will be used.
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_1 geometry by factor of 2
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fill_2" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fill_2.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fill_2.mag.
+The discovered version will be used.
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_2 geometry by factor of 2
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_4" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_4.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fillcap_4.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_32" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_32.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fillcap_32.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_8" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_8.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fillcap_8.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_16" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_64" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_64.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fillcap_64.mag.
+The discovered version will be used.
+Warning:  Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__antenna" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__antenna.mag.
+The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__antenna.mag.
+The discovered version will be used.
+Diagnostic:  Scale value is 0.005000
+[INFO]: LEF Write Complete
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/23-maglef.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/23-maglef.log
new file mode 100644
index 0000000..5ac081d
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/23-maglef.log
@@ -0,0 +1,18 @@
+
+Magic 8.3 revision 331 - Compiled on Sat Oct 22 18:40:56 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology gf180mcuC ...
+10 Magic internal units = 1 Lambda
+Input style import: scaleFactor=10, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    obsactive mvobsactive filldiff fillpoly m1hole obsm1 fillm1 obsv1 m2hole obsm2 fillm2 obsv2 m3hole obsm3 fillm3 m4hole obsm4 fillm4 m5hole obsm5 fillm5 glass fillblock lvstext obscomment 
+Scaled tech values by 10 / 1 to match internal grid scaling
+Loading gf180mcuC Device Generator Menu ...
+Using technology "gf180mcuC", version 1.0.349-0-g0059588
+Reading LEF data from file /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/cntr_example.lef.
+This action cannot be undone.
+LEF read: Processed 470 lines.
+[INFO]: DONE GENERATING MAGLEF VIEW
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/24-spice.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/24-spice.log
new file mode 100644
index 0000000..9301061
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/24-spice.log
@@ -0,0 +1,91 @@
+
+Magic 8.3 revision 331 - Compiled on Sat Oct 22 18:40:56 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology gf180mcuC ...
+10 Magic internal units = 1 Lambda
+Input style import: scaleFactor=10, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    obsactive mvobsactive filldiff fillpoly m1hole obsm1 fillm1 obsv1 m2hole obsm2 fillm2 obsv2 m3hole obsm3 fillm3 m4hole obsm4 fillm4 m5hole obsm5 fillm5 glass fillblock lvstext obscomment 
+Scaled tech values by 10 / 1 to match internal grid scaling
+Loading gf180mcuC Device Generator Menu ...
+Using technology "gf180mcuC", version 1.0.349-0-g0059588
+Reading LEF data from file /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef.
+This action cannot be undone.
+LEF read, Line 78 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 85 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 95 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 96 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 110 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 114 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 126 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 133 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 134 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 135 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 144 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 145 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 161 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 165 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 177 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 184 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 185 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 186 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 195 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 196 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 212 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 216 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 228 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 235 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 236 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 237 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 246 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 247 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 264 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 268 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 282 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 294 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 295 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 296 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 301 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 302 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read: Processed 1366 lines.
+Reading DEF data from file /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def.
+This action cannot be undone.
+  Processed 3 vias total.
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_1 geometry by factor of 2
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_2 geometry by factor of 2
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__endcap geometry by factor of 2
+  Processed 58369 subcell instances total.
+  Processed 42 pins total.
+  Processed 2 special nets total.
+  Processed 111 nets total.
+DEF read: Processed 72758 lines.
+Processing cntr_example
+Extracting gf180mcu_fd_sc_mcu7t5v0__tiel into gf180mcu_fd_sc_mcu7t5v0__tiel.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__endcap into gf180mcu_fd_sc_mcu7t5v0__endcap.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__fillcap_16 into gf180mcu_fd_sc_mcu7t5v0__fillcap_16.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__fillcap_4 into gf180mcu_fd_sc_mcu7t5v0__fillcap_4.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__fillcap_8 into gf180mcu_fd_sc_mcu7t5v0__fillcap_8.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__fill_1 into gf180mcu_fd_sc_mcu7t5v0__fill_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__filltie into gf180mcu_fd_sc_mcu7t5v0__filltie.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__fillcap_32 into gf180mcu_fd_sc_mcu7t5v0__fillcap_32.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__fillcap_64 into gf180mcu_fd_sc_mcu7t5v0__fillcap_64.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__fill_2 into gf180mcu_fd_sc_mcu7t5v0__fill_2.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__antenna into gf180mcu_fd_sc_mcu7t5v0__antenna.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 into gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__buf_1 into gf180mcu_fd_sc_mcu7t5v0__buf_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__clkinv_3 into gf180mcu_fd_sc_mcu7t5v0__clkinv_3.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__aoi21_1 into gf180mcu_fd_sc_mcu7t5v0__aoi21_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__nand2_1 into gf180mcu_fd_sc_mcu7t5v0__nand2_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__nand3_1 into gf180mcu_fd_sc_mcu7t5v0__nand3_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__nor2_1 into gf180mcu_fd_sc_mcu7t5v0__nor2_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__oai21_1 into gf180mcu_fd_sc_mcu7t5v0__oai21_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__xor2_1 into gf180mcu_fd_sc_mcu7t5v0__xor2_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__buf_2 into gf180mcu_fd_sc_mcu7t5v0__buf_2.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__dffq_1 into gf180mcu_fd_sc_mcu7t5v0__dffq_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__dffq_2 into gf180mcu_fd_sc_mcu7t5v0__dffq_2.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 into gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.ext:
+Extracting cntr_example into cntr_example.ext:
+exttospice finished.
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/25-write_powered_def.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/25-write_powered_def.log
new file mode 100644
index 0000000..62b684f
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/25-write_powered_def.log
@@ -0,0 +1,21 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO ODB-0222] Reading LEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef
+[INFO ODB-0223]     Created 13 technology layers
+[INFO ODB-0224]     Created 60 technology vias
+[INFO ODB-0225]     Created 229 library cells
+[INFO ODB-0226] Finished LEF file:  /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef
+[INFO ODB-0127] Reading DEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def
+[INFO ODB-0128] Design: cntr_example
+[INFO ODB-0130]     Created 42 pins.
+[INFO ODB-0131]     Created 58369 components and 117183 component-terminals.
+[INFO ODB-0132]     Created 2 special nets and 116738 connections.
+[INFO ODB-0133]     Created 111 nets and 445 connections.
+[INFO ODB-0134] Finished DEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def
+Top-level design name: cntr_example
+Found default power net 'vdd'
+Found default ground net 'vss'
+Found 1 power ports.
+Found 1 ground ports.
+Modified power connections of 58369/58369 cells.
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/25-write_powered_verilog.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/25-write_powered_verilog.log
new file mode 100644
index 0000000..ad665d3
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/25-write_powered_verilog.log
@@ -0,0 +1,7 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Setting global connections for newly added cells...
+[WARNING] Did not save OpenROAD database!
+Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.pnl.v...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/27-cntr_example.lef.lvs.json b/openlane/cntr_example/runs/cntr_example/logs/signoff/27-cntr_example.lef.lvs.json
new file mode 100644
index 0000000..d8e9ff2
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/27-cntr_example.lef.lvs.json
@@ -0,0 +1,448 @@
+[
+  {
+   "pins": [
+      [
+        "VDD",
+        "VSS"
+      ], [
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "VDD",
+        "VSS"
+      ], [
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "VDD",
+        "VSS"
+      ], [
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "VDD",
+        "VSS"
+      ], [
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "VDD",
+        "VSS"
+      ], [
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "A1",
+        "A2",
+        "A3",
+        "ZN",
+        "VDD",
+        "VSS"
+      ], [
+        "A1",
+        "A2",
+        "A3",
+        "ZN",
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "I",
+        "VDD",
+        "VSS"
+      ], [
+        "I",
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "I",
+        "Z",
+        "VDD",
+        "VSS"
+      ], [
+        "I",
+        "Z",
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "A1",
+        "A2",
+        "B",
+        "ZN",
+        "VDD",
+        "VSS"
+      ], [
+        "A1",
+        "A2",
+        "B",
+        "ZN",
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "D",
+        "CLK",
+        "Q",
+        "VDD",
+        "VSS"
+      ], [
+        "D",
+        "CLK",
+        "Q",
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "ZN",
+        "VDD",
+        "VSS"
+      ], [
+        "ZN",
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "D",
+        "CLK",
+        "Q",
+        "VDD",
+        "VSS"
+      ], [
+        "D",
+        "CLK",
+        "Q",
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "A1",
+        "A2",
+        "B",
+        "ZN",
+        "VDD",
+        "VSS"
+      ], [
+        "A1",
+        "A2",
+        "B",
+        "ZN",
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "A1",
+        "A2",
+        "ZN",
+        "VDD",
+        "VSS"
+      ], [
+        "A1",
+        "A2",
+        "ZN",
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "I",
+        "Z",
+        "VDD",
+        "VSS"
+      ], [
+        "I",
+        "Z",
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "A1",
+        "A2",
+        "Z",
+        "VDD",
+        "VSS"
+      ], [
+        "A1",
+        "A2",
+        "Z",
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "A1",
+        "A2",
+        "ZN",
+        "VDD",
+        "VSS"
+      ], [
+        "A1",
+        "A2",
+        "ZN",
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "I",
+        "Z",
+        "VDD",
+        "VSS"
+      ], [
+        "I",
+        "Z",
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "I",
+        "Z",
+        "VDD",
+        "VSS"
+      ], [
+        "I",
+        "Z",
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "pins": [
+      [
+        "I",
+        "ZN",
+        "VDD",
+        "VSS"
+      ], [
+        "I",
+        "ZN",
+        "VDD",
+        "VSS"
+      ]
+   ]
+  },
+  {
+   "name": [
+      "cntr_example",
+      "cntr_example"
+   ],
+   "devices": [
+       [
+         ["gf180mcu_fd_sc_mcu7t5v0__fillcap_4", 1],
+         ["gf180mcu_fd_sc_mcu7t5v0__fillcap_64", 1],
+         ["gf180mcu_fd_sc_mcu7t5v0__fillcap_32", 1],
+         ["gf180mcu_fd_sc_mcu7t5v0__fillcap_16", 1],
+         ["gf180mcu_fd_sc_mcu7t5v0__fillcap_8", 1],
+         ["gf180mcu_fd_sc_mcu7t5v0__nand3_1", 5],
+         ["gf180mcu_fd_sc_mcu7t5v0__antenna", 60],
+         ["gf180mcu_fd_sc_mcu7t5v0__clkbuf_4", 20],
+         ["gf180mcu_fd_sc_mcu7t5v0__aoi21_1", 10],
+         ["gf180mcu_fd_sc_mcu7t5v0__dffq_1", 5],
+         ["gf180mcu_fd_sc_mcu7t5v0__tiel", 18],
+         ["gf180mcu_fd_sc_mcu7t5v0__dffq_2", 15],
+         ["gf180mcu_fd_sc_mcu7t5v0__oai21_1", 5],
+         ["gf180mcu_fd_sc_mcu7t5v0__nor2_1", 15],
+         ["gf180mcu_fd_sc_mcu7t5v0__buf_1", 1],
+         ["gf180mcu_fd_sc_mcu7t5v0__xor2_1", 5],
+         ["gf180mcu_fd_sc_mcu7t5v0__nand2_1", 5],
+         ["gf180mcu_fd_sc_mcu7t5v0__clkbuf_16", 3],
+         ["gf180mcu_fd_sc_mcu7t5v0__buf_2", 1],
+         ["gf180mcu_fd_sc_mcu7t5v0__clkinv_3", 1 ]
+       ], [
+         ["gf180mcu_fd_sc_mcu7t5v0__fillcap_4", 1 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__fillcap_64", 1 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__fillcap_32", 1 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__fillcap_16", 1 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__fillcap_8", 1 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__nand3_1", 5 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__antenna", 60 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__clkbuf_4", 20 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__aoi21_1", 10 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__dffq_1", 5 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__tiel", 18 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__dffq_2", 15 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__oai21_1", 5 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__nor2_1", 15 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__buf_1", 1 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__xor2_1", 5 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__nand2_1", 5 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__clkbuf_16", 3 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__buf_2", 1 ],
+         ["gf180mcu_fd_sc_mcu7t5v0__clkinv_3", 1 ]
+       ]
+   ],
+   "nets": [
+    113,
+    113
+   ],
+   "badnets": [
+   ],
+   "badelements": [
+   ],
+   "pins": [
+      [
+        "wb_clk_i",
+        "wb_rst_i",
+        "io_out[10]",
+        "io_out[6]",
+        "io_out[2]",
+        "io_out[18]",
+        "io_out[14]",
+        "io_out[11]",
+        "io_out[7]",
+        "io_out[19]",
+        "io_out[3]",
+        "io_out[15]",
+        "io_out[12]",
+        "io_out[4]",
+        "io_out[16]",
+        "io_out[0]",
+        "io_out[8]",
+        "io_out[13]",
+        "io_out[5]",
+        "io_out[1]",
+        "io_out[9]",
+        "io_out[17]",
+        "io_out[27]",
+        "io_out[37]",
+        "io_out[26]",
+        "io_out[36]",
+        "io_out[25]",
+        "io_out[35]",
+        "io_out[24]",
+        "io_out[34]",
+        "io_out[23]",
+        "io_out[33]",
+        "io_out[22]",
+        "io_out[32]",
+        "io_out[21]",
+        "io_out[31]",
+        "io_out[20]",
+        "io_out[30]",
+        "io_out[29]",
+        "io_out[28]",
+        "vdd",
+        "vss"
+      ], [
+        "wb_clk_i",
+        "wb_rst_i",
+        "io_out[10]",
+        "io_out[6]",
+        "io_out[2]",
+        "io_out[18]",
+        "io_out[14]",
+        "io_out[11]",
+        "io_out[7]",
+        "io_out[19]",
+        "io_out[3]",
+        "io_out[15]",
+        "io_out[12]",
+        "io_out[4]",
+        "io_out[16]",
+        "io_out[0]",
+        "io_out[8]",
+        "io_out[13]",
+        "io_out[5]",
+        "io_out[1]",
+        "io_out[9]",
+        "io_out[17]",
+        "io_out[27]",
+        "io_out[37]",
+        "io_out[26]",
+        "io_out[36]",
+        "io_out[25]",
+        "io_out[35]",
+        "io_out[24]",
+        "io_out[34]",
+        "io_out[23]",
+        "io_out[33]",
+        "io_out[22]",
+        "io_out[32]",
+        "io_out[21]",
+        "io_out[31]",
+        "io_out[20]",
+        "io_out[30]",
+        "io_out[29]",
+        "io_out[28]",
+        "vdd",
+        "vss"
+      ]
+   ]
+  }
+]
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/27-cntr_example.lef.lvs.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/27-cntr_example.lef.lvs.log
new file mode 100644
index 0000000..f714c6d
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/27-cntr_example.lef.lvs.log
@@ -0,0 +1,422 @@
+
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__fillca |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__fillca 
+-------------------------------------------|-------------------------------------------
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__fillcap_4 and gf180mcu_fd_sc_mcu7t5v0__fillcap_4 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64 (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__fillca |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__fillca 
+-------------------------------------------|-------------------------------------------
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__fillcap_64 and gf180mcu_fd_sc_mcu7t5v0__fillcap_64 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32 (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__fillca |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__fillca 
+-------------------------------------------|-------------------------------------------
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__fillcap_32 and gf180mcu_fd_sc_mcu7t5v0__fillcap_32 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16 (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__fillca |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__fillca 
+-------------------------------------------|-------------------------------------------
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__fillcap_16 and gf180mcu_fd_sc_mcu7t5v0__fillcap_16 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8 (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__fillca |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__fillca 
+-------------------------------------------|-------------------------------------------
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__fillcap_8 and gf180mcu_fd_sc_mcu7t5v0__fillcap_8 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__nand3_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__nand3_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__nand3_1 (0) disconnected node: A3
+Cell gf180mcu_fd_sc_mcu7t5v0__nand3_1 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__nand3_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__nand3_1 (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__nand3_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__nand3_ |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__nand3_ 
+-------------------------------------------|-------------------------------------------
+A1                                         |A1                                         
+A2                                         |A2                                         
+A3                                         |A3                                         
+ZN                                         |ZN                                         
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__nand3_1 and gf180mcu_fd_sc_mcu7t5v0__nand3_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__antenna (0) disconnected node: I
+Cell gf180mcu_fd_sc_mcu7t5v0__antenna (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__antenna (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__antenna is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__antenn |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__antenn 
+-------------------------------------------|-------------------------------------------
+I                                          |I                                          
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__antenna and gf180mcu_fd_sc_mcu7t5v0__antenna are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 (0) disconnected node: I
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 (0) disconnected node: Z
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__clkbuf |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__clkbuf 
+-------------------------------------------|-------------------------------------------
+I                                          |I                                          
+Z                                          |Z                                          
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 and gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1 (0) disconnected node: B
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1 (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__aoi21_ |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__aoi21_ 
+-------------------------------------------|-------------------------------------------
+A1                                         |A1                                         
+A2                                         |A2                                         
+B                                          |B                                          
+ZN                                         |ZN                                         
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__aoi21_1 and gf180mcu_fd_sc_mcu7t5v0__aoi21_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__dffq_1 (0) disconnected node: D
+Cell gf180mcu_fd_sc_mcu7t5v0__dffq_1 (0) disconnected node: CLK
+Cell gf180mcu_fd_sc_mcu7t5v0__dffq_1 (0) disconnected node: Q
+Cell gf180mcu_fd_sc_mcu7t5v0__dffq_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__dffq_1 (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__dffq_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__dffq_1 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__dffq_1 
+-------------------------------------------|-------------------------------------------
+D                                          |D                                          
+CLK                                        |CLK                                        
+Q                                          |Q                                          
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__dffq_1 and gf180mcu_fd_sc_mcu7t5v0__dffq_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__tiel (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__tiel (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__tiel (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__tiel is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__tiel   |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__tiel   
+-------------------------------------------|-------------------------------------------
+ZN                                         |ZN                                         
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__tiel and gf180mcu_fd_sc_mcu7t5v0__tiel are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__dffq_2 (0) disconnected node: D
+Cell gf180mcu_fd_sc_mcu7t5v0__dffq_2 (0) disconnected node: CLK
+Cell gf180mcu_fd_sc_mcu7t5v0__dffq_2 (0) disconnected node: Q
+Cell gf180mcu_fd_sc_mcu7t5v0__dffq_2 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__dffq_2 (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__dffq_2 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__dffq_2 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__dffq_2 
+-------------------------------------------|-------------------------------------------
+D                                          |D                                          
+CLK                                        |CLK                                        
+Q                                          |Q                                          
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__dffq_2 and gf180mcu_fd_sc_mcu7t5v0__dffq_2 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__oai21_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__oai21_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__oai21_1 (0) disconnected node: B
+Cell gf180mcu_fd_sc_mcu7t5v0__oai21_1 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__oai21_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__oai21_1 (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__oai21_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__oai21_ |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__oai21_ 
+-------------------------------------------|-------------------------------------------
+A1                                         |A1                                         
+A2                                         |A2                                         
+B                                          |B                                          
+ZN                                         |ZN                                         
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__oai21_1 and gf180mcu_fd_sc_mcu7t5v0__oai21_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__nor2_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__nor2_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__nor2_1 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__nor2_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__nor2_1 (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__nor2_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__nor2_1 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__nor2_1 
+-------------------------------------------|-------------------------------------------
+A1                                         |A1                                         
+A2                                         |A2                                         
+ZN                                         |ZN                                         
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__nor2_1 and gf180mcu_fd_sc_mcu7t5v0__nor2_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__buf_1 (0) disconnected node: I
+Cell gf180mcu_fd_sc_mcu7t5v0__buf_1 (0) disconnected node: Z
+Cell gf180mcu_fd_sc_mcu7t5v0__buf_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__buf_1 (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__buf_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__buf_1  |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__buf_1  
+-------------------------------------------|-------------------------------------------
+I                                          |I                                          
+Z                                          |Z                                          
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__buf_1 and gf180mcu_fd_sc_mcu7t5v0__buf_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__xor2_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__xor2_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__xor2_1 (0) disconnected node: Z
+Cell gf180mcu_fd_sc_mcu7t5v0__xor2_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__xor2_1 (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__xor2_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__xor2_1 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__xor2_1 
+-------------------------------------------|-------------------------------------------
+A1                                         |A1                                         
+A2                                         |A2                                         
+Z                                          |Z                                          
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__xor2_1 and gf180mcu_fd_sc_mcu7t5v0__xor2_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__nand2_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__nand2_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__nand2_1 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__nand2_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__nand2_1 (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__nand2_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__nand2_ |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__nand2_ 
+-------------------------------------------|-------------------------------------------
+A1                                         |A1                                         
+A2                                         |A2                                         
+ZN                                         |ZN                                         
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__nand2_1 and gf180mcu_fd_sc_mcu7t5v0__nand2_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 (0) disconnected node: I
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 (0) disconnected node: Z
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__clkbuf |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__clkbuf 
+-------------------------------------------|-------------------------------------------
+I                                          |I                                          
+Z                                          |Z                                          
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 and gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__buf_2 (0) disconnected node: I
+Cell gf180mcu_fd_sc_mcu7t5v0__buf_2 (0) disconnected node: Z
+Cell gf180mcu_fd_sc_mcu7t5v0__buf_2 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__buf_2 (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__buf_2 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__buf_2  |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__buf_2  
+-------------------------------------------|-------------------------------------------
+I                                          |I                                          
+Z                                          |Z                                          
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__buf_2 and gf180mcu_fd_sc_mcu7t5v0__buf_2 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3 (0) disconnected node: I
+Cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3 (0) disconnected node: VSS
+Warning: Equate pins:  cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__clkinv |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__clkinv 
+-------------------------------------------|-------------------------------------------
+I                                          |I                                          
+ZN                                         |ZN                                         
+VDD                                        |VDD                                        
+VSS                                        |VSS                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__clkinv_3 and gf180mcu_fd_sc_mcu7t5v0__clkinv_3 are equivalent.
+
+Class cntr_example (0):  Merged 28627 parallel devices.
+Class cntr_example (1):  Merged 28627 parallel devices.
+Subcircuit summary:
+Circuit 1: cntr_example                    |Circuit 2: cntr_example                    
+-------------------------------------------|-------------------------------------------
+gf180mcu_fd_sc_mcu7t5v0__fillcap_4 (13770- |gf180mcu_fd_sc_mcu7t5v0__fillcap_4 (13770- 
+gf180mcu_fd_sc_mcu7t5v0__fillcap_64 (13503 |gf180mcu_fd_sc_mcu7t5v0__fillcap_64 (13503 
+gf180mcu_fd_sc_mcu7t5v0__fillcap_32 (547-> |gf180mcu_fd_sc_mcu7t5v0__fillcap_32 (547-> 
+gf180mcu_fd_sc_mcu7t5v0__fillcap_16 (438-> |gf180mcu_fd_sc_mcu7t5v0__fillcap_16 (438-> 
+gf180mcu_fd_sc_mcu7t5v0__fillcap_8 (274->1 |gf180mcu_fd_sc_mcu7t5v0__fillcap_8 (274->1 
+gf180mcu_fd_sc_mcu7t5v0__nand3_1 (5)       |gf180mcu_fd_sc_mcu7t5v0__nand3_1 (5)       
+gf180mcu_fd_sc_mcu7t5v0__antenna (160->60) |gf180mcu_fd_sc_mcu7t5v0__antenna (160->60) 
+gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 (20)     |gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 (20)     
+gf180mcu_fd_sc_mcu7t5v0__aoi21_1 (10)      |gf180mcu_fd_sc_mcu7t5v0__aoi21_1 (10)      
+gf180mcu_fd_sc_mcu7t5v0__dffq_1 (5)        |gf180mcu_fd_sc_mcu7t5v0__dffq_1 (5)        
+gf180mcu_fd_sc_mcu7t5v0__tiel (18)         |gf180mcu_fd_sc_mcu7t5v0__tiel (18)         
+gf180mcu_fd_sc_mcu7t5v0__dffq_2 (15)       |gf180mcu_fd_sc_mcu7t5v0__dffq_2 (15)       
+gf180mcu_fd_sc_mcu7t5v0__oai21_1 (5)       |gf180mcu_fd_sc_mcu7t5v0__oai21_1 (5)       
+gf180mcu_fd_sc_mcu7t5v0__nor2_1 (15)       |gf180mcu_fd_sc_mcu7t5v0__nor2_1 (15)       
+gf180mcu_fd_sc_mcu7t5v0__buf_1 (1)         |gf180mcu_fd_sc_mcu7t5v0__buf_1 (1)         
+gf180mcu_fd_sc_mcu7t5v0__xor2_1 (5)        |gf180mcu_fd_sc_mcu7t5v0__xor2_1 (5)        
+gf180mcu_fd_sc_mcu7t5v0__nand2_1 (5)       |gf180mcu_fd_sc_mcu7t5v0__nand2_1 (5)       
+gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 (3)     |gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 (3)     
+gf180mcu_fd_sc_mcu7t5v0__buf_2 (1)         |gf180mcu_fd_sc_mcu7t5v0__buf_2 (1)         
+gf180mcu_fd_sc_mcu7t5v0__clkinv_3 (1)      |gf180mcu_fd_sc_mcu7t5v0__clkinv_3 (1)      
+Number of devices: 174                     |Number of devices: 174                     
+Number of nets: 113                        |Number of nets: 113                        
+---------------------------------------------------------------------------------------
+Resolving symmetries by property value.
+Resolving symmetries by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: cntr_example                    |Circuit 2: cntr_example                    
+-------------------------------------------|-------------------------------------------
+wb_clk_i                                   |wb_clk_i                                   
+wb_rst_i                                   |wb_rst_i                                   
+io_out[10]                                 |io_out[10]                                 
+io_out[6]                                  |io_out[6]                                  
+io_out[2]                                  |io_out[2]                                  
+io_out[18]                                 |io_out[18]                                 
+io_out[14]                                 |io_out[14]                                 
+io_out[11]                                 |io_out[11]                                 
+io_out[7]                                  |io_out[7]                                  
+io_out[19]                                 |io_out[19]                                 
+io_out[3]                                  |io_out[3]                                  
+io_out[15]                                 |io_out[15]                                 
+io_out[12]                                 |io_out[12]                                 
+io_out[4]                                  |io_out[4]                                  
+io_out[16]                                 |io_out[16]                                 
+io_out[0]                                  |io_out[0]                                  
+io_out[8]                                  |io_out[8]                                  
+io_out[13]                                 |io_out[13]                                 
+io_out[5]                                  |io_out[5]                                  
+io_out[1]                                  |io_out[1]                                  
+io_out[9]                                  |io_out[9]                                  
+io_out[17]                                 |io_out[17]                                 
+io_out[27]                                 |io_out[27]                                 
+io_out[37]                                 |io_out[37]                                 
+io_out[26]                                 |io_out[26]                                 
+io_out[36]                                 |io_out[36]                                 
+io_out[25]                                 |io_out[25]                                 
+io_out[35]                                 |io_out[35]                                 
+io_out[24]                                 |io_out[24]                                 
+io_out[34]                                 |io_out[34]                                 
+io_out[23]                                 |io_out[23]                                 
+io_out[33]                                 |io_out[33]                                 
+io_out[22]                                 |io_out[22]                                 
+io_out[32]                                 |io_out[32]                                 
+io_out[21]                                 |io_out[21]                                 
+io_out[31]                                 |io_out[31]                                 
+io_out[20]                                 |io_out[20]                                 
+io_out[30]                                 |io_out[30]                                 
+io_out[29]                                 |io_out[29]                                 
+io_out[28]                                 |io_out[28]                                 
+vdd                                        |vdd                                        
+vss                                        |vss                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes cntr_example and cntr_example are equivalent.
+
+Final result: Circuits match uniquely.
+.
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/27-lvs.lef.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/27-lvs.lef.log
new file mode 100644
index 0000000..ebac821
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/27-lvs.lef.log
@@ -0,0 +1,321 @@
+Netgen 1.5.242 compiled on Wed Nov 16 22:54:20 UTC 2022
+Warning: netgen command 'format' use fully-qualified name '::netgen::format'
+Warning: netgen command 'global' use fully-qualified name '::netgen::global'
+Generating JSON file result
+Reading netlist file /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/cntr_example.spice
+Reading netlist file /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.pnl.v
+Warning:  A case-insensitive file has been read and so the	verilog file must be treated case-insensitive to match.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__clkinv_3.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__xor2_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__tiel.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__endcap.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__filltie.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__antenna.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Reading setup file /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/netgen/gf180mcuC_setup.tcl
+Comparison output logged to file /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/27-cntr_example.lef.lvs.log
+Logging to file "/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/27-cntr_example.lef.lvs.log" enabled
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_4'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_4 contains 0 device instances.
+Circuit contains 0 nets, and 2 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_4'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_4 contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_64'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_64 contains 0 device instances.
+Circuit contains 0 nets, and 2 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_64'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_64 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_64 contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_32'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_32 contains 0 device instances.
+Circuit contains 0 nets, and 2 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_32'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_32 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_32 contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_16'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_16 contains 0 device instances.
+Circuit contains 0 nets, and 2 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_16'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_16 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_16 contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_8'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_8 contains 0 device instances.
+Circuit contains 0 nets, and 2 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_8'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_8 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_8 contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nand3_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nand3_1 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nand3_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nand3_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__nand3_1 contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__antenna'
+Circuit gf180mcu_fd_sc_mcu7t5v0__antenna contains 0 device instances.
+Circuit contains 0 nets, and 3 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__antenna'
+Circuit gf180mcu_fd_sc_mcu7t5v0__antenna contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__antenna contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__clkbuf_4'
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 contains 0 device instances.
+Circuit contains 0 nets, and 4 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__clkbuf_4'
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__aoi21_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__aoi21_1 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__aoi21_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__aoi21_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__aoi21_1 contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__dffq_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__dffq_1 contains 0 device instances.
+Circuit contains 0 nets, and 5 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__dffq_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__dffq_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__dffq_1 contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__tiel'
+Circuit gf180mcu_fd_sc_mcu7t5v0__tiel contains 0 device instances.
+Circuit contains 0 nets, and 3 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__tiel'
+Circuit gf180mcu_fd_sc_mcu7t5v0__tiel contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__tiel contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__dffq_2'
+Circuit gf180mcu_fd_sc_mcu7t5v0__dffq_2 contains 0 device instances.
+Circuit contains 0 nets, and 5 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__dffq_2'
+Circuit gf180mcu_fd_sc_mcu7t5v0__dffq_2 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__dffq_2 contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__oai21_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__oai21_1 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__oai21_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__oai21_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__oai21_1 contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nor2_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nor2_1 contains 0 device instances.
+Circuit contains 0 nets, and 5 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nor2_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nor2_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__nor2_1 contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__buf_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__buf_1 contains 0 device instances.
+Circuit contains 0 nets, and 4 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__buf_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__buf_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__buf_1 contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__xor2_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__xor2_1 contains 0 device instances.
+Circuit contains 0 nets, and 5 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__xor2_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__xor2_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__xor2_1 contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nand2_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nand2_1 contains 0 device instances.
+Circuit contains 0 nets, and 5 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nand2_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nand2_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__nand2_1 contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__clkbuf_16'
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 contains 0 device instances.
+Circuit contains 0 nets, and 4 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__clkbuf_16'
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__buf_2'
+Circuit gf180mcu_fd_sc_mcu7t5v0__buf_2 contains 0 device instances.
+Circuit contains 0 nets, and 4 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__buf_2'
+Circuit gf180mcu_fd_sc_mcu7t5v0__buf_2 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__buf_2 contains no devices.
+
+Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__clkinv_3'
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkinv_3 contains 0 device instances.
+Circuit contains 0 nets, and 4 disconnected pins.
+Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__clkinv_3'
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkinv_3 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkinv_3 contains no devices.
+
+Contents of circuit 1:  Circuit: 'cntr_example'
+Circuit cntr_example contains 28801 device instances.
+  Class: gf180mcu_fd_sc_mcu7t5v0__nand3_1 instances:   5
+  Class: gf180mcu_fd_sc_mcu7t5v0__dffq_1 instances:   5
+  Class: gf180mcu_fd_sc_mcu7t5v0__dffq_2 instances:  15
+  Class: gf180mcu_fd_sc_mcu7t5v0__nand2_1 instances:   5
+  Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 instances:  20
+  Class: gf180mcu_fd_sc_mcu7t5v0__clkinv_3 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__buf_1 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__buf_2 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 instances:   3
+  Class: gf180mcu_fd_sc_mcu7t5v0__aoi21_1 instances:  10
+  Class: gf180mcu_fd_sc_mcu7t5v0__tiel instances:  18
+  Class: gf180mcu_fd_sc_mcu7t5v0__oai21_1 instances:   5
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_4 instances: 13770
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_8 instances: 274
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_64 instances: 13503
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_16 instances: 438
+  Class: gf180mcu_fd_sc_mcu7t5v0__nor2_1 instances:  15
+  Class: gf180mcu_fd_sc_mcu7t5v0__antenna instances: 160
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_32 instances: 547
+  Class: gf180mcu_fd_sc_mcu7t5v0__xor2_1 instances:   5
+Circuit contains 113 nets.
+Contents of circuit 2:  Circuit: 'cntr_example'
+Circuit cntr_example contains 28801 device instances.
+  Class: gf180mcu_fd_sc_mcu7t5v0__nand3_1 instances:   5
+  Class: gf180mcu_fd_sc_mcu7t5v0__dffq_1 instances:   5
+  Class: gf180mcu_fd_sc_mcu7t5v0__dffq_2 instances:  15
+  Class: gf180mcu_fd_sc_mcu7t5v0__nand2_1 instances:   5
+  Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 instances:  20
+  Class: gf180mcu_fd_sc_mcu7t5v0__clkinv_3 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__buf_1 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__buf_2 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 instances:   3
+  Class: gf180mcu_fd_sc_mcu7t5v0__aoi21_1 instances:  10
+  Class: gf180mcu_fd_sc_mcu7t5v0__tiel instances:  18
+  Class: gf180mcu_fd_sc_mcu7t5v0__oai21_1 instances:   5
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_4 instances: 13770
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_8 instances: 274
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_64 instances: 13503
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_16 instances: 438
+  Class: gf180mcu_fd_sc_mcu7t5v0__nor2_1 instances:  15
+  Class: gf180mcu_fd_sc_mcu7t5v0__antenna instances: 160
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_32 instances: 547
+  Class: gf180mcu_fd_sc_mcu7t5v0__xor2_1 instances:   5
+Circuit contains 113 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'cntr_example'
+Circuit cntr_example contains 174 device instances.
+  Class: gf180mcu_fd_sc_mcu7t5v0__nand3_1 instances:   5
+  Class: gf180mcu_fd_sc_mcu7t5v0__dffq_1 instances:   5
+  Class: gf180mcu_fd_sc_mcu7t5v0__dffq_2 instances:  15
+  Class: gf180mcu_fd_sc_mcu7t5v0__nand2_1 instances:   5
+  Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 instances:  20
+  Class: gf180mcu_fd_sc_mcu7t5v0__clkinv_3 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__buf_1 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__buf_2 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 instances:   3
+  Class: gf180mcu_fd_sc_mcu7t5v0__aoi21_1 instances:  10
+  Class: gf180mcu_fd_sc_mcu7t5v0__tiel instances:  18
+  Class: gf180mcu_fd_sc_mcu7t5v0__oai21_1 instances:   5
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_4 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_8 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_64 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_16 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__nor2_1 instances:  15
+  Class: gf180mcu_fd_sc_mcu7t5v0__antenna instances:  60
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_32 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__xor2_1 instances:   5
+Circuit contains 113 nets.
+Contents of circuit 2:  Circuit: 'cntr_example'
+Circuit cntr_example contains 174 device instances.
+  Class: gf180mcu_fd_sc_mcu7t5v0__nand3_1 instances:   5
+  Class: gf180mcu_fd_sc_mcu7t5v0__dffq_1 instances:   5
+  Class: gf180mcu_fd_sc_mcu7t5v0__dffq_2 instances:  15
+  Class: gf180mcu_fd_sc_mcu7t5v0__nand2_1 instances:   5
+  Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 instances:  20
+  Class: gf180mcu_fd_sc_mcu7t5v0__clkinv_3 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__buf_1 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__buf_2 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 instances:   3
+  Class: gf180mcu_fd_sc_mcu7t5v0__aoi21_1 instances:  10
+  Class: gf180mcu_fd_sc_mcu7t5v0__tiel instances:  18
+  Class: gf180mcu_fd_sc_mcu7t5v0__oai21_1 instances:   5
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_4 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_8 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_64 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_16 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__nor2_1 instances:  15
+  Class: gf180mcu_fd_sc_mcu7t5v0__antenna instances:  60
+  Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_32 instances:   1
+  Class: gf180mcu_fd_sc_mcu7t5v0__xor2_1 instances:   5
+Circuit contains 113 nets.
+
+Circuit 1 contains 174 devices, Circuit 2 contains 174 devices.
+Circuit 1 contains 113 nets,    Circuit 2 contains 113 nets.
+
+
+Final result: 
+Circuits match uniquely.
+.
+Logging to file "/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/27-cntr_example.lef.lvs.log" disabled
+LVS Done.
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/28-drc.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/28-drc.log
new file mode 100644
index 0000000..ff74d83
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/28-drc.log
@@ -0,0 +1,159 @@
+
+Magic 8.3 revision 331 - Compiled on Sat Oct 22 18:40:56 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology gf180mcuC ...
+10 Magic internal units = 1 Lambda
+Input style import: scaleFactor=10, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    obsactive mvobsactive filldiff fillpoly m1hole obsm1 fillm1 obsv1 m2hole obsm2 fillm2 obsv2 m3hole obsm3 fillm3 m4hole obsm4 fillm4 m5hole obsm5 fillm5 glass fillblock lvstext obscomment 
+Scaled tech values by 10 / 1 to match internal grid scaling
+Loading gf180mcuC Device Generator Menu ...
+Using technology "gf180mcuC", version 1.0.349-0-g0059588
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: cntr_example
+Reading "gf180mcu_fd_sc_mcu7t5v0__tiel".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Reading "gf180mcu_fd_sc_mcu7t5v0__endcap".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_16".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_8".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fill_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__filltie".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_64".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_32".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fill_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__antenna".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_3".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi21_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand3_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai21_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__xor2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__xor2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__xor2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__xor2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__xor2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffq_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffq_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Reading "cntr_example".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+[INFO]: Loading cntr_example
+
+DRC style is now "drc(full)"
+Loading DRC CIF style.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.rpt)
+[INFO]: Saving mag view with DRC errors (/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/cntr_example.drc.mag)
+[INFO]: Saved
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/29-antenna.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/29-antenna.log
new file mode 100644
index 0000000..aa60ee7
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/29-antenna.log
@@ -0,0 +1,862 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Net: net5
+  Pin: _089_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+    Layer: Metal3
+      Partial area ratio:   26.98
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:  104.35
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:   69.47
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:  155.20
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:    0.88
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    3.69
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.88
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    3.69
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.14
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.21
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_VV
+      Partial area ratio:    0.07
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.07
+      Required ratio:    0.00 (Cumulative area) 
+
+  Pin: output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+    Layer: Metal3
+      Partial area ratio:   26.98
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:  104.35
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:  319.25
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio: 1119.47
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.11
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_HV
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.06
+      Required ratio:    0.00 (Cumulative area) 
+
+  Pin: _086_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+    Layer: Metal3
+      Partial area ratio:   26.98
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:  104.35
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:  320.81
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio: 1126.05
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:    1.57
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    6.59
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    1.57
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    6.59
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.12
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_VV
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.06
+      Required ratio:    0.00 (Cumulative area) 
+
+  Pin: _087_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+    Layer: Metal3
+      Partial area ratio:   26.98
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:  104.35
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:  319.25
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio: 1119.47
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:  249.78
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:  964.27
+      Required ratio:  400.00 (Side area) (VIOLATED)
+      Cumulative area ratio:  249.78
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:  964.27
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.18
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.25
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_VV
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.06
+      Required ratio:    0.00 (Cumulative area) 
+
+  Pin: _088_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+    Layer: Metal3
+      Partial area ratio:   26.98
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:  104.35
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:   69.47
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:  155.20
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.12
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_VV
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.06
+      Required ratio:    0.00 (Cumulative area) 
+
+  Pin: _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+    Layer: Metal3
+      Partial area ratio:   26.98
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:  104.35
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:   68.59
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:  151.51
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:   11.98
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:   47.16
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:   11.98
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:   47.16
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.14
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.21
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_HV
+      Partial area ratio:    0.07
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.07
+      Required ratio:    0.00 (Cumulative area) 
+
+
+Net: net10
+  Pin: output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+    Layer: Metal3
+      Partial area ratio:   15.30
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:   59.27
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:  247.71
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:  890.24
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:    0.46
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    2.04
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.46
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    2.04
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.11
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_HV
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.06
+      Required ratio:    0.00 (Cumulative area) 
+
+  Pin: _053_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+    Layer: Metal3
+      Partial area ratio:   15.30
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:   59.27
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:  247.24
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:  888.20
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:  209.68
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:  809.68
+      Required ratio:  400.00 (Side area) (VIOLATED)
+      Cumulative area ratio:  209.68
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:  809.68
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.14
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.21
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_HV
+      Partial area ratio:    0.07
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.07
+      Required ratio:    0.00 (Cumulative area) 
+
+  Pin: _050_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+    Layer: Metal3
+      Partial area ratio:   15.30
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:   59.27
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:   39.20
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:   85.11
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:    1.64
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    6.59
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    1.64
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    6.59
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.12
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_VV
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.06
+      Required ratio:    0.00 (Cumulative area) 
+
+  Pin: _052_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+    Layer: Metal3
+      Partial area ratio:   15.30
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:   59.27
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:   37.56
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:   78.52
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.12
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_VV
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.06
+      Required ratio:    0.00 (Cumulative area) 
+
+  Pin: _051_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+    Layer: Metal3
+      Partial area ratio:   15.30
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:   59.27
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:   37.56
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:   78.52
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:    4.85
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:   19.25
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    4.85
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:   19.25
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.12
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.18
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_VV
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.06
+      Required ratio:    0.00 (Cumulative area) 
+
+
+Net: net12
+  Pin: output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+    Layer: Metal4
+      Partial area ratio:   24.16
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:   93.25
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:  326.82
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:  937.43
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal3
+      Partial area ratio:   86.38
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:  333.40
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:  269.96
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:  844.18
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:    0.82
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    3.62
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    1.39
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    3.62
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via3_HV
+      Partial area ratio:    0.02
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.22
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.11
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_HV
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.06
+      Required ratio:    0.00 (Cumulative area) 
+
+  Pin: _056_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+    Layer: Metal4
+      Partial area ratio:   24.16
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:   93.25
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:  325.43
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:  933.81
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal3
+      Partial area ratio:   86.38
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:  333.40
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:  268.57
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:  840.56
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:  131.19
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:  507.15
+      Required ratio:  400.00 (Side area) (VIOLATED)
+      Cumulative area ratio:  131.19
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:  507.15
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via3_HV
+      Partial area ratio:    0.02
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.15
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.08
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.13
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_HV
+      Partial area ratio:    0.04
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.04
+      Required ratio:    0.00 (Cumulative area) 
+
+
+Net: net20
+  Pin: _076_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+    Layer: Metal3
+      Partial area ratio:   18.55
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:   71.85
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:   39.16
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:   73.12
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:    0.25
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    1.27
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.25
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    1.27
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.07
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.14
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_VV
+      Partial area ratio:    0.07
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.07
+      Required ratio:    0.00 (Cumulative area) 
+
+  Pin: _078_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+    Layer: Metal3
+      Partial area ratio:   18.55
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:   71.85
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:   38.91
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:   71.85
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.12
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_VV
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.06
+      Required ratio:    0.00 (Cumulative area) 
+
+  Pin: _077_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+    Layer: Metal3
+      Partial area ratio:   18.55
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:   71.85
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:   69.43
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:  190.39
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:   30.52
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:  118.55
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:   30.52
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:  118.55
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.12
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.18
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_VV
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.06
+      Required ratio:    0.00 (Cumulative area) 
+
+  Pin: _080_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+    Layer: Metal3
+      Partial area ratio:   18.55
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:   71.85
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:   69.83
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:  192.24
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:    0.40
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    1.84
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.40
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    1.84
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.07
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.14
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_VV
+      Partial area ratio:    0.07
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.07
+      Required ratio:    0.00 (Cumulative area) 
+
+  Pin: output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+    Layer: Metal3
+      Partial area ratio:   18.55
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:   71.85
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:  249.45
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:  885.56
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:    0.33
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    1.53
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.33
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    1.53
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.11
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_HV
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.06
+      Required ratio:    0.00 (Cumulative area) 
+
+  Pin: _079_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+    Layer: Metal3
+      Partial area ratio:   18.55
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:   71.85
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:  249.12
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:  884.03
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal2
+      Partial area ratio:  179.69
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:  693.64
+      Required ratio:  400.00 (Side area) (VIOLATED)
+      Cumulative area ratio:  179.69
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:  693.64
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Layer: Metal1
+      Partial area ratio:    0.00
+      Required ratio:    0.00 (Gate area) 
+      Partial area ratio:    0.00
+      Required ratio:  400.00 (Side area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative area) 
+      Cumulative area ratio:    0.00
+      Required ratio:    0.00 (Cumulative side area) 
+
+    Via: Via2_VH
+      Partial area ratio:    0.12
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.18
+      Required ratio:    0.00 (Cumulative area) 
+
+    Via: Via1_VV
+      Partial area ratio:    0.06
+      Required ratio:   20.00 (Gate area) 
+      Cumulative area ratio:    0.06
+      Required ratio:    0.00 (Cumulative area) 
+
+
+[INFO ANT-0002] Found 4 net violations.
+[INFO ANT-0001] Found 4 pin violations.
diff --git a/openlane/cntr_example/runs/cntr_example/logs/synthesis/1-synthesis.log b/openlane/cntr_example/runs/cntr_example/logs/synthesis/1-synthesis.log
new file mode 100644
index 0000000..517c198
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/synthesis/1-synthesis.log
@@ -0,0 +1,1163 @@
+
+ /----------------------------------------------------------------------------\
+ |                                                                            |
+ |  yosys -- Yosys Open SYnthesis Suite                                       |
+ |                                                                            |
+ |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
+ |                                                                            |
+ |  Permission to use, copy, modify, and/or distribute this software for any  |
+ |  purpose with or without fee is hereby granted, provided that the above    |
+ |  copyright notice and this permission notice appear in all copies.         |
+ |                                                                            |
+ |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
+ |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
+ |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
+ |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
+ |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
+ |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
+ |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
+ |                                                                            |
+ \----------------------------------------------------------------------------/
+
+ Yosys 0.22 (git sha1 f109fa3d4c5, gcc 8.3.1 -fPIC -Os)
+
+[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
+Defining MPRJ_IO_PADS=38
+
+1. Executing Verilog-2005 frontend: /home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v
+Parsing SystemVerilog input from `/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v' to AST representation.
+Generating RTLIL representation for module `\cntr_example'.
+Generating RTLIL representation for module `\cntr_1'.
+Generating RTLIL representation for module `\cntr_2'.
+Generating RTLIL representation for module `\cntr_3'.
+Generating RTLIL representation for module `\cntr_4'.
+Generating RTLIL representation for module `\cntr_5'.
+Successfully finished Verilog frontend.
+
+2. Generating Graphviz representation of design.
+Writing dot description to `/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/hierarchy.dot'.
+Dumping module cntr_example to page 1.
+Warning: WIDTHLABEL \io_out [19:16] 4
+Warning: WIDTHLABEL \io_out [15:12] 4
+Warning: WIDTHLABEL \io_out [11:8] 4
+Warning: WIDTHLABEL \io_out [7:4] 4
+Warning: WIDTHLABEL \io_out [3:0] 4
+
+3. Executing HIERARCHY pass (managing design hierarchy).
+
+3.1. Analyzing design hierarchy..
+Top module:  \cntr_example
+Used module:     \cntr_5
+Used module:     \cntr_4
+Used module:     \cntr_3
+Used module:     \cntr_2
+Used module:     \cntr_1
+Parameter \BITS = 20
+
+3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\cntr_5'.
+Parameter \BITS = 20
+Generating RTLIL representation for module `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100'.
+Parameter \BITS = 20
+
+3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\cntr_4'.
+Parameter \BITS = 20
+Generating RTLIL representation for module `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100'.
+Parameter \BITS = 20
+
+3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\cntr_3'.
+Parameter \BITS = 20
+Generating RTLIL representation for module `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100'.
+Parameter \BITS = 20
+
+3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\cntr_2'.
+Parameter \BITS = 20
+Generating RTLIL representation for module `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100'.
+Parameter \BITS = 20
+
+3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\cntr_1'.
+Parameter \BITS = 20
+Generating RTLIL representation for module `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100'.
+
+3.7. Analyzing design hierarchy..
+Top module:  \cntr_example
+Used module:     $paramod\cntr_5\BITS=s32'00000000000000000000000000010100
+Used module:     $paramod\cntr_4\BITS=s32'00000000000000000000000000010100
+Used module:     $paramod\cntr_3\BITS=s32'00000000000000000000000000010100
+Used module:     $paramod\cntr_2\BITS=s32'00000000000000000000000000010100
+Used module:     $paramod\cntr_1\BITS=s32'00000000000000000000000000010100
+
+3.8. Analyzing design hierarchy..
+Top module:  \cntr_example
+Used module:     $paramod\cntr_5\BITS=s32'00000000000000000000000000010100
+Used module:     $paramod\cntr_4\BITS=s32'00000000000000000000000000010100
+Used module:     $paramod\cntr_3\BITS=s32'00000000000000000000000000010100
+Used module:     $paramod\cntr_2\BITS=s32'00000000000000000000000000010100
+Used module:     $paramod\cntr_1\BITS=s32'00000000000000000000000000010100
+Removing unused module `\cntr_5'.
+Removing unused module `\cntr_4'.
+Removing unused module `\cntr_3'.
+Removing unused module `\cntr_2'.
+Removing unused module `\cntr_1'.
+Removed 5 unused modules.
+Warning: Resizing cell port cntr_example.cntr_5.out5 from 4 bits to 20 bits.
+Warning: Resizing cell port cntr_example.cntr_4.out4 from 4 bits to 20 bits.
+Warning: Resizing cell port cntr_example.cntr_3.out3 from 4 bits to 20 bits.
+Warning: Resizing cell port cntr_example.cntr_2.out2 from 4 bits to 20 bits.
+Warning: Resizing cell port cntr_example.cntr_1.out1 from 4 bits to 20 bits.
+WARNING: TRISTATE_BUFFER_MAP is defined but could not be found: /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tribuff_map.v
+
+4. Executing SYNTH pass.
+
+4.1. Executing HIERARCHY pass (managing design hierarchy).
+
+4.1.1. Analyzing design hierarchy..
+Top module:  \cntr_example
+Used module:     $paramod\cntr_5\BITS=s32'00000000000000000000000000010100
+Used module:     $paramod\cntr_4\BITS=s32'00000000000000000000000000010100
+Used module:     $paramod\cntr_3\BITS=s32'00000000000000000000000000010100
+Used module:     $paramod\cntr_2\BITS=s32'00000000000000000000000000010100
+Used module:     $paramod\cntr_1\BITS=s32'00000000000000000000000000010100
+
+4.1.2. Analyzing design hierarchy..
+Top module:  \cntr_example
+Used module:     $paramod\cntr_5\BITS=s32'00000000000000000000000000010100
+Used module:     $paramod\cntr_4\BITS=s32'00000000000000000000000000010100
+Used module:     $paramod\cntr_3\BITS=s32'00000000000000000000000000010100
+Used module:     $paramod\cntr_2\BITS=s32'00000000000000000000000000010100
+Used module:     $paramod\cntr_1\BITS=s32'00000000000000000000000000010100
+Removed 0 unused modules.
+
+4.2. Executing PROC pass (convert processes to netlists).
+
+4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Cleaned up 0 empty switches.
+
+4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
+Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28 in module $paramod\cntr_1\BITS=s32'00000000000000000000000000010100.
+Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25 in module $paramod\cntr_2\BITS=s32'00000000000000000000000000010100.
+Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22 in module $paramod\cntr_3\BITS=s32'00000000000000000000000000010100.
+Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19 in module $paramod\cntr_4\BITS=s32'00000000000000000000000000010100.
+Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16 in module $paramod\cntr_5\BITS=s32'00000000000000000000000000010100.
+Removed a total of 0 dead cases.
+
+4.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
+Removed 5 redundant assignments.
+Promoted 0 assignments to connections.
+
+4.2.4. Executing PROC_INIT pass (extract init attributes).
+
+4.2.5. Executing PROC_ARST pass (detect async resets in processes).
+
+4.2.6. Executing PROC_ROM pass (convert switches to ROMs).
+Converted 0 switches.
+<suppressed ~5 debug messages>
+
+4.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
+Creating decoders for process `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28'.
+     1/1: $0\out1[19:0]
+Creating decoders for process `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25'.
+     1/1: $0\out2[19:0]
+Creating decoders for process `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22'.
+     1/1: $0\out3[19:0]
+Creating decoders for process `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19'.
+     1/1: $0\out4[19:0]
+Creating decoders for process `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16'.
+     1/1: $0\out5[19:0]
+
+4.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
+
+4.2.9. Executing PROC_DFF pass (convert process syncs to FFs).
+Creating register for signal `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.\out1' using process `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28'.
+  created $dff cell `$procdff$51' with positive edge clock.
+Creating register for signal `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.\out2' using process `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25'.
+  created $dff cell `$procdff$52' with positive edge clock.
+Creating register for signal `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.\out3' using process `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22'.
+  created $dff cell `$procdff$53' with positive edge clock.
+Creating register for signal `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.\out4' using process `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19'.
+  created $dff cell `$procdff$54' with positive edge clock.
+Creating register for signal `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.\out5' using process `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16'.
+  created $dff cell `$procdff$55' with positive edge clock.
+
+4.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
+
+4.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Found and cleaned up 1 empty switch in `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28'.
+Removing empty process `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28'.
+Found and cleaned up 1 empty switch in `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25'.
+Removing empty process `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25'.
+Found and cleaned up 1 empty switch in `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22'.
+Removing empty process `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22'.
+Found and cleaned up 1 empty switch in `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19'.
+Removing empty process `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19'.
+Found and cleaned up 1 empty switch in `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16'.
+Removing empty process `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16'.
+Cleaned up 5 empty switches.
+
+4.2.12. Executing OPT_EXPR pass (perform const folding).
+Optimizing module $paramod\cntr_1\BITS=s32'00000000000000000000000000010100.
+<suppressed ~1 debug messages>
+Optimizing module $paramod\cntr_2\BITS=s32'00000000000000000000000000010100.
+<suppressed ~1 debug messages>
+Optimizing module $paramod\cntr_3\BITS=s32'00000000000000000000000000010100.
+<suppressed ~1 debug messages>
+Optimizing module $paramod\cntr_4\BITS=s32'00000000000000000000000000010100.
+<suppressed ~1 debug messages>
+Optimizing module $paramod\cntr_5\BITS=s32'00000000000000000000000000010100.
+<suppressed ~1 debug messages>
+Optimizing module cntr_example.
+
+4.3. Executing FLATTEN pass (flatten design).
+Deleting now unused module $paramod\cntr_1\BITS=s32'00000000000000000000000000010100.
+Deleting now unused module $paramod\cntr_2\BITS=s32'00000000000000000000000000010100.
+Deleting now unused module $paramod\cntr_3\BITS=s32'00000000000000000000000000010100.
+Deleting now unused module $paramod\cntr_4\BITS=s32'00000000000000000000000000010100.
+Deleting now unused module $paramod\cntr_5\BITS=s32'00000000000000000000000000010100.
+<suppressed ~5 debug messages>
+
+4.4. Executing OPT_EXPR pass (perform const folding).
+Optimizing module cntr_example.
+
+4.5. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \cntr_example..
+Removed 5 unused cells and 20 unused wires.
+<suppressed ~6 debug messages>
+
+4.6. Executing CHECK pass (checking for obvious problems).
+Checking module cntr_example...
+Warning: Wire cntr_example.\io_out [37] is used but has no driver.
+Warning: Wire cntr_example.\io_out [36] is used but has no driver.
+Warning: Wire cntr_example.\io_out [35] is used but has no driver.
+Warning: Wire cntr_example.\io_out [34] is used but has no driver.
+Warning: Wire cntr_example.\io_out [33] is used but has no driver.
+Warning: Wire cntr_example.\io_out [32] is used but has no driver.
+Warning: Wire cntr_example.\io_out [31] is used but has no driver.
+Warning: Wire cntr_example.\io_out [30] is used but has no driver.
+Warning: Wire cntr_example.\io_out [29] is used but has no driver.
+Warning: Wire cntr_example.\io_out [28] is used but has no driver.
+Warning: Wire cntr_example.\io_out [27] is used but has no driver.
+Warning: Wire cntr_example.\io_out [26] is used but has no driver.
+Warning: Wire cntr_example.\io_out [25] is used but has no driver.
+Warning: Wire cntr_example.\io_out [24] is used but has no driver.
+Warning: Wire cntr_example.\io_out [23] is used but has no driver.
+Warning: Wire cntr_example.\io_out [22] is used but has no driver.
+Warning: Wire cntr_example.\io_out [21] is used but has no driver.
+Warning: Wire cntr_example.\io_out [20] is used but has no driver.
+Found and reported 18 problems.
+
+4.7. Executing OPT pass (performing simple optimizations).
+
+4.7.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module cntr_example.
+
+4.7.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\cntr_example'.
+Removed a total of 0 cells.
+
+4.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \cntr_example..
+  Creating internal representation of mux trees.
+  Evaluating internal representation of mux trees.
+  Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~5 debug messages>
+
+4.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+  Optimizing cells in module \cntr_example.
+Performed a total of 0 changes.
+
+4.7.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\cntr_example'.
+Removed a total of 0 cells.
+
+4.7.6. Executing OPT_DFF pass (perform DFF optimizations).
+
+4.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \cntr_example..
+
+4.7.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module cntr_example.
+
+4.7.9. Finished OPT passes. (There is nothing left to do.)
+
+4.8. Executing FSM pass (extract and optimize FSM).
+
+4.8.1. Executing FSM_DETECT pass (finding FSMs in design).
+
+4.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).
+
+4.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).
+
+4.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \cntr_example..
+
+4.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).
+
+4.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
+
+4.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
+
+4.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
+
+4.9. Executing OPT pass (performing simple optimizations).
+
+4.9.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module cntr_example.
+
+4.9.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\cntr_example'.
+Removed a total of 0 cells.
+
+4.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \cntr_example..
+  Creating internal representation of mux trees.
+  Evaluating internal representation of mux trees.
+  Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~5 debug messages>
+
+4.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+  Optimizing cells in module \cntr_example.
+Performed a total of 0 changes.
+
+4.9.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\cntr_example'.
+Removed a total of 0 cells.
+
+4.9.6. Executing OPT_DFF pass (perform DFF optimizations).
+Adding SRST signal on $flatten\cntr_5.$procdff$55 ($dff) from module cntr_example (D = $flatten\cntr_5.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18_Y [19:0], Q = \cntr_5.out5, rval = 20'00000000000000000000).
+Adding SRST signal on $flatten\cntr_4.$procdff$54 ($dff) from module cntr_example (D = $flatten\cntr_4.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21_Y [19:0], Q = \cntr_4.out4, rval = 20'00000000000000000000).
+Adding SRST signal on $flatten\cntr_3.$procdff$53 ($dff) from module cntr_example (D = $flatten\cntr_3.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24_Y [19:0], Q = \cntr_3.out3, rval = 20'00000000000000000000).
+Adding SRST signal on $flatten\cntr_2.$procdff$52 ($dff) from module cntr_example (D = $flatten\cntr_2.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27_Y [19:0], Q = \cntr_2.out2, rval = 20'00000000000000000000).
+Adding SRST signal on $flatten\cntr_1.$procdff$51 ($dff) from module cntr_example (D = $flatten\cntr_1.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30_Y [19:0], Q = \cntr_1.out1, rval = 20'00000000000000000000).
+
+4.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \cntr_example..
+Removed 5 unused cells and 5 unused wires.
+<suppressed ~6 debug messages>
+
+4.9.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module cntr_example.
+
+4.9.9. Rerunning OPT passes. (Maybe there is more to do..)
+
+4.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \cntr_example..
+  Creating internal representation of mux trees.
+  No muxes found in this module.
+Removed 0 multiplexer ports.
+
+4.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+  Optimizing cells in module \cntr_example.
+Performed a total of 0 changes.
+
+4.9.12. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\cntr_example'.
+Removed a total of 0 cells.
+
+4.9.13. Executing OPT_DFF pass (perform DFF optimizations).
+
+4.9.14. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \cntr_example..
+
+4.9.15. Executing OPT_EXPR pass (perform const folding).
+Optimizing module cntr_example.
+
+4.9.16. Finished OPT passes. (There is nothing left to do.)
+
+4.10. Executing WREDUCE pass (reducing word size of cells).
+Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_1.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30 ($add).
+Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_1.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30 ($add).
+Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_2.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27 ($add).
+Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_2.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27 ($add).
+Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_3.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24 ($add).
+Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_3.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24 ($add).
+Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_4.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21 ($add).
+Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_4.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21 ($add).
+Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_5.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18 ($add).
+Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_5.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18 ($add).
+Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_1.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30_Y.
+Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_2.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27_Y.
+Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_3.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24_Y.
+Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_4.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21_Y.
+Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_5.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18_Y.
+
+4.11. Executing PEEPOPT pass (run peephole optimizers).
+
+4.12. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \cntr_example..
+Removed 0 unused cells and 5 unused wires.
+<suppressed ~1 debug messages>
+
+4.13. Executing ALUMACC pass (create $alu and $macc cells).
+Extracting $alu and $macc cells in module cntr_example:
+  creating $macc model for $flatten\cntr_1.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30 ($add).
+  creating $macc model for $flatten\cntr_2.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27 ($add).
+  creating $macc model for $flatten\cntr_3.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24 ($add).
+  creating $macc model for $flatten\cntr_4.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21 ($add).
+  creating $macc model for $flatten\cntr_5.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18 ($add).
+  creating $alu model for $macc $flatten\cntr_5.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18.
+  creating $alu model for $macc $flatten\cntr_4.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21.
+  creating $alu model for $macc $flatten\cntr_3.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24.
+  creating $alu model for $macc $flatten\cntr_2.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27.
+  creating $alu model for $macc $flatten\cntr_1.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30.
+  creating $alu cell for $flatten\cntr_1.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30: $auto$alumacc.cc:485:replace_alu$66
+  creating $alu cell for $flatten\cntr_2.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27: $auto$alumacc.cc:485:replace_alu$69
+  creating $alu cell for $flatten\cntr_3.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24: $auto$alumacc.cc:485:replace_alu$72
+  creating $alu cell for $flatten\cntr_4.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21: $auto$alumacc.cc:485:replace_alu$75
+  creating $alu cell for $flatten\cntr_5.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18: $auto$alumacc.cc:485:replace_alu$78
+  created 5 $alu and 0 $macc cells.
+
+4.14. Executing SHARE pass (SAT-based resource sharing).
+
+4.15. Executing OPT pass (performing simple optimizations).
+
+4.15.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module cntr_example.
+
+4.15.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\cntr_example'.
+Removed a total of 0 cells.
+
+4.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \cntr_example..
+  Creating internal representation of mux trees.
+  No muxes found in this module.
+Removed 0 multiplexer ports.
+
+4.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+  Optimizing cells in module \cntr_example.
+Performed a total of 0 changes.
+
+4.15.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\cntr_example'.
+Removed a total of 0 cells.
+
+4.15.6. Executing OPT_DFF pass (perform DFF optimizations).
+
+4.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \cntr_example..
+
+4.15.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module cntr_example.
+
+4.15.9. Finished OPT passes. (There is nothing left to do.)
+
+4.16. Executing MEMORY pass.
+
+4.16.1. Executing OPT_MEM pass (optimize memories).
+Performed a total of 0 transformations.
+
+4.16.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
+Performed a total of 0 transformations.
+
+4.16.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
+
+4.16.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
+
+4.16.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
+
+4.16.6. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \cntr_example..
+
+4.16.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
+
+4.16.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
+Performed a total of 0 transformations.
+
+4.16.9. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \cntr_example..
+
+4.16.10. Executing MEMORY_COLLECT pass (generating $mem cells).
+
+4.17. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \cntr_example..
+
+4.18. Executing OPT pass (performing simple optimizations).
+
+4.18.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module cntr_example.
+<suppressed ~6 debug messages>
+
+4.18.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\cntr_example'.
+Removed a total of 0 cells.
+
+4.18.3. Executing OPT_DFF pass (perform DFF optimizations).
+
+4.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \cntr_example..
+
+4.18.5. Finished fast OPT passes.
+
+4.19. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
+
+4.20. Executing OPT pass (performing simple optimizations).
+
+4.20.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module cntr_example.
+
+4.20.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\cntr_example'.
+Removed a total of 0 cells.
+
+4.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \cntr_example..
+  Creating internal representation of mux trees.
+  No muxes found in this module.
+Removed 0 multiplexer ports.
+
+4.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+  Optimizing cells in module \cntr_example.
+Performed a total of 0 changes.
+
+4.20.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\cntr_example'.
+Removed a total of 0 cells.
+
+4.20.6. Executing OPT_SHARE pass.
+
+4.20.7. Executing OPT_DFF pass (perform DFF optimizations).
+
+4.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \cntr_example..
+
+4.20.9. Executing OPT_EXPR pass (perform const folding).
+Optimizing module cntr_example.
+
+4.20.10. Finished OPT passes. (There is nothing left to do.)
+
+4.21. Executing TECHMAP pass (map to technology primitives).
+
+4.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
+Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
+Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
+Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
+Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
+Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
+Generating RTLIL representation for module `\_90_simplemap_various'.
+Generating RTLIL representation for module `\_90_simplemap_registers'.
+Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
+Generating RTLIL representation for module `\_90_shift_shiftx'.
+Generating RTLIL representation for module `\_90_fa'.
+Generating RTLIL representation for module `\_90_lcu'.
+Generating RTLIL representation for module `\_90_alu'.
+Generating RTLIL representation for module `\_90_macc'.
+Generating RTLIL representation for module `\_90_alumacc'.
+Generating RTLIL representation for module `\$__div_mod_u'.
+Generating RTLIL representation for module `\$__div_mod_trunc'.
+Generating RTLIL representation for module `\_90_div'.
+Generating RTLIL representation for module `\_90_mod'.
+Generating RTLIL representation for module `\$__div_mod_floor'.
+Generating RTLIL representation for module `\_90_divfloor'.
+Generating RTLIL representation for module `\_90_modfloor'.
+Generating RTLIL representation for module `\_90_pow'.
+Generating RTLIL representation for module `\_90_pmux'.
+Generating RTLIL representation for module `\_90_demux'.
+Generating RTLIL representation for module `\_90_lut'.
+Successfully finished Verilog frontend.
+
+4.21.2. Continuing TECHMAP pass.
+Using extmapper simplemap for cells of type $sdff.
+Using template $paramod$ce0ec84be7047712840b0952f343ee9e63ef75d1\_90_alu for cells of type $alu.
+Using extmapper simplemap for cells of type $xor.
+Using extmapper simplemap for cells of type $and.
+Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000010100 for cells of type $lcu.
+Using extmapper simplemap for cells of type $pos.
+Using extmapper simplemap for cells of type $mux.
+Using extmapper simplemap for cells of type $not.
+Using extmapper simplemap for cells of type $or.
+No more expansions possible.
+<suppressed ~675 debug messages>
+
+4.22. Executing OPT pass (performing simple optimizations).
+
+4.22.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module cntr_example.
+<suppressed ~555 debug messages>
+
+4.22.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\cntr_example'.
+<suppressed ~15 debug messages>
+Removed a total of 5 cells.
+
+4.22.3. Executing OPT_DFF pass (perform DFF optimizations).
+
+4.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \cntr_example..
+Removed 410 unused cells and 440 unused wires.
+<suppressed ~411 debug messages>
+
+4.22.5. Finished fast OPT passes.
+
+4.23. Executing ABC pass (technology mapping using ABC).
+
+4.23.1. Extracting gate netlist of module `\cntr_example' to `<abc-temp-dir>/input.blif'..
+Extracted 30 gates and 50 wires to a netlist network with 20 inputs and 20 outputs.
+
+4.23.1.1. Executing ABC.
+Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
+ABC: ABC command line: "source <abc-temp-dir>/abc.script".
+ABC: 
+ABC: + read_blif <abc-temp-dir>/input.blif 
+ABC: + read_library <abc-temp-dir>/stdcells.genlib 
+ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib".
+ABC: + strash 
+ABC: + dretime 
+ABC: + map 
+ABC: + write_blif <abc-temp-dir>/output.blif 
+
+4.23.1.2. Re-integrating ABC results.
+ABC RESULTS:               NOT cells:        5
+ABC RESULTS:              NAND cells:        5
+ABC RESULTS:              XNOR cells:        5
+ABC RESULTS:            ANDNOT cells:        5
+ABC RESULTS:               XOR cells:       10
+ABC RESULTS:        internal signals:       10
+ABC RESULTS:           input signals:       20
+ABC RESULTS:          output signals:       20
+Removing temp directory.
+
+4.24. Executing OPT pass (performing simple optimizations).
+
+4.24.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module cntr_example.
+
+4.24.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\cntr_example'.
+Removed a total of 0 cells.
+
+4.24.3. Executing OPT_DFF pass (perform DFF optimizations).
+
+4.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \cntr_example..
+Removed 0 unused cells and 45 unused wires.
+<suppressed ~1 debug messages>
+
+4.24.5. Finished fast OPT passes.
+
+4.25. Executing HIERARCHY pass (managing design hierarchy).
+
+4.25.1. Analyzing design hierarchy..
+Top module:  \cntr_example
+
+4.25.2. Analyzing design hierarchy..
+Top module:  \cntr_example
+Removed 0 unused modules.
+
+4.26. Printing statistics.
+
+=== cntr_example ===
+
+   Number of wires:                 40
+   Number of wire bits:            362
+   Number of public wires:          20
+   Number of public wire bits:     152
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              0
+   Number of cells:                 50
+     $_ANDNOT_                       5
+     $_NAND_                         5
+     $_NOT_                          5
+     $_SDFF_PN0_                    20
+     $_XNOR_                         5
+     $_XOR_                         10
+
+4.27. Executing CHECK pass (checking for obvious problems).
+Checking module cntr_example...
+Found and reported 0 problems.
+
+5. Generating Graphviz representation of design.
+Writing dot description to `/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/post_techmap.dot'.
+Dumping module cntr_example to page 1.
+Warning: WIDTHLABEL \cntr_3.out3 [0] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$72.X [0] 1
+Warning: WIDTHLABEL \cntr_5.out5 [0] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$78.X [0] 1
+Warning: WIDTHLABEL \cntr_2.out2 [0] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$69.X [0] 1
+Warning: WIDTHLABEL \cntr_4.out4 [0] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$75.X [0] 1
+Warning: WIDTHLABEL \cntr_1.out1 [0] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$66.X [0] 1
+Warning: WIDTHLABEL \cntr_2.out2 [1] 1
+Warning: WIDTHLABEL \cntr_2.out2 [0] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$69.Y [1] 1
+Warning: WIDTHLABEL \cntr_2.out2 [1] 1
+Warning: WIDTHLABEL \cntr_2.out2 [0] 1
+Warning: WIDTHLABEL \cntr_2.out2 [2] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$69.Y [2] 1
+Warning: WIDTHLABEL \cntr_2.out2 [2] 1
+Warning: WIDTHLABEL \cntr_2.out2 [3] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$69.Y [3] 1
+Warning: WIDTHLABEL \cntr_3.out3 [1] 1
+Warning: WIDTHLABEL \cntr_3.out3 [0] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$72.Y [1] 1
+Warning: WIDTHLABEL \cntr_3.out3 [1] 1
+Warning: WIDTHLABEL \cntr_3.out3 [0] 1
+Warning: WIDTHLABEL \cntr_3.out3 [2] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$72.Y [2] 1
+Warning: WIDTHLABEL \cntr_3.out3 [2] 1
+Warning: WIDTHLABEL \cntr_3.out3 [3] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$72.Y [3] 1
+Warning: WIDTHLABEL \cntr_4.out4 [1] 1
+Warning: WIDTHLABEL \cntr_4.out4 [0] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$75.Y [1] 1
+Warning: WIDTHLABEL \cntr_4.out4 [1] 1
+Warning: WIDTHLABEL \cntr_4.out4 [0] 1
+Warning: WIDTHLABEL \cntr_4.out4 [2] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$75.Y [2] 1
+Warning: WIDTHLABEL \cntr_4.out4 [2] 1
+Warning: WIDTHLABEL \cntr_4.out4 [3] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$75.Y [3] 1
+Warning: WIDTHLABEL \cntr_1.out1 [1] 1
+Warning: WIDTHLABEL \cntr_1.out1 [0] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$66.Y [1] 1
+Warning: WIDTHLABEL \cntr_1.out1 [1] 1
+Warning: WIDTHLABEL \cntr_1.out1 [0] 1
+Warning: WIDTHLABEL \cntr_1.out1 [2] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$66.Y [2] 1
+Warning: WIDTHLABEL \cntr_1.out1 [2] 1
+Warning: WIDTHLABEL \cntr_1.out1 [3] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$66.Y [3] 1
+Warning: WIDTHLABEL \cntr_5.out5 [1] 1
+Warning: WIDTHLABEL \cntr_5.out5 [0] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$78.Y [1] 1
+Warning: WIDTHLABEL \cntr_5.out5 [1] 1
+Warning: WIDTHLABEL \cntr_5.out5 [0] 1
+Warning: WIDTHLABEL \cntr_5.out5 [2] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$78.Y [2] 1
+Warning: WIDTHLABEL \cntr_5.out5 [2] 1
+Warning: WIDTHLABEL \cntr_5.out5 [3] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$78.Y [3] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$78.X [0] 1
+Warning: WIDTHLABEL \cntr_5.out5 [0] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$78.Y [1] 1
+Warning: WIDTHLABEL \cntr_5.out5 [1] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$78.Y [2] 1
+Warning: WIDTHLABEL \cntr_5.out5 [2] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$78.Y [3] 1
+Warning: WIDTHLABEL \cntr_5.out5 [3] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$66.X [0] 1
+Warning: WIDTHLABEL \cntr_1.out1 [0] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$66.Y [1] 1
+Warning: WIDTHLABEL \cntr_1.out1 [1] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$66.Y [2] 1
+Warning: WIDTHLABEL \cntr_1.out1 [2] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$66.Y [3] 1
+Warning: WIDTHLABEL \cntr_1.out1 [3] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$69.X [0] 1
+Warning: WIDTHLABEL \cntr_2.out2 [0] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$69.Y [1] 1
+Warning: WIDTHLABEL \cntr_2.out2 [1] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$69.Y [2] 1
+Warning: WIDTHLABEL \cntr_2.out2 [2] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$69.Y [3] 1
+Warning: WIDTHLABEL \cntr_2.out2 [3] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$72.X [0] 1
+Warning: WIDTHLABEL \cntr_3.out3 [0] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$72.Y [1] 1
+Warning: WIDTHLABEL \cntr_3.out3 [1] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$72.Y [2] 1
+Warning: WIDTHLABEL \cntr_3.out3 [2] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$72.Y [3] 1
+Warning: WIDTHLABEL \cntr_3.out3 [3] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$75.X [0] 1
+Warning: WIDTHLABEL \cntr_4.out4 [0] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$75.Y [1] 1
+Warning: WIDTHLABEL \cntr_4.out4 [1] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$75.Y [2] 1
+Warning: WIDTHLABEL \cntr_4.out4 [2] 1
+Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$75.Y [3] 1
+Warning: WIDTHLABEL \cntr_4.out4 [3] 1
+
+6. Executing SHARE pass (SAT-based resource sharing).
+
+7. Executing OPT pass (performing simple optimizations).
+
+7.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module cntr_example.
+
+7.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\cntr_example'.
+Removed a total of 0 cells.
+
+7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \cntr_example..
+  Creating internal representation of mux trees.
+  No muxes found in this module.
+Removed 0 multiplexer ports.
+
+7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+  Optimizing cells in module \cntr_example.
+Performed a total of 0 changes.
+
+7.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\cntr_example'.
+Removed a total of 0 cells.
+
+7.6. Executing OPT_DFF pass (perform DFF optimizations).
+
+7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \cntr_example..
+
+7.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module cntr_example.
+
+7.9. Finished OPT passes. (There is nothing left to do.)
+
+8. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \cntr_example..
+Removed 0 unused cells and 17 unused wires.
+<suppressed ~17 debug messages>
+
+9. Printing statistics.
+
+=== cntr_example ===
+
+   Number of wires:                 23
+   Number of wire bits:            250
+   Number of public wires:           3
+   Number of public wire bits:      40
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              0
+   Number of cells:                 50
+     $_ANDNOT_                       5
+     $_NAND_                         5
+     $_NOT_                          5
+     $_SDFF_PN0_                    20
+     $_XNOR_                         5
+     $_XOR_                         10
+
+10. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
+  cell gf180mcu_fd_sc_mcu7t5v0__dffnq_1 (noninv, pins=3, area=65.86) is a direct match for cell type $_DFF_N_.
+  cell gf180mcu_fd_sc_mcu7t5v0__dffq_1 (noninv, pins=3, area=63.66) is a direct match for cell type $_DFF_P_.
+  cell gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1 (noninv, pins=4, area=74.64) is a direct match for cell type $_DFF_NN0_.
+  cell gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1 (noninv, pins=4, area=79.03) is a direct match for cell type $_DFF_NN1_.
+  cell gf180mcu_fd_sc_mcu7t5v0__dffrnq_1 (noninv, pins=4, area=74.64) is a direct match for cell type $_DFF_PN0_.
+  cell gf180mcu_fd_sc_mcu7t5v0__dffsnq_1 (noninv, pins=4, area=79.03) is a direct match for cell type $_DFF_PN1_.
+  cell gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1 (noninv, pins=5, area=94.39) is a direct match for cell type $_DFFSR_NNN_.
+  cell gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1 (noninv, pins=5, area=85.61) is a direct match for cell type $_DFFSR_PNN_.
+  final dff cell mappings:
+    \gf180mcu_fd_sc_mcu7t5v0__dffnq_1 _DFF_N_ (.CLKN( C), .D( D), .Q( Q));
+    \gf180mcu_fd_sc_mcu7t5v0__dffq_1 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
+    \gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1 _DFF_NN0_ (.CLKN( C), .D( D), .Q( Q), .RN( R));
+    \gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1 _DFF_NN1_ (.CLKN( C), .D( D), .Q( Q), .SETN( R));
+    unmapped dff cell: $_DFF_NP0_
+    unmapped dff cell: $_DFF_NP1_
+    \gf180mcu_fd_sc_mcu7t5v0__dffrnq_1 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RN( R));
+    \gf180mcu_fd_sc_mcu7t5v0__dffsnq_1 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SETN( R));
+    unmapped dff cell: $_DFF_PP0_
+    unmapped dff cell: $_DFF_PP1_
+    \gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1 _DFFSR_NNN_ (.CLKN( C), .D( D), .Q( Q), .RN( R), .SETN( S));
+    unmapped dff cell: $_DFFSR_NNP_
+    unmapped dff cell: $_DFFSR_NPN_
+    unmapped dff cell: $_DFFSR_NPP_
+    \gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1 _DFFSR_PNN_ (.CLK( C), .D( D), .Q( Q), .RN( R), .SETN( S));
+    unmapped dff cell: $_DFFSR_PNP_
+    unmapped dff cell: $_DFFSR_PPN_
+    unmapped dff cell: $_DFFSR_PPP_
+
+10.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
+Mapping DFF cells in module `\cntr_example':
+  mapped 20 $_DFF_P_ cells to \gf180mcu_fd_sc_mcu7t5v0__dffq_1 cells.
+
+11. Printing statistics.
+
+=== cntr_example ===
+
+   Number of wires:                 43
+   Number of wire bits:            270
+   Number of public wires:           3
+   Number of public wire bits:      40
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              0
+   Number of cells:                 70
+     $_ANDNOT_                       5
+     $_MUX_                         20
+     $_NAND_                         5
+     $_NOT_                          5
+     $_XNOR_                         5
+     $_XOR_                         10
+     gf180mcu_fd_sc_mcu7t5v0__dffq_1     20
+
+[INFO]: USING STRATEGY AREA 0
+
+12. Executing ABC pass (technology mapping using ABC).
+
+12.1. Extracting gate netlist of module `\cntr_example' to `/tmp/yosys-abc-V62u8j/input.blif'..
+Extracted 50 gates and 72 wires to a netlist network with 21 inputs and 20 outputs.
+
+12.1.1. Executing ABC.
+Running ABC command: "/build/bin/yosys-abc" -s -f /tmp/yosys-abc-V62u8j/abc.script 2>&1
+ABC: ABC command line: "source /tmp/yosys-abc-V62u8j/abc.script".
+ABC: 
+ABC: + read_blif /tmp/yosys-abc-V62u8j/input.blif 
+ABC: + read_lib -w /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/trimmed.lib 
+ABC: Parsing finished successfully.  Parsing time =     0.10 sec
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__antenna" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_1".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_2".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_3".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_4".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_8".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_12".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_16".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnrnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnrnq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnsnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnsnq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffrnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffrnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffrnq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffrsnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffrsnq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffsnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffsnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffsnq_4".
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__endcap" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_1" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_2" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_4" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_8" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_16" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_32" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_64" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fillcap_4" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fillcap_8" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fillcap_16" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fillcap_32" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fillcap_64" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__filltie" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__hold".
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__icgtn_1" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__icgtn_2" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__icgtn_4" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__icgtp_1" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__icgtp_2" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__icgtp_4" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_1".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_2".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_3".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_4".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_8".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_12".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_16".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latrnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latrnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latrnq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latrsnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latrsnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latrsnq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latsnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latsnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latsnq_4".
+ABC: Library "gf180mcuC_merged" from "/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/trimmed.lib" has 143 cells (72 skipped: 36 seq; 15 tri-state; 21 no func; 0 dont_use).  Time =     0.21 sec
+ABC: Memory =   23.58 MB. Time =     0.21 sec
+ABC: Warning: Detected 6 multi-output gates (for example, "gf180mcu_fd_sc_mcu7t5v0__addf_1").
+ABC: + read_constr -v /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/synthesis.sdc 
+ABC: Setting driving cell to be "gf180mcu_fd_sc_mcu7t5v0__inv_1".
+ABC: Setting output load to be 72.910004.
+ABC: + read_constr /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/synthesis.sdc 
+ABC: + fx 
+ABC: + mfs 
+ABC: + strash 
+ABC: + refactor 
+ABC: + balance 
+ABC: + rewrite 
+ABC: + refactor 
+ABC: + balance 
+ABC: + rewrite 
+ABC: + rewrite -z 
+ABC: + balance 
+ABC: + refactor -z 
+ABC: + rewrite -z 
+ABC: + balance 
+ABC: + retime -D -D 65000 -M 5 
+ABC: + scleanup 
+ABC: Error: The network is combinational.
+ABC: + fraig_store 
+ABC: + balance 
+ABC: + fraig_store 
+ABC: + balance 
+ABC: + rewrite 
+ABC: + refactor 
+ABC: + balance 
+ABC: + rewrite 
+ABC: + rewrite -z 
+ABC: + balance 
+ABC: + refactor -z 
+ABC: + rewrite -z 
+ABC: + balance 
+ABC: + fraig_store 
+ABC: + balance 
+ABC: + rewrite 
+ABC: + refactor 
+ABC: + balance 
+ABC: + rewrite 
+ABC: + rewrite -z 
+ABC: + balance 
+ABC: + refactor -z 
+ABC: + rewrite -z 
+ABC: + balance 
+ABC: + fraig_store 
+ABC: + balance 
+ABC: + rewrite 
+ABC: + refactor 
+ABC: + balance 
+ABC: + rewrite 
+ABC: + rewrite -z 
+ABC: + balance 
+ABC: + refactor -z 
+ABC: + rewrite -z 
+ABC: + balance 
+ABC: + fraig_store 
+ABC: + fraig_restore 
+ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 
+ABC: + retime -D -D 65000 
+ABC: + &get -n 
+ABC: + &st 
+ABC: + &dch 
+ABC: + &nf 
+ABC: + &put 
+ABC: + buffer -N 10 -S 3000 
+ABC: + upsize -D 65000 
+ABC: Current delay (2618.90 ps) does not exceed the target delay (65000.00 ps). Upsizing is not performed.
+ABC: + dnsize -D 65000 
+ABC: + stime -p 
+ABC: WireLoad = "none"  Gates =     47 (  4.3 %)   Cap = 29.1 ff (  8.1 %)   Area =      746.37 ( 85.1 %)   Delay =  3469.14 ps  ( 55.3 %)               
+ABC: Path  0 --      21 : 0    2 pi                               A =   0.00  Df = 103.0  -47.2 ps  S = 248.8 ps  Cin =  0.0 ff  Cout =   7.5 ff  Cmax =   0.0 ff  G =    0  
+ABC: Path  1 --      44 : 1   10 gf180mcu_fd_sc_mcu7t5v0__buf_1   A =  13.17  Df = 988.4 -236.4 ps  S =1189.3 ps  Cin =  2.8 ff  Cout =  46.8 ff  Cmax = 359.7 ff  G = 1651  
+ABC: Path  2 --      45 : 3    1 gf180mcu_fd_sc_mcu7t5v0__oai21_1 A =  17.56  Df =1267.0  -85.3 ps  S = 430.8 ps  Cin =  4.7 ff  Cout =   3.9 ff  Cmax = 181.9 ff  G =   82  
+ABC: Path  3 --      46 : 3    1 gf180mcu_fd_sc_mcu7t5v0__aoi21_1 A =  17.56  Df =3469.1-1212.2 ps  S =3554.1 ps  Cin =  4.4 ff  Cout =  72.9 ff  Cmax = 181.5 ff  G = 1642  
+ABC: Start-point = pi20 (\wb_rst_i).  End-point = po1 ($auto$rtlil.cc:2560:MuxGate$1324).
+ABC: + print_stats -m 
+ABC: netlist                       : i/o =   21/   20  lat =    0  nd =    47  edge =    112  area =746.35  delay = 3.00  lev = 3
+ABC: + write_blif /tmp/yosys-abc-V62u8j/output.blif 
+
+12.1.2. Re-integrating ABC results.
+ABC RESULTS:   gf180mcu_fd_sc_mcu7t5v0__inv_1 cells:        1
+ABC RESULTS:   gf180mcu_fd_sc_mcu7t5v0__buf_1 cells:        1
+ABC RESULTS:   gf180mcu_fd_sc_mcu7t5v0__oai21_1 cells:        5
+ABC RESULTS:   gf180mcu_fd_sc_mcu7t5v0__aoi21_1 cells:       10
+ABC RESULTS:   gf180mcu_fd_sc_mcu7t5v0__nand3_1 cells:        5
+ABC RESULTS:   gf180mcu_fd_sc_mcu7t5v0__nand2_1 cells:        5
+ABC RESULTS:   gf180mcu_fd_sc_mcu7t5v0__xor2_1 cells:        5
+ABC RESULTS:   gf180mcu_fd_sc_mcu7t5v0__nor2_1 cells:       15
+ABC RESULTS:        internal signals:       31
+ABC RESULTS:           input signals:       21
+ABC RESULTS:          output signals:       20
+Removing temp directory.
+
+13. Executing SETUNDEF pass (replace undef values with defined constants).
+
+14. Executing HILOMAP pass (mapping to constant drivers).
+
+15. Executing SPLITNETS pass (splitting up multi-bit signals).
+
+16. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \cntr_example..
+Removed 0 unused cells and 269 unused wires.
+<suppressed ~1 debug messages>
+
+17. Executing INSBUF pass (insert buffer cells for connected wires).
+
+18. Executing CHECK pass (checking for obvious problems).
+Checking module cntr_example...
+Warning: Wire cntr_example.\io_out [37] is used but has no driver.
+Warning: Wire cntr_example.\io_out [36] is used but has no driver.
+Warning: Wire cntr_example.\io_out [35] is used but has no driver.
+Warning: Wire cntr_example.\io_out [34] is used but has no driver.
+Warning: Wire cntr_example.\io_out [33] is used but has no driver.
+Warning: Wire cntr_example.\io_out [32] is used but has no driver.
+Warning: Wire cntr_example.\io_out [31] is used but has no driver.
+Warning: Wire cntr_example.\io_out [30] is used but has no driver.
+Warning: Wire cntr_example.\io_out [29] is used but has no driver.
+Warning: Wire cntr_example.\io_out [28] is used but has no driver.
+Warning: Wire cntr_example.\io_out [27] is used but has no driver.
+Warning: Wire cntr_example.\io_out [26] is used but has no driver.
+Warning: Wire cntr_example.\io_out [25] is used but has no driver.
+Warning: Wire cntr_example.\io_out [24] is used but has no driver.
+Warning: Wire cntr_example.\io_out [23] is used but has no driver.
+Warning: Wire cntr_example.\io_out [22] is used but has no driver.
+Warning: Wire cntr_example.\io_out [21] is used but has no driver.
+Warning: Wire cntr_example.\io_out [20] is used but has no driver.
+Warning: Wire cntr_example.\io_out [19] is used but has no driver.
+Warning: Wire cntr_example.\io_out [18] is used but has no driver.
+Warning: Wire cntr_example.\io_out [17] is used but has no driver.
+Warning: Wire cntr_example.\io_out [16] is used but has no driver.
+Warning: Wire cntr_example.\io_out [15] is used but has no driver.
+Warning: Wire cntr_example.\io_out [14] is used but has no driver.
+Warning: Wire cntr_example.\io_out [13] is used but has no driver.
+Warning: Wire cntr_example.\io_out [12] is used but has no driver.
+Warning: Wire cntr_example.\io_out [11] is used but has no driver.
+Warning: Wire cntr_example.\io_out [10] is used but has no driver.
+Warning: Wire cntr_example.\io_out [9] is used but has no driver.
+Warning: Wire cntr_example.\io_out [8] is used but has no driver.
+Warning: Wire cntr_example.\io_out [7] is used but has no driver.
+Warning: Wire cntr_example.\io_out [6] is used but has no driver.
+Warning: Wire cntr_example.\io_out [5] is used but has no driver.
+Warning: Wire cntr_example.\io_out [4] is used but has no driver.
+Warning: Wire cntr_example.\io_out [3] is used but has no driver.
+Warning: Wire cntr_example.\io_out [2] is used but has no driver.
+Warning: Wire cntr_example.\io_out [1] is used but has no driver.
+Warning: Wire cntr_example.\io_out [0] is used but has no driver.
+Found and reported 38 problems.
+
+19. Printing statistics.
+
+=== cntr_example ===
+
+   Number of wires:                 50
+   Number of wire bits:             87
+   Number of public wires:           3
+   Number of public wire bits:      40
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              0
+   Number of cells:                 85
+     gf180mcu_fd_sc_mcu7t5v0__aoi21_1     10
+     gf180mcu_fd_sc_mcu7t5v0__buf_1      1
+     gf180mcu_fd_sc_mcu7t5v0__dffq_1     20
+     gf180mcu_fd_sc_mcu7t5v0__inv_1      1
+     gf180mcu_fd_sc_mcu7t5v0__nand2_1      5
+     gf180mcu_fd_sc_mcu7t5v0__nand3_1      5
+     gf180mcu_fd_sc_mcu7t5v0__nor2_1     15
+     gf180mcu_fd_sc_mcu7t5v0__oai21_1      5
+     gf180mcu_fd_sc_mcu7t5v0__tiel     18
+     gf180mcu_fd_sc_mcu7t5v0__xor2_1      5
+
+   Chip area for module '\cntr_example': 2177.638400
+
+20. Executing Verilog backend.
+
+20.1. Executing BMUXMAP pass.
+
+20.2. Executing DEMUXMAP pass.
+Dumping module `\cntr_example'.
+
+Warnings: 88 unique messages, 166 total
+End of script. Logfile hash: 383cbbea59, CPU: user 1.22s system 0.04s, MEM: 58.29 MB peak
+Yosys 0.22 (git sha1 f109fa3d4c5, gcc 8.3.1 -fPIC -Os)
+Time spent: 30% 1x dfflibmap (0 sec), 30% 4x stat (0 sec), ...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/synthesis/2-sta.log b/openlane/cntr_example/runs/cntr_example/logs/synthesis/2-sta.log
new file mode 100644
index 0000000..bc96fa2
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/logs/synthesis/2-sta.log
@@ -0,0 +1,457 @@
+OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO ODB-0222] Reading LEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef
+[INFO ODB-0223]     Created 13 technology layers
+[INFO ODB-0224]     Created 60 technology vias
+[INFO ODB-0225]     Created 229 library cells
+[INFO ODB-0226] Finished LEF file:  /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef
+Reading netlist...
+[INFO]: Setting output delay to: 13.0
+[INFO]: Setting input delay to: 13.0
+[INFO]: Setting load to: 0.07291
+[INFO]: Setting clock uncertainty to: 0.25
+[INFO]: Setting clock transition to: 0.15
+[INFO]: Setting timing derate to: 0.5 %
+min_report
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.05    1.46    1.46 v _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     3    0.08                           io_out[18] (net)
+                  1.05    0.00    1.46 v _052_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.47    0.44    1.90 ^ _052_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.00                           _023_ (net)
+                  0.47    0.00    1.90 ^ _055_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  0.17    0.14    2.03 v _055_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     1    0.00                           _002_ (net)
+                  0.17    0.00    2.03 v _096_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  2.03   data arrival time
+
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                                  0.25 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.07    0.32   library hold time
+                                  0.32   data required time
+-----------------------------------------------------------------------------
+                                  0.32   data required time
+                                 -2.03   data arrival time
+-----------------------------------------------------------------------------
+                                  1.72   slack (MET)
+
+
+Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.05    1.46    1.46 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     3    0.08                           io_out[2] (net)
+                  1.05    0.00    1.46 v _061_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.47    0.44    1.90 ^ _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.00                           _028_ (net)
+                  0.47    0.00    1.90 ^ _064_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  0.17    0.14    2.03 v _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     1    0.00                           _006_ (net)
+                  0.17    0.00    2.03 v _100_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  2.03   data arrival time
+
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                                  0.25 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.07    0.32   library hold time
+                                  0.32   data required time
+-----------------------------------------------------------------------------
+                                  0.32   data required time
+                                 -2.03   data arrival time
+-----------------------------------------------------------------------------
+                                  1.72   slack (MET)
+
+
+Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.05    1.46    1.46 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     3    0.08                           io_out[6] (net)
+                  1.05    0.00    1.46 v _070_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.47    0.44    1.90 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.00                           _033_ (net)
+                  0.47    0.00    1.90 ^ _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  0.17    0.14    2.03 v _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     1    0.00                           _010_ (net)
+                  0.17    0.00    2.03 v _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  2.03   data arrival time
+
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                                  0.25 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.07    0.32   library hold time
+                                  0.32   data required time
+-----------------------------------------------------------------------------
+                                  0.32   data required time
+                                 -2.03   data arrival time
+-----------------------------------------------------------------------------
+                                  1.72   slack (MET)
+
+
+Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.05    1.46    1.46 v _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     3    0.08                           io_out[10] (net)
+                  1.05    0.00    1.46 v _079_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.47    0.44    1.90 ^ _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.00                           _038_ (net)
+                  0.47    0.00    1.90 ^ _082_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  0.17    0.14    2.03 v _082_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     1    0.00                           _014_ (net)
+                  0.17    0.00    2.03 v _108_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  2.03   data arrival time
+
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                                  0.25 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.07    0.32   library hold time
+                                  0.32   data required time
+-----------------------------------------------------------------------------
+                                  0.32   data required time
+                                 -2.03   data arrival time
+-----------------------------------------------------------------------------
+                                  1.72   slack (MET)
+
+
+Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  1.05    1.46    1.46 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     3    0.08                           io_out[14] (net)
+                  1.05    0.00    1.46 v _088_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+                  0.47    0.44    1.90 ^ _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+     1    0.00                           _043_ (net)
+                  0.47    0.00    1.90 ^ _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+                  0.17    0.14    2.03 v _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+     1    0.00                           _018_ (net)
+                  0.17    0.00    2.03 v _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                                  2.03   data arrival time
+
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                          0.25    0.25   clock uncertainty
+                          0.00    0.25   clock reconvergence pessimism
+                                  0.25 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                          0.07    0.32   library hold time
+                                  0.32   data required time
+-----------------------------------------------------------------------------
+                                  0.32   data required time
+                                 -2.03   data arrival time
+-----------------------------------------------------------------------------
+                                  1.72   slack (MET)
+
+
+min_report_end
+max_report
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.35    2.41    2.41 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.10                           io_out[0] (net)
+                  2.35    0.00    2.41 ^ io_out[0] (out)
+                                  2.41   data arrival time
+
+                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (ideal)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.41   data arrival time
+-----------------------------------------------------------------------------
+                                 49.34   slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[12] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.35    2.41    2.41 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.10                           io_out[12] (net)
+                  2.35    0.00    2.41 ^ io_out[12] (out)
+                                  2.41   data arrival time
+
+                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (ideal)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.41   data arrival time
+-----------------------------------------------------------------------------
+                                 49.34   slack (MET)
+
+
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.35    2.41    2.41 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.10                           io_out[16] (net)
+                  2.35    0.00    2.41 ^ io_out[16] (out)
+                                  2.41   data arrival time
+
+                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (ideal)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.41   data arrival time
+-----------------------------------------------------------------------------
+                                 49.34   slack (MET)
+
+
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[4] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.35    2.41    2.41 ^ _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.10                           io_out[4] (net)
+                  2.35    0.00    2.41 ^ io_out[4] (out)
+                                  2.41   data arrival time
+
+                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (ideal)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.41   data arrival time
+-----------------------------------------------------------------------------
+                                 49.34   slack (MET)
+
+
+Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[8] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.35    2.41    2.41 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.10                           io_out[8] (net)
+                  2.35    0.00    2.41 ^ io_out[8] (out)
+                                  2.41   data arrival time
+
+                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (ideal)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.41   data arrival time
+-----------------------------------------------------------------------------
+                                 49.34   slack (MET)
+
+
+max_report_end
+check_report
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout     Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------------
+                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
+                          0.00    0.00   clock network delay (ideal)
+                  0.15    0.00    0.00 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+                  2.35    2.41    2.41 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+     6    0.10                           io_out[0] (net)
+                  2.35    0.00    2.41 ^ io_out[0] (out)
+                                  2.41   data arrival time
+
+                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
+                          0.00   65.00   clock network delay (ideal)
+                         -0.25   64.75   clock uncertainty
+                          0.00   64.75   clock reconvergence pessimism
+                        -13.00   51.75   output external delay
+                                 51.75   data required time
+-----------------------------------------------------------------------------
+                                 51.75   data required time
+                                 -2.41   data arrival time
+-----------------------------------------------------------------------------
+                                 49.34   slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
+check_report_end
+check_slew
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
+check_slew_end
+tns_report
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
+tns_report_end
+wns_report
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
+wns_report_end
+worst_slack
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 49.34
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 1.72
+worst_slack_end
+clock_skew
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency      CRPR       Skew
+_094_/CLK ^
+   0.23
+_094_/CLK ^
+   0.21      0.00       0.02
+
+clock_skew_end
+power_report
+
+===========================================================================
+ report_power
+============================================================================
+Group                  Internal  Switching    Leakage      Total
+                          Power      Power      Power      Power (Watts)
+----------------------------------------------------------------
+Sequential             6.99e-05   1.61e-05   1.89e-09   8.60e-05  92.8%
+Combinational          4.47e-06   2.19e-06   2.66e-09   6.66e-06   7.2%
+Macro                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+----------------------------------------------------------------
+Total                  7.43e-05   1.83e-05   4.55e-09   9.26e-05 100.0%
+                          80.2%      19.8%       0.0%
+power_report_end
+area_report
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 2178 u^2 100% utilization.
+area_report_end
+[WARNING] Did not save OpenROAD database!
+Writing SDF to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/synthesis/cntr_example.sdf...
diff --git a/openlane/cntr_example/runs/cntr_example/openlane.log b/openlane/cntr_example/runs/cntr_example/openlane.log
index d00491f..c935a06 100644
--- a/openlane/cntr_example/runs/cntr_example/openlane.log
+++ b/openlane/cntr_example/runs/cntr_example/openlane.log
@@ -1 +1,51 @@
-1
+[INFO]: Run Directory: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29
+[INFO]: Preparing LEF files for the nom corner...
+[INFO]: Running Synthesis (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/synthesis/1-synthesis.log)...
+[INFO]: Running Single-Corner Static Timing Analysis (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/synthesis/2-sta.log)...
+[INFO]: Running Initial Floorplanning (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan/3-initial_fp.log)...
+[INFO]: Floorplanned with width 1486.24 and height 1466.08.
+[INFO]: Running IO Placement...
+[INFO]: Running Tap/Decap Insertion (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan/5-tap.log)...
+[INFO]: Power planning with power {vdd} and ground {vss}...
+[INFO]: Generating PDN (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan/6-pdn.log)...
+[INFO]: Running Global Placement (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/placement/7-global.log)...
+[INFO]: Running Placement Resizer Design Optimizations (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/placement/8-resizer.log)...
+[INFO]: Running Detailed Placement (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/placement/9-detailed.log)...
+[INFO]: Running Clock Tree Synthesis (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/cts/10-cts.log)...
+[INFO]: Running Placement Resizer Timing Optimizations (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/cts/11-resizer.log)...
+[INFO]: Running Global Routing Resizer Timing Optimizations (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/12-resizer.log)...
+[INFO]: Running Diode Insertion (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/13-diodes.log)...
+[INFO]: Running Detailed Placement (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/14-diode_legalization.log)...
+[INFO]: Running Fill Insertion (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/15-fill.log)...
+[INFO]: Running Global Routing (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/16-global.log)...
+[INFO]: Writing Verilog (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/16-global_write_netlist.log)...
+[INFO]: Running Detailed Routing (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/18-detailed.log)...
+[INFO]: No DRC violations after detailed routing.
+[INFO]: Checking Wire Lengths (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/19-wire_lengths.log)...
+[INFO]: Running SPEF Extraction at the nom process corner (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/20-parasitics_extraction.nom.log)...
+[INFO]: Running Multi-Corner Static Timing Analysis at the nom process corner (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/21-rcx_mcsta.nom.log)...
+[INFO]: Running Single-Corner Static Timing Analysis at the nom process corner (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/22-rcx_sta.log)...
+[INFO]: Running Magic to generate various views...
+[INFO]: Streaming out GDSII with Magic (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/23-gdsii.log)...
+[INFO]: Generating MAGLEF views...
+[INFO]: Running Magic Spice Export from LEF (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/24-spice.log)...
+[INFO]: Writing Powered Verilog (logs: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/25-write_powered_def.log, ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/25-write_powered_verilog.log)...
+[INFO]: Writing Verilog (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/25-write_powered_verilog.log)...
+[INFO]: Running LVS (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/27-lvs.lef.log)...
+[INFO]: Running Magic DRC (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/28-drc.log)...
+[INFO]: Converting Magic DRC database to various tool-readable formats...
+[INFO]: No DRC violations after GDS streaming out.
+[INFO]: Running OpenROAD Antenna Rule Checker (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/29-antenna.log)...
+[WARNING]: This PDK does not support the Circuit Validity Checker, skipping...
+[INFO]: Saving current set of views in '../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/final'...
+[INFO]: Saving current set of views in '../home/htf6ry/gf180-demo'...
+[INFO]: Saving runtime environment...
+[INFO]: Generating final set of reports...
+[INFO]: Created manufacturability report at '../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/manufacturability.rpt'.
+[INFO]: Created metrics report at '../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/metrics.csv'.
+[WARNING]: There are max slew violations in the design at the typical corner. Please refer to '../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/22-rcx_sta.slew.rpt'.
+[WARNING]: There are max capacitance violations in the design at the typical corner. Please refer to '../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/22-rcx_sta.slew.rpt'.
+[INFO]: There are no hold violations in the design at the typical corner.
+[INFO]: There are no setup violations in the design at the typical corner.
+[SUCCESS]: Flow complete.
+[INFO]: Note that the following warnings have been generated:
diff --git a/openlane/cntr_example/runs/cntr_example/runtime.yaml b/openlane/cntr_example/runs/cntr_example/runtime.yaml
new file mode 100644
index 0000000..c7ea24c
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/runtime.yaml
@@ -0,0 +1,97 @@
+- status: 0 - openlane design prep
+  runtime_s: 1.83
+  runtime_ts: 0h0m1s830ms
+- status: 1 - synthesis - yosys
+  runtime_s: 2.21
+  runtime_ts: 0h0m2s209ms
+- status: 2 - sta - openroad
+  runtime_s: 0.81
+  runtime_ts: 0h0m0s807ms
+- status: 3 - floorplan initialization - openroad
+  runtime_s: 1.47
+  runtime_ts: 0h0m1s468ms
+- status: 4 - ioplace - openroad
+  runtime_s: 0.71
+  runtime_ts: 0h0m0s714ms
+- status: 5 - tap/decap insertion - openroad
+  runtime_s: 0.81
+  runtime_ts: 0h0m0s806ms
+- status: 6 - pdn generation - openroad
+  runtime_s: 1.91
+  runtime_ts: 0h0m1s907ms
+- status: 7 - global placement - openroad
+  runtime_s: 15.42
+  runtime_ts: 0h0m15s419ms
+- status: 8 - resizer design optimizations - openroad
+  runtime_s: 1.34
+  runtime_ts: 0h0m1s345ms
+- status: 9 - detailed placement - openroad
+  runtime_s: 0.98
+  runtime_ts: 0h0m0s977ms
+- status: 10 - cts - openroad
+  runtime_s: 30.52
+  runtime_ts: 0h0m30s522ms
+- status: 11 - resizer timing optimizations - openroad
+  runtime_s: 1.27
+  runtime_ts: 0h0m1s274ms
+- status: 12 - resizer timing optimizations - openroad
+  runtime_s: 1.43
+  runtime_ts: 0h0m1s427ms
+- status: 14 - detailed placement - openroad
+  runtime_s: 1.0
+  runtime_ts: 0h0m0s998ms
+- status: 14 - diode insertion - openlane
+  runtime_s: 1.09
+  runtime_ts: 0h0m1s90ms
+- status: 15 - fill insertion - openroad
+  runtime_s: 1.45
+  runtime_ts: 0h0m1s453ms
+- status: 17 - write verilog - openroad
+  runtime_s: 0.99
+  runtime_ts: 0h0m0s993ms
+- status: 17 - global routing - openroad
+  runtime_s: 1.08
+  runtime_ts: 0h0m1s84ms
+- status: 18 - detailed_routing - openroad
+  runtime_s: 31.16
+  runtime_ts: 0h0m31s158ms
+- status: 19 - wire lengths - openlane
+  runtime_s: 0.72
+  runtime_ts: 0h0m0s720ms
+- status: 20 - parasitics extraction - openroad
+  runtime_s: 1.15
+  runtime_ts: 0h0m1s145ms
+- status: 21 - sta - openroad
+  runtime_s: 2.87
+  runtime_ts: 0h0m2s865ms
+- status: 22 - sta - openroad
+  runtime_s: 1.27
+  runtime_ts: 0h0m1s270ms
+- status: 23 - gdsii - magic
+  runtime_s: 8.63
+  runtime_ts: 0h0m8s634ms
+- status: 24 - spice extraction - magic
+  runtime_s: 15.51
+  runtime_ts: 0h0m15s506ms
+- status: 26 - write verilog - openroad
+  runtime_s: 1.04
+  runtime_ts: 0h0m1s42ms
+- status: 26 - write powered verilog - openlane
+  runtime_s: 1.14
+  runtime_ts: 0h0m1s141ms
+- status: 27 - lvs - netgen
+  runtime_s: 1.01
+  runtime_ts: 0h0m1s12ms
+- status: 28 - drc - magic
+  runtime_s: 160.14
+  runtime_ts: 0h2m40s137ms
+- status: 29 - antenna check - openroad
+  runtime_s: 0.99
+  runtime_ts: 0h0m0s991ms
+---
+- status: routed
+  runtime_s: 100.0
+  runtime_ts: 0h1m40s0ms
+- status: flow completed
+  runtime_s: 295.0
+  runtime_ts: 0h4m55s0ms
diff --git a/openlane/cntr_example/runs/cntr_example/warnings.log b/openlane/cntr_example/runs/cntr_example/warnings.log
new file mode 100644
index 0000000..6eebec7
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/warnings.log
@@ -0,0 +1,3 @@
+[WARNING]: This PDK does not support the Circuit Validity Checker, skipping...
+[WARNING]: There are max slew violations in the design at the typical corner. Please refer to '../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/22-rcx_sta.slew.rpt'.
+[WARNING]: There are max capacitance violations in the design at the typical corner. Please refer to '../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/22-rcx_sta.slew.rpt'.