OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO]: Setting signal min routing layer to: Metal2 and clock min routing layer to Metal2. 
[INFO]: Setting signal max routing layer to: Metal4 and clock max routing layer to Metal4. 
-congestion_iterations 50 -verbose
[INFO GRT-0020] Min routing layer: Metal2
[INFO GRT-0021] Max routing layer: Metal4
[INFO GRT-0022] Global adjustment: 30%
[INFO GRT-0023] Grid origin: (0, 0)
[INFO GRT-0043] No OR_DEFAULT vias defined.
[INFO GRT-0088] Layer Metal1  Track-Pitch = 0.5600  line-2-Via Pitch: 0.5450
[INFO GRT-0088] Layer Metal2  Track-Pitch = 0.5600  line-2-Via Pitch: 0.5800
[INFO GRT-0088] Layer Metal3  Track-Pitch = 0.5600  line-2-Via Pitch: 0.5800
[INFO GRT-0088] Layer Metal4  Track-Pitch = 0.5600  line-2-Via Pitch: 0.5800
[INFO GRT-0019] Found 4 clock nets.
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 12
[INFO GRT-0003] Macros: 0
[INFO GRT-0004] Blockages: 0

[INFO GRT-0053] Routing resources analysis:
          Routing      Original      Derated      Resource
Layer     Direction    Resources     Resources    Reduction (%)
---------------------------------------------------------------
Metal1     Horizontal          0             0          0.00%
Metal2     Vertical       443576        286032          35.52%
Metal3     Horizontal     443576        286032          35.52%
Metal4     Vertical       443576        283057          36.19%
---------------------------------------------------------------

[INFO GRT-0197] Via related to pin nodes: 469
[INFO GRT-0198] Via related Steiner nodes: 11
[INFO GRT-0199] Via filling finished.
[INFO GRT-0111] Final number of vias: 595
[INFO GRT-0112] Final usage 3D: 9430

[INFO GRT-0096] Final congestion report:
Layer         Resource        Demand        Usage (%)    Max H / Max V / Total Overflow
---------------------------------------------------------------------------------------
Metal1               0             0            0.00%             0 /  0 /  0
Metal2          286032          6795            2.38%             0 /  0 /  0
Metal3          286032           687            0.24%             0 /  0 /  0
Metal4          283057           163            0.06%             0 /  0 /  0
---------------------------------------------------------------------------------------
Total           855121          7645            0.89%             0 /  0 /  0

[INFO GRT-0018] Total wirelength: 68006 um
[INFO GRT-0014] Routed nets: 125
[INFO]: Setting RC values...
[INFO RSZ-0033] No hold violations found.
Placement Analysis
---------------------------------
total displacement          0.0 u
average displacement        0.0 u
max displacement            0.0 u
original HPWL           64289.9 u
legalized HPWL          64527.1 u
delta HPWL                    0 %

[INFO DPL-0020] Mirrored 67 instances
[INFO DPL-0021] HPWL before           64527.1 u
[INFO DPL-0022] HPWL after            64289.9 u
[INFO DPL-0023] HPWL delta               -0.4 %
Setting global connections for newly added cells...
Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/12-cntr_example.odb...
Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/12-cntr_example.nl.v...
Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/12-cntr_example.pnl.v...
Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/12-cntr_example.def...
Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/12-cntr_example.sdc...
min_report

===========================================================================
report_checks -path_delay min (Hold)
============================================================================
Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.23    0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.22    0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.51 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.33    0.77    1.28 v _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     3    0.03                           net3 (net)
                  0.33    0.01    1.29 v _096_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
                  0.27    0.22    1.51 ^ _096_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
     1    0.00                           _046_ (net)
                  0.27    0.00    1.51 ^ _099_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
                  0.29    0.23    1.74 v _099_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
     1    0.02                           _014_ (net)
                  0.29    0.00    1.74 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                  1.74   data arrival time

                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                          0.25    0.82   clock uncertainty
                         -0.05    0.76   clock reconvergence pessimism
                          0.03    0.80   library hold time
                                  0.80   data required time
-----------------------------------------------------------------------------
                                  0.80   data required time
                                 -1.74   data arrival time
-----------------------------------------------------------------------------
                                  0.95   slack (MET)


Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.23    0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.22    0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.51 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.34    0.77    1.29 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     3    0.03                           net18 (net)
                  0.34    0.01    1.30 v _086_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
                  0.27    0.22    1.52 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
     1    0.00                           _040_ (net)
                  0.27    0.00    1.52 ^ _089_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
                  0.29    0.23    1.75 v _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
     1    0.02                           _010_ (net)
                  0.29    0.00    1.75 v _122_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                  1.75   data arrival time

                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                          0.25    0.82   clock uncertainty
                         -0.05    0.76   clock reconvergence pessimism
                          0.03    0.80   library hold time
                                  0.80   data required time
-----------------------------------------------------------------------------
                                  0.80   data required time
                                 -1.75   data arrival time
-----------------------------------------------------------------------------
                                  0.95   slack (MET)


Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.23    0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.22    0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.51 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.35    0.78    1.30 v _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     3    0.03                           net14 (net)
                  0.36    0.01    1.31 v _076_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
                  0.27    0.22    1.53 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
     1    0.00                           _034_ (net)
                  0.27    0.00    1.53 ^ _079_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
                  0.29    0.23    1.76 v _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
     1    0.02                           _006_ (net)
                  0.29    0.00    1.77 v _118_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                  1.77   data arrival time

                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                          0.25    0.82   clock uncertainty
                         -0.05    0.76   clock reconvergence pessimism
                          0.03    0.80   library hold time
                                  0.80   data required time
-----------------------------------------------------------------------------
                                  0.80   data required time
                                 -1.77   data arrival time
-----------------------------------------------------------------------------
                                  0.97   slack (MET)


Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.23    0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.23    0.52 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
                  0.10    0.00    0.52 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.35    0.78    1.30 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     3    0.03                           net7 (net)
                  0.35    0.01    1.31 v _106_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
                  0.27    0.23    1.53 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
     1    0.00                           _052_ (net)
                  0.27    0.00    1.53 ^ _109_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
                  0.30    0.24    1.77 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
     1    0.02                           _018_ (net)
                  0.30    0.00    1.78 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                  1.78   data arrival time

                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                          0.25    0.82   clock uncertainty
                         -0.05    0.77   clock reconvergence pessimism
                          0.03    0.80   library hold time
                                  0.80   data required time
-----------------------------------------------------------------------------
                                  0.80   data required time
                                 -1.78   data arrival time
-----------------------------------------------------------------------------
                                  0.98   slack (MET)


Startpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.23    0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.23    0.52 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
                  0.10    0.00    0.52 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.36    0.79    1.31 v _114_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     3    0.03                           net11 (net)
                  0.36    0.01    1.32 v _064_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
                  0.27    0.22    1.54 ^ _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
     1    0.00                           _026_ (net)
                  0.27    0.00    1.54 ^ _068_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
                  0.30    0.24    1.78 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
     1    0.02                           _002_ (net)
                  0.30    0.00    1.78 v _114_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                  1.78   data arrival time

                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                          0.25    0.82   clock uncertainty
                         -0.05    0.77   clock reconvergence pessimism
                          0.03    0.80   library hold time
                                  0.80   data required time
-----------------------------------------------------------------------------
                                  0.80   data required time
                                 -1.78   data arrival time
-----------------------------------------------------------------------------
                                  0.99   slack (MET)


min_report_end
max_report

===========================================================================
report_checks -path_delay max (Setup)
============================================================================
Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.41    0.94    1.50 ^ _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     2    0.02                           net13 (net)
                  0.41    0.01    1.51 ^ fanout25/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
                  0.53    0.51    2.02 ^ fanout25/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
     4    0.03                           net25 (net)
                  0.53    0.00    2.02 ^ output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
                  0.34    0.51    2.53 ^ output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
     1    0.07                           io_out[1] (net)
                  0.34    0.00    2.53 ^ io_out[1] (out)
                                  2.53   data arrival time

                         65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (propagated)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -2.53   data arrival time
-----------------------------------------------------------------------------
                                 49.22   slack (MET)


Startpoint: _121_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[5] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _121_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.40    0.93    1.50 ^ _121_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     2    0.02                           net17 (net)
                  0.40    0.01    1.51 ^ fanout24/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
                  0.50    0.49    2.00 ^ fanout24/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
     4    0.03                           net24 (net)
                  0.50    0.00    2.00 ^ output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
                  0.34    0.51    2.50 ^ output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
     1    0.07                           io_out[5] (net)
                  0.34    0.00    2.50 ^ io_out[5] (out)
                                  2.50   data arrival time

                         65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (propagated)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -2.50   data arrival time
-----------------------------------------------------------------------------
                                 49.25   slack (MET)


Startpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[18] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.59    1.04    1.61 ^ _114_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     3    0.03                           net11 (net)
                  0.59    0.01    1.63 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
                  0.34    0.52    2.15 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
     1    0.07                           io_out[18] (net)
                  0.34    0.00    2.15 ^ io_out[18] (out)
                                  2.15   data arrival time

                         65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (propagated)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -2.15   data arrival time
-----------------------------------------------------------------------------
                                 49.60   slack (MET)


Startpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[19] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.58    1.04    1.60 ^ _115_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     2    0.03                           net12 (net)
                  0.58    0.01    1.62 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
                  0.34    0.52    2.14 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
     1    0.07                           io_out[19] (net)
                  0.34    0.00    2.14 ^ io_out[19] (out)
                                  2.14   data arrival time

                         65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (propagated)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -2.14   data arrival time
-----------------------------------------------------------------------------
                                 49.61   slack (MET)


Startpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.57    1.03    1.60 ^ _116_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     3    0.03                           net2 (net)
                  0.57    0.01    1.62 ^ output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
                  0.34    0.52    2.14 ^ output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
     1    0.07                           io_out[0] (net)
                  0.34    0.00    2.14 ^ io_out[0] (out)
                                  2.14   data arrival time

                         65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (propagated)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -2.14   data arrival time
-----------------------------------------------------------------------------
                                 49.61   slack (MET)


max_report_end
check_report

===========================================================================
report_checks -unconstrained
============================================================================
Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.41    0.94    1.50 ^ _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     2    0.02                           net13 (net)
                  0.41    0.01    1.51 ^ fanout25/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
                  0.53    0.51    2.02 ^ fanout25/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
     4    0.03                           net25 (net)
                  0.53    0.00    2.02 ^ output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
                  0.34    0.51    2.53 ^ output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
     1    0.07                           io_out[1] (net)
                  0.34    0.00    2.53 ^ io_out[1] (out)
                                  2.53   data arrival time

                         65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (propagated)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -2.53   data arrival time
-----------------------------------------------------------------------------
                                 49.22   slack (MET)


===========================================================================
report_checks --slack_max -0.01
============================================================================
No paths found.
check_report_end
check_slew

===========================================================================
 report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
max fanout

Pin                                   Limit Fanout  Slack
---------------------------------------------------------
clkbuf_1_0__f_wb_clk_i/Z                  4     11     -7 (VIOLATED)
clkbuf_1_1__f_wb_clk_i/Z                  4      9     -5 (VIOLATED)


===========================================================================
max slew violation count 0
max fanout violation count 2
max cap violation count 0
============================================================================
check_slew_end
tns_report

===========================================================================
 report_tns
============================================================================
tns 0.00
tns_report_end
wns_report

===========================================================================
 report_wns
============================================================================
wns 0.00
wns_report_end
worst_slack

===========================================================================
 report_worst_slack -max (Setup)
============================================================================
worst slack 49.22

===========================================================================
 report_worst_slack -min (Hold)
============================================================================
worst slack 0.95
worst_slack_end
clock_skew

===========================================================================
 report_clock_skew
============================================================================
Clock wb_clk_i
Latency      CRPR       Skew
_114_/CLK ^
   0.57
_115_/CLK ^
   0.51     -0.03       0.03

clock_skew_end
power_report

===========================================================================
 report_power
============================================================================
Group                  Internal  Switching    Leakage      Total
                          Power      Power      Power      Power (Watts)
----------------------------------------------------------------
Sequential             1.66e-04   1.21e-05   4.08e-09   1.78e-04  39.0%
Combinational          1.83e-04   9.48e-05   7.47e-07   2.79e-04  61.0%
Macro                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
----------------------------------------------------------------
Total                  3.49e-04   1.07e-04   7.51e-07   4.57e-04 100.0%
                          76.4%      23.4%       0.2%
power_report_end
area_report

===========================================================================
 report_design_area
============================================================================
Design area 67750 u^2 3% utilization.
area_report_end
Setting global connections for newly added cells...
Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/12-cntr_example.odb...
Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/12-cntr_example.nl.v...
Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/12-cntr_example.pnl.v...
Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/12-cntr_example.def...
Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/12-cntr_example.sdc...