OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO]: Setting RC values...
[INFO]: Configuring cts characterization...
[INFO]: Performing clock tree synthesis...
[INFO]: Looking for the following net(s): wb_clk_i
[INFO]: Running Clock Tree Synthesis...
[INFO CTS-0049] Characterization buffer is: gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.
[INFO CTS-0038] Number of created patterns = 50000.
[INFO CTS-0038] Number of created patterns = 100000.
[INFO CTS-0039] Number of created patterns = 137808.
[INFO CTS-0084] Compiling LUT.
Min. len    Max. len    Min. cap    Max. cap    Min. slew   Max. slew
2           8           1           34          1           79          
[WARNING CTS-0043] 4752 wires are pure wire and no slew degradation.
TritonCTS forced slew degradation on these wires.
[INFO CTS-0046]     Number of wire segments: 137808.
[INFO CTS-0047]     Number of keys in characterization LUT: 1810.
[INFO CTS-0048]     Actual min input cap: 1.
[INFO CTS-0007] Net "wb_clk_i" found for clock "wb_clk_i".
[INFO CTS-0010]  Clock net "wb_clk_i" has 20 sinks.
[INFO CTS-0008] TritonCTS found 1 clock nets.
[INFO CTS-0097] Characterization used 2 buffer(s) types.
[INFO CTS-0027] Generating H-Tree topology for net wb_clk_i.
[INFO CTS-0028]  Total number of sinks: 20.
[INFO CTS-0029]  Sinks will be clustered in groups of up to 25 and with maximum cluster diameter of 50.0 um.
[INFO CTS-0030]  Number of static layers: 0.
[INFO CTS-0020]  Wire segment unit: 38000  dbu (19 um).
[INFO CTS-0023]  Original sink region: [(725760, 43120), (788480, 145040)].
[INFO CTS-0024]  Normalized sink region: [(19.0989, 1.13474), (20.7495, 3.81684)].
[INFO CTS-0025]     Width:  1.6505.
[INFO CTS-0026]     Height: 2.6821.
[WARNING CTS-0045] Creating fake entries in the LUT.
 Level 1
    Direction: Vertical
    Sinks per sub-region: 10
    Sub-region size: 1.6505 X 1.3411
[INFO CTS-0034]     Segment length (rounded): 1.
    Key: 137808 inSlew: 1 inCap: 1 outSlew: 2 load: 1 length: 1 delay: 1
 Out of 20 sinks, 1 sinks closer to other cluster.
[INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
[INFO CTS-0035]  Number of sinks covered: 20.
[INFO CTS-0036]  Average source sink dist: 37560.00 dbu.
[INFO CTS-0037]  Number of outlier sinks: 0.
[INFO CTS-0018]     Created 3 clock buffers.
[INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
[INFO CTS-0013]     Maximum number of buffers in the clock path: 2.
[INFO CTS-0015]     Created 3 clock nets.
[INFO CTS-0016]     Fanout distribution for the current clock = 9:1, 11:1..
[INFO CTS-0017]     Max level of the clock tree: 1.
[INFO CTS-0098] Clock net "wb_clk_i"
[INFO CTS-0099]  Sinks 20
[INFO CTS-0100]  Leaf buffers 0
[INFO CTS-0101]  Average sink wire length 115.90 um
[INFO CTS-0102]  Path depth 2 - 2
[INFO]: Repairing long wires on clock nets...
[INFO RSZ-0058] Using max wire length 18670um.
Setting global connections for newly added cells...
Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/cts/cntr_example.odb...
Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/cts/cntr_example.def...
Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/cts/cntr_example.sdc...
[INFO]: Legalizing...
Placement Analysis
---------------------------------
total displacement         52.3 u
average displacement        0.0 u
max displacement            9.5 u
original HPWL           64247.1 u
legalized HPWL          64527.1 u
delta HPWL                    0 %

[INFO DPL-0020] Mirrored 67 instances
[INFO DPL-0021] HPWL before           64527.1 u
[INFO DPL-0022] HPWL after            64289.9 u
[INFO DPL-0023] HPWL delta               -0.4 %
Setting global connections for newly added cells...
Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/cts/cntr_example.odb...
Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/cts/cntr_example.def...
Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/cts/cntr_example.sdc...
cts_report
[INFO CTS-0003] Total number of Clock Roots: 1.
[INFO CTS-0004] Total number of Buffers Inserted: 3.
[INFO CTS-0005] Total number of Clock Subnets: 3.
[INFO CTS-0006] Total number of Sinks: 20.
cts_report_end
min_report

===========================================================================
report_checks -path_delay min (Hold)
============================================================================
Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.23    0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.22    0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.51 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.33    0.77    1.28 v _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     3    0.03                           net3 (net)
                  0.33    0.01    1.29 v _096_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
                  0.26    0.22    1.51 ^ _096_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
     1    0.00                           _046_ (net)
                  0.26    0.00    1.51 ^ _099_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
                  0.29    0.23    1.73 v _099_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
     1    0.02                           _014_ (net)
                  0.29    0.00    1.74 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                  1.74   data arrival time

                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                          0.25    0.82   clock uncertainty
                         -0.05    0.76   clock reconvergence pessimism
                          0.03    0.80   library hold time
                                  0.80   data required time
-----------------------------------------------------------------------------
                                  0.80   data required time
                                 -1.74   data arrival time
-----------------------------------------------------------------------------
                                  0.94   slack (MET)


Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.23    0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.22    0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.51 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.34    0.77    1.29 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     3    0.03                           net18 (net)
                  0.34    0.01    1.30 v _086_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
                  0.27    0.22    1.51 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
     1    0.00                           _040_ (net)
                  0.27    0.00    1.51 ^ _089_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
                  0.29    0.23    1.74 v _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
     1    0.02                           _010_ (net)
                  0.29    0.00    1.75 v _122_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                  1.75   data arrival time

                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                          0.25    0.82   clock uncertainty
                         -0.05    0.76   clock reconvergence pessimism
                          0.03    0.79   library hold time
                                  0.79   data required time
-----------------------------------------------------------------------------
                                  0.79   data required time
                                 -1.75   data arrival time
-----------------------------------------------------------------------------
                                  0.95   slack (MET)


Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.23    0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.22    0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.51 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.35    0.78    1.30 v _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     3    0.03                           net14 (net)
                  0.35    0.01    1.31 v _076_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
                  0.27    0.22    1.53 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
     1    0.00                           _034_ (net)
                  0.27    0.00    1.53 ^ _079_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
                  0.29    0.23    1.76 v _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
     1    0.02                           _006_ (net)
                  0.29    0.00    1.76 v _118_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                  1.76   data arrival time

                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                          0.25    0.82   clock uncertainty
                         -0.05    0.76   clock reconvergence pessimism
                          0.03    0.79   library hold time
                                  0.79   data required time
-----------------------------------------------------------------------------
                                  0.79   data required time
                                 -1.76   data arrival time
-----------------------------------------------------------------------------
                                  0.97   slack (MET)


Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.23    0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.23    0.52 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
                  0.10    0.00    0.52 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.34    0.78    1.30 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     3    0.03                           net7 (net)
                  0.35    0.01    1.31 v _106_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
                  0.27    0.22    1.53 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
     1    0.00                           _052_ (net)
                  0.27    0.00    1.53 ^ _109_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
                  0.30    0.24    1.77 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
     1    0.02                           _018_ (net)
                  0.30    0.00    1.77 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                  1.77   data arrival time

                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                          0.25    0.82   clock uncertainty
                         -0.05    0.77   clock reconvergence pessimism
                          0.03    0.80   library hold time
                                  0.80   data required time
-----------------------------------------------------------------------------
                                  0.80   data required time
                                 -1.77   data arrival time
-----------------------------------------------------------------------------
                                  0.98   slack (MET)


Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.23    0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.23    0.52 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
                  0.10    0.00    0.52 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.32    0.77    1.28 v _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     2    0.03                           net4 (net)
                  0.33    0.01    1.29 v _100_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
                  0.28    0.23    1.53 ^ _100_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
     1    0.00                           _049_ (net)
                  0.28    0.00    1.53 ^ _101_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
                  0.29    0.25    1.78 v _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
     1    0.02                           _015_ (net)
                  0.29    0.00    1.78 v _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                  1.78   data arrival time

                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                          0.25    0.82   clock uncertainty
                         -0.05    0.77   clock reconvergence pessimism
                          0.03    0.80   library hold time
                                  0.80   data required time
-----------------------------------------------------------------------------
                                  0.80   data required time
                                 -1.78   data arrival time
-----------------------------------------------------------------------------
                                  0.98   slack (MET)


min_report_end
max_report

===========================================================================
report_checks -path_delay max (Setup)
============================================================================
Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.41    0.93    1.50 ^ _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     2    0.02                           net13 (net)
                  0.41    0.01    1.51 ^ fanout25/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
                  0.52    0.50    2.01 ^ fanout25/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
     4    0.03                           net25 (net)
                  0.52    0.00    2.01 ^ output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
                  0.34    0.51    2.52 ^ output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
     1    0.07                           io_out[1] (net)
                  0.34    0.00    2.52 ^ io_out[1] (out)
                                  2.52   data arrival time

                         65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (propagated)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -2.52   data arrival time
-----------------------------------------------------------------------------
                                 49.23   slack (MET)


Startpoint: _121_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[5] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _121_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.40    0.93    1.50 ^ _121_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     2    0.02                           net17 (net)
                  0.40    0.01    1.50 ^ fanout24/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
                  0.50    0.49    1.99 ^ fanout24/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
     4    0.03                           net24 (net)
                  0.50    0.00    1.99 ^ output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
                  0.34    0.51    2.50 ^ output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
     1    0.07                           io_out[5] (net)
                  0.34    0.00    2.50 ^ io_out[5] (out)
                                  2.50   data arrival time

                         65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (propagated)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -2.50   data arrival time
-----------------------------------------------------------------------------
                                 49.25   slack (MET)


Startpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[18] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.58    1.04    1.61 ^ _114_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     3    0.03                           net11 (net)
                  0.58    0.01    1.62 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
                  0.34    0.52    2.15 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
     1    0.07                           io_out[18] (net)
                  0.34    0.00    2.15 ^ io_out[18] (out)
                                  2.15   data arrival time

                         65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (propagated)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -2.15   data arrival time
-----------------------------------------------------------------------------
                                 49.60   slack (MET)


Startpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.57    1.03    1.60 ^ _116_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     3    0.03                           net2 (net)
                  0.57    0.01    1.61 ^ output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
                  0.34    0.52    2.13 ^ output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
     1    0.07                           io_out[0] (net)
                  0.34    0.00    2.13 ^ io_out[0] (out)
                                  2.13   data arrival time

                         65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (propagated)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -2.13   data arrival time
-----------------------------------------------------------------------------
                                 49.62   slack (MET)


Startpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[19] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.57    1.03    1.60 ^ _115_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     2    0.03                           net12 (net)
                  0.58    0.01    1.61 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
                  0.34    0.52    2.13 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
     1    0.07                           io_out[19] (net)
                  0.34    0.00    2.13 ^ io_out[19] (out)
                                  2.13   data arrival time

                         65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (propagated)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -2.13   data arrival time
-----------------------------------------------------------------------------
                                 49.62   slack (MET)


max_report_end
check_report

===========================================================================
report_checks -unconstrained
============================================================================
Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.13    0.06    0.06 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.13    0.00    0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.11    0.26    0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.05                           clknet_0_wb_clk_i (net)
                  0.11    0.00    0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.10    0.25    0.57 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.10    0.00    0.57 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.41    0.93    1.50 ^ _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     2    0.02                           net13 (net)
                  0.41    0.01    1.51 ^ fanout25/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
                  0.52    0.50    2.01 ^ fanout25/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
     4    0.03                           net25 (net)
                  0.52    0.00    2.01 ^ output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
                  0.34    0.51    2.52 ^ output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
     1    0.07                           io_out[1] (net)
                  0.34    0.00    2.52 ^ io_out[1] (out)
                                  2.52   data arrival time

                         65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (propagated)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -2.52   data arrival time
-----------------------------------------------------------------------------
                                 49.23   slack (MET)


===========================================================================
report_checks --slack_max -0.01
============================================================================
No paths found.
check_report_end
check_slew

===========================================================================
 report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
max fanout

Pin                                   Limit Fanout  Slack
---------------------------------------------------------
clkbuf_1_0__f_wb_clk_i/Z                  4     11     -7 (VIOLATED)
clkbuf_1_1__f_wb_clk_i/Z                  4      9     -5 (VIOLATED)


===========================================================================
max slew violation count 0
max fanout violation count 2
max cap violation count 0
============================================================================
check_slew_end
tns_report

===========================================================================
 report_tns
============================================================================
tns 0.00
tns_report_end
wns_report

===========================================================================
 report_wns
============================================================================
wns 0.00
wns_report_end
worst_slack

===========================================================================
 report_worst_slack -max (Setup)
============================================================================
worst slack 49.23

===========================================================================
 report_worst_slack -min (Hold)
============================================================================
worst slack 0.94
worst_slack_end
clock_skew

===========================================================================
 report_clock_skew
============================================================================
Clock wb_clk_i
Latency      CRPR       Skew
_113_/CLK ^
   0.57
_115_/CLK ^
   0.51     -0.03       0.03

clock_skew_end
power_report

===========================================================================
 report_power
============================================================================
Group                  Internal  Switching    Leakage      Total
                          Power      Power      Power      Power (Watts)
----------------------------------------------------------------
Sequential             1.66e-04   1.21e-05   4.08e-09   1.78e-04  39.0%
Combinational          1.83e-04   9.42e-05   7.47e-07   2.78e-04  61.0%
Macro                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
----------------------------------------------------------------
Total                  3.49e-04   1.06e-04   7.51e-07   4.56e-04 100.0%
                          76.6%      23.3%       0.2%
power_report_end
area_report

===========================================================================
 report_design_area
============================================================================
Design area 67750 u^2 3% utilization.
area_report_end
Setting global connections for newly added cells...
Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/cts/cntr_example.odb...
Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/cts/cntr_example.def...
Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/cts/cntr_example.sdc...