commit	c8673eacf2a21c28d047acbf95e20be530ab849d	[log] [tgz]
author	Cocogoat <70917894+AyaseErii@users.noreply.github.com>	Sat Dec 03 16:54:55 2022 -0500
committer	GitHub <noreply@github.com>	Sat Dec 03 16:54:55 2022 -0500
tree	aa5facbdf37641640051d41477878a220d6e6a9c
parent	e3efc9924d2eed382099298261e40cec8088a96a [diff]

Add files via upload

sdc/cntr_example.sdc[Added - diff]
sdc/user_project_wrapper.sdc[Added - diff]
sdf/cntr_example.sdf[Added - diff]
sdf/multicorner/nom/user_project_wrapper.ff.sdf[Added - diff]
sdf/multicorner/nom/user_project_wrapper.ss.sdf[Added - diff]
sdf/multicorner/nom/user_project_wrapper.tt.sdf[Added - diff]
sdf/user_project_wrapper.sdf[Added - diff]
signoff/cntr_example/OPENLANE_VERSION[Added - diff]
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signoff/cntr_example/metrics.csv[Added - diff]
signoff/user_project_wrapper/OPENLANE_VERSION[diff]
signoff/user_project_wrapper/PDK_SOURCES[diff]
signoff/user_project_wrapper/metrics.csv[Added - diff]
spef/cntr_example.spef[Added - diff]
spef/multicorner/user_project_wrapper.nom.spef[Added - diff]
spef/user_project_wrapper.spef[Added - diff]
spi/lvs/cntr_example.spice[Added - diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/defines.v[Added - diff]
verilog/dv/README.md[diff]
verilog/gl/cntr_example.nl.v[Added - diff]
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verilog/gl/user_project_wrapper.nl.v[Added - diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/includes.rtl.caravel_user_project[Added - diff]
verilog/includes/includes.gl+sdf.caravel_user_project[diff]
verilog/includes/includes.gl.caravel_user_project[diff]
verilog/includes/includes.rtl.caravel_user_project[diff]
verilog/multilib.v[Added - diff]
verilog/rtl/2bit_up_counter/cntr_example.v[Added - diff]
verilog/rtl/2bit_up_counter/user_project_wrapper.v[Added - diff]
verilog/rtl/backups/cntr_example.v[Added - diff]
verilog/rtl/backups/user_project_wrapper.v[Added - diff]
verilog/rtl/cntr_example.v[Added - diff]
verilog/rtl/five_2bit_up_counter/cntr_example.v[Added - diff]
verilog/rtl/five_2bit_up_counter/user_project_wrapper.v[Added - diff]
verilog/rtl/simple_cntr/cntr_example.v[Added - diff]
verilog/rtl/simple_cntr/user_project_wrapper.v[Added - diff]
verilog/rtl/uprj_netlists.v[diff]
verilog/rtl/user_project_wrapper.v[diff]
verilog/uprj_netlists.v[Added - diff]
verilog/user_defines.v[Added - diff]
verilog/user_proj_example.v[Added - diff]
verilog/user_project_wrapper.v[Added - diff]
verilog/wrapped_multiplier.v[Added - diff]

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tree: aa5facbdf37641640051d41477878a220d6e6a9c

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quickstart of how to use caravel_user_project

Refer to README for this sample project documentation.