Rename user_proj_example
diff --git a/openlane/user_proj_example/config.tcl b/openlane/unigate/config.tcl
similarity index 94%
rename from openlane/user_proj_example/config.tcl
rename to openlane/unigate/config.tcl
index 48e913c..8a99b61 100644
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/unigate/config.tcl
@@ -16,11 +16,11 @@
set ::env(PDK) "gf180mcuC"
set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0"
-set ::env(DESIGN_NAME) user_proj_example
+set ::env(DESIGN_NAME) unigate
set ::env(VERILOG_FILES) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $::env(DESIGN_DIR)/../../verilog/rtl/user_proj_example.v"
+ $::env(DESIGN_DIR)/../../verilog/rtl/unigate.v"
set ::env(DESIGN_IS_CORE) 0
@@ -53,4 +53,4 @@
set ::env(DIODE_INSERTION_STRATEGY) 4
# If you're going to use multiple power domains, then disable cvc run.
-set ::env(RUN_CVC) 1
\ No newline at end of file
+set ::env(RUN_CVC) 1
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/unigate/pin_order.cfg
similarity index 100%
rename from openlane/user_proj_example/pin_order.cfg
rename to openlane/unigate/pin_order.cfg
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index df19160..835e7dc 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -49,13 +49,13 @@
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $::env(DESIGN_DIR)/../../verilog/rtl/user_proj_example.v"
+ $::env(DESIGN_DIR)/../../verilog/rtl/unigate.v"
set ::env(EXTRA_LEFS) "\
- $::env(DESIGN_DIR)/../../lef/user_proj_example.lef"
+ $::env(DESIGN_DIR)/../../lef/unigate.lef"
set ::env(EXTRA_GDS_FILES) "\
- $::env(DESIGN_DIR)/../../gds/user_proj_example.gds"
+ $::env(DESIGN_DIR)/../../gds/unigate.gds"
set ::env(RT_MAX_LAYER) {Metal4}
@@ -80,4 +80,4 @@
set ::env(CLOCK_TREE_SYNTH) 0
# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS
-source $::env(DESIGN_DIR)/fixed_dont_change/fixed_wrapper_cfgs.tcl
\ No newline at end of file
+source $::env(DESIGN_DIR)/fixed_dont_change/fixed_wrapper_cfgs.tcl
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/unigate.v
similarity index 98%
rename from verilog/rtl/user_proj_example.v
rename to verilog/rtl/unigate.v
index 78cd884..687827c 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/unigate.v
@@ -17,7 +17,7 @@
/*
*-------------------------------------------------------------
*
- * user_proj_example
+ * unigate
*
* This is an example of a (trivially simple) user project,
* showing how the user project can connect to the logic
@@ -35,7 +35,7 @@
*-------------------------------------------------------------
*/
-module user_proj_example #(
+module unigate #(
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3537de8..00436c1 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -21,8 +21,8 @@
// Assume default net type to be wire because GL netlists don't have the wire definitions
`default_nettype wire
`include "gl/user_project_wrapper.v"
- `include "gl/user_proj_example.v"
+ `include "gl/unigate.v"
`else
`include "user_project_wrapper.v"
- `include "user_proj_example.v"
-`endif
\ No newline at end of file
+ `include "unigate.v"
+`endif
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 146877d..32e3ef8 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -70,7 +70,7 @@
/* User project is instantiated here */
/*--------------------------------------*/
-user_proj_example mprj (
+unigate mprj (
`ifdef USE_POWER_PINS
.vdd(vdd), // User area 1 1.8V power
.vss(vss), // User area 1 digital ground
