Add verilog sources
16 files changed
tree: 874a6677bb6afba963357f3497ae4f9d52b6dc0a
  1. .github/
  2. docs/
  3. openlane/
  4. verilog/
  5. .gitignore
  6. LICENSE
  7. Makefile
  8. README.md
README.md

Caravel User Project

License UPRJ_CI Caravel Build

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.