commit	6ba59c40e10388d3b16b40925be6d16e0a09ad31	[log] [tgz]
author	Guohua <yghlovelyf0616@gmail.com>	Tue Dec 06 01:40:14 2022 +0800
committer	Guohua <yghlovelyf0616@gmail.com>	Tue Dec 06 01:40:14 2022 +0800
tree	86e1e0b0d46b608755723b8a4dc874d18e8575fb
parent	31981ed486e7890db5e59bd366fe790c6760e10b [diff]

lalala

def/user_project_wrapper.def[Deleted - diff]
def/user_project_wrapper.def.gz[Added - diff]
docs/source/index.rst[diff]
gds/user_proj_example.gds[Deleted - diff]
gds/user_project_wrapper.gds[Deleted - diff]
gds/user_project_wrapper.gds.gz[Added - diff]
lef/user_proj_example.lef[Deleted - diff]
lef/user_project_wrapper.lef[Deleted - diff]
lef/user_project_wrapper.lef.gz[Added - diff]
lib/user_project_wrapper.lib.gz[Added - diff]
mag/user_proj_example.mag[Deleted - diff]
mag/user_project_wrapper.mag[Deleted - diff]
mag/user_project_wrapper.mag.gz[Added - diff]
maglef/user_proj_example.mag[Deleted - diff]
maglef/user_project_wrapper.mag[Deleted - diff]
maglef/user_project_wrapper.mag.gz[Added - diff]
openlane/user_proj_example/config.json[Deleted - diff]
openlane/user_proj_example/pin_order.cfg[Deleted - diff]
openlane/user_project_wrapper/config.json[diff]
openlane/user_project_wrapper/macro.cfg[Deleted - diff]
sdc/user_project_wrapper.sdc[Added - diff]
sdf/multicorner/nom/user_project_wrapper.ff.sdf.gz[Added - diff]
sdf/multicorner/nom/user_project_wrapper.ss.sdf.gz[Added - diff]
sdf/multicorner/nom/user_project_wrapper.tt.sdf.gz[Added - diff]
sdf/user_project_wrapper.sdf.gz[Added - diff]
signoff/user_proj_example/OPENLANE_VERSION[Deleted - diff]
signoff/user_proj_example/PDK_SOURCES[Deleted - diff]
signoff/user_project_wrapper/OPENLANE_VERSION[diff]
signoff/user_project_wrapper/PDK_SOURCES[diff]
signoff/user_project_wrapper/metrics.csv[Added - diff]
spef/multicorner/user_project_wrapper.nom.spef.gz[Added - diff]
spef/user_project_wrapper.spef.gz[Added - diff]
spi/lvs/user_proj_example.spice[Deleted - diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/base.sdc[Added - diff]
verilog/dv/wb_port/wb_port.c[diff]
verilog/gl/user_proj_example.v[Deleted - diff]
verilog/gl/user_project_wrapper.nl.v[Added - diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/includes/includes.rtl.caravel_user_project[diff]
verilog/rtl/user_defines.v[diff]
verilog/rtl/user_project_wrapper.v[diff]
verilog/rtl_sram_out_cache/bus_arbiter.v[Added - diff]
verilog/rtl_sram_out_cache/caravel/defines.v[Added - diff]
verilog/rtl_sram_out_cache/caravel_defines.v[Added - diff]
verilog/rtl_sram_out_cache/data_ram_mux.v[Added - diff]
verilog/rtl_sram_out_cache/gpio.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/base.sdc[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/cache/cacheblock/sky130_sram_1kbyte_1rw1r_32x256_8.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/cache/cacheblock/std_dffe.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/cache/cacheblock/std_dffr.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/cache/l1dcache.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/cache/l1icache_32.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/cache/params.vh[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/core_empty.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/ac.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/agu.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/cu.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/lr.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/lsq.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/nblsu.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/params.vh[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/mmu/leaf_pte_check.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/mmu/mmu_sv39.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/mmu/ptw.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/params.vh[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/pipeline/backend.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/pipeline/frontend.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/btb.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter_rob.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter_tmp.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/csr.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/decode.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/excep_ctrl.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fake_icache.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fetch.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fifo.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fifo_tmp.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/gshare.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/ins_buffer.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/new_alu.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/new_fu.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/physical_regfile.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/core_empty/units/rcu.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/macros/gds/sky130_sram_1rw1r_64x256_8.gds[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/macros/lef/sky130_sram_1rw1r_64x256_8.lef[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/macros/verilog/sky130_sram_1rw1r_64x256_8.v[Added - diff]
verilog/rtl_sram_out_cache/hehe/src/params.vh[Added - diff]
verilog/rtl_sram_out_cache/inc/rvj1_defines.v[Added - diff]
verilog/rtl_sram_out_cache/instr_ram_mux.v[Added - diff]
verilog/rtl_sram_out_cache/latch_map.v[Added - diff]
verilog/rtl_sram_out_cache/params.vh[Added - diff]
verilog/rtl_sram_out_cache/rvj1_caravel_soc.v[Added - diff]
verilog/rtl_sram_out_cache/timer.v[Added - diff]
verilog/rtl_sram_out_cache/to.v[Added - diff]
verilog/rtl_sram_out_cache/top.v[Added - diff]
verilog/rtl_sram_out_cache/user_project_wrapper.v[Added - diff]
verilog/rtl_sram_out_cache/wishbone_mux.v[Added - diff]

102 files changed

tree: 86e1e0b0d46b608755723b8a4dc874d18e8575fb

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quickstart of how to use caravel_user_project

Refer to README for this sample project documentation.