)]}'
{
  "commit": "fb9cbd2095794f85b4030f4694e54f2b33b74f18",
  "tree": "4b31a449c86be2f9a3b82785d275783580c3bbdc",
  "parents": [
    "71086aa5b20841f9a1dd9c419e31a017e308d4ca"
  ],
  "author": {
    "name": "filippocarastro",
    "email": "filippo.carastro@icloud.com",
    "time": "Wed Nov 30 20:46:10 2022 +0100"
  },
  "committer": {
    "name": "filippocarastro",
    "email": "filippo.carastro@icloud.com",
    "time": "Wed Nov 30 20:46:10 2022 +0100"
  },
  "message": "add verilog files\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "2e89d44e1818db99c5b3a599b2e3bf095ded3530",
      "new_mode": 33188,
      "new_path": "verilog/rtl/MPPT/rtl/dpwm.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "b344e0ffa22df3d24a22240ce4203f26d3aead64",
      "new_mode": 33188,
      "new_path": "verilog/rtl/MPPT/rtl/mppt.v"
    }
  ]
}