commit	6aebd52ec9b06ad6a126ff91cb32e9d2cbf131ce	[log] [tgz]
author	Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>	Mon Nov 21 08:26:21 2022 -0800
committer	Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>	Mon Nov 21 08:26:21 2022 -0800
tree	1b877acc2270e821148e6905600eca416818daa0
parent	741335cb7fa9005e57c76982b87bb3fdcaaa0c27 [diff]

First itterations that:
- Changed config.json back to config.tcl
- Incorprated the new changes done in caravel configuration
- New template def file
- Default configuration is specific for gf180mcuC
- Fixed user_project_wrapper and example rtl verilog to be the same as
the on in caravel
TODO:
- reharden user_project_wrapper in caravel with new OpenLane as the via
insertion is different and will cause an issue with XOR
- Make the repo usable for multiple technologies

Makefile[diff]
def/user_proj_example.def[diff]
def/user_project_wrapper.def[diff]
gds/user_proj_example.gds[diff]
gds/user_project_wrapper.gds[diff]
lef/user_proj_example.lef[diff]
lef/user_project_wrapper.lef[diff]
lib/user_proj_example.lib[Added - diff]
lib/user_project_wrapper.lib[Added - diff]
mag/user_proj_example.mag[diff]
mag/user_project_wrapper.mag[diff]
maglef/user_proj_example.mag[diff]
maglef/user_project_wrapper.mag[diff]
openlane/Makefile[diff]
openlane/user_proj_example/config.json[Deleted - diff]
openlane/user_proj_example/config.tcl[Added - diff]
openlane/user_project_wrapper/config.json[Deleted - diff]
openlane/user_project_wrapper/config.tcl[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl[diff]
openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl[diff]
openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper_gf180mcu.def[diff]
sdc/user_proj_example.sdc[Added - diff]
sdc/user_project_wrapper.sdc[Added - diff]
sdf/multicorner/nom/user_project_wrapper.ff.sdf[Added - diff]
sdf/multicorner/nom/user_project_wrapper.ss.sdf[Added - diff]
sdf/multicorner/nom/user_project_wrapper.tt.sdf[Added - diff]
sdf/user_proj_example.sdf[Added - diff]
sdf/user_project_wrapper.sdf[Added - diff]
signoff/user_proj_example/OPENLANE_VERSION[diff]
signoff/user_proj_example/PDK_SOURCES[diff]
signoff/user_proj_example/metrics.csv[Added - diff]
signoff/user_project_wrapper/OPENLANE_VERSION[diff]
signoff/user_project_wrapper/PDK_SOURCES[diff]
signoff/user_project_wrapper/metrics.csv[Added - diff]
spef/multicorner/user_project_wrapper.nom.spef[Added - diff]
spef/user_proj_example.spef[Added - diff]
spef/user_project_wrapper.spef[Added - diff]
spi/lvs/user_proj_example.spice[diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/dv/Makefile[Deleted - diff]
verilog/dv/README.md[Deleted - diff]
verilog/dv/io_ports/Makefile[Deleted - diff]
verilog/dv/io_ports/io_ports.c[Deleted - diff]
verilog/dv/io_ports/io_ports_tb.v[Deleted - diff]
verilog/dv/la_test1/Makefile[Deleted - diff]
verilog/dv/la_test1/la_test1.c[Deleted - diff]
verilog/dv/la_test1/la_test1_tb.v[Deleted - diff]
verilog/dv/la_test2/Makefile[Deleted - diff]
verilog/dv/la_test2/la_test2.c[Deleted - diff]
verilog/dv/la_test2/la_test2_tb.v[Deleted - diff]
verilog/dv/local-install.md[Deleted - diff]
verilog/dv/mprj_stimulus/Makefile[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Deleted - diff]
verilog/dv/wb_port/Makefile[Deleted - diff]
verilog/dv/wb_port/wb_port.c[Deleted - diff]
verilog/dv/wb_port/wb_port_tb.v[Deleted - diff]
verilog/gl/user_proj_example.v[diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/rtl/user_proj_example.v[diff]
verilog/rtl/user_project_wrapper.v[diff]

61 files changed

tree: 1b877acc2270e821148e6905600eca416818daa0

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quickstart of how to use caravel_user_project

Refer to README for this sample project documentation.