upload fake design files
diff --git a/Makefile b/Makefile
index 3b25487..5917171 100644
--- a/Makefile
+++ b/Makefile
@@ -23,6 +23,9 @@
# Install lite version of caravel, (1): caravel-lite, (0): caravel
CARAVEL_LITE?=1
+export OPENLANE_ROOT=$(PWD)/dependencies/openlane_src
+export PDK_ROOT=$(PWD)/dependencies/pdks
+
# PDK switch varient
export PDK?=gf180mcuC
#export PDK?=gf180mcuC
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 48e913c..bc4376f 100644
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -16,17 +16,19 @@
set ::env(PDK) "gf180mcuC"
set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0"
-set ::env(DESIGN_NAME) user_proj_example
+set ::env(DESIGN_NAME) rift2Wrap
set ::env(VERILOG_FILES) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $::env(DESIGN_DIR)/../../verilog/rtl/user_proj_example.v"
+ $::env(DESIGN_DIR)/../../verilog/rtl/Sky130BLFSR.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/rift2Fake.v \
+ "
set ::env(DESIGN_IS_CORE) 0
set ::env(CLOCK_PORT) "wb_clk_i"
-set ::env(CLOCK_NET) "counter.clk"
-set ::env(CLOCK_PERIOD) "24.0"
+set ::env(CLOCK_NET) "i_fake.clock"
+set ::env(CLOCK_PERIOD) "20.0"
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 900 600"
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/user_proj_example/pin_order.cfg
index 2fda806..c671b89 100644
--- a/openlane/user_proj_example/pin_order.cfg
+++ b/openlane/user_proj_example/pin_order.cfg
@@ -1,10 +1,127 @@
#BUS_SORT
+#NR
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
#S
wb_.*
wbs_.*
la_.*
-irq.*
+user_clock2
+user_irq.*
-#N
-io_.*
+#E
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+
+#WR
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index df19160..8ed2f4e 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -33,15 +33,15 @@
$::env(DESIGN_DIR)/../../verilog/rtl/user_project_wrapper.v"
## Clock configurations
-set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_NET) "i_rift2Wrap.wb_clk_i"
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PERIOD) "20"
## Internal Macros
### Macro PDN Connections
set ::env(FP_PDN_MACRO_HOOKS) "\
- mprj vdd vss vdd vss"
+ i_rift2Wrap vdd vss vdd vss"
### Macro Placement
set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
@@ -49,13 +49,13 @@
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $::env(DESIGN_DIR)/../../verilog/rtl/user_proj_example.v"
+ $::env(DESIGN_DIR)/../../verilog/rtl/rift2Fake.v"
set ::env(EXTRA_LEFS) "\
- $::env(DESIGN_DIR)/../../lef/user_proj_example.lef"
+ $::env(DESIGN_DIR)/../../lef/rift2Wrap.lef"
set ::env(EXTRA_GDS_FILES) "\
- $::env(DESIGN_DIR)/../../gds/user_proj_example.gds"
+ $::env(DESIGN_DIR)/../../gds/rift2Wrap.gds"
set ::env(RT_MAX_LAYER) {Metal4}
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..351b08e 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1 @@
-mprj 1175 1690 N
+i_rift2Wrap 1175 1690 N
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg
index c9632da..c671b89 100644
--- a/openlane/user_project_wrapper/pin_order.cfg
+++ b/openlane/user_project_wrapper/pin_order.cfg
@@ -1,38 +1,29 @@
#BUS_SORT
#NR
-analog_io\[8\]
io_in\[15\]
io_out\[15\]
io_oeb\[15\]
-analog_io\[9\]
io_in\[16\]
io_out\[16\]
io_oeb\[16\]
-analog_io\[10\]
io_in\[17\]
io_out\[17\]
io_oeb\[17\]
-analog_io\[11\]
io_in\[18\]
io_out\[18\]
io_oeb\[18\]
-analog_io\[12\]
io_in\[19\]
io_out\[19\]
io_oeb\[19\]
-analog_io\[13\]
io_in\[20\]
io_out\[20\]
io_oeb\[20\]
-analog_io\[14\]
io_in\[21\]
io_out\[21\]
io_oeb\[21\]
-analog_io\[15\]
io_in\[22\]
io_out\[22\]
io_oeb\[22\]
-analog_io\[16\]
io_in\[23\]
io_out\[23\]
io_oeb\[23\]
@@ -66,85 +57,65 @@
io_in\[6\]
io_out\[6\]
io_oeb\[6\]
-analog_io\[0\]
io_in\[7\]
io_out\[7\]
io_oeb\[7\]
-analog_io\[1\]
io_in\[8\]
io_out\[8\]
io_oeb\[8\]
-analog_io\[2\]
io_in\[9\]
io_out\[9\]
io_oeb\[9\]
-analog_io\[3\]
io_in\[10\]
io_out\[10\]
io_oeb\[10\]
-analog_io\[4\]
io_in\[11\]
io_out\[11\]
io_oeb\[11\]
-analog_io\[5\]
io_in\[12\]
io_out\[12\]
io_oeb\[12\]
-analog_io\[6\]
io_in\[13\]
io_out\[13\]
io_oeb\[13\]
-analog_io\[7\]
io_in\[14\]
io_out\[14\]
io_oeb\[14\]
#WR
-analog_io\[17\]
io_in\[24\]
io_out\[24\]
io_oeb\[24\]
-analog_io\[18\]
io_in\[25\]
io_out\[25\]
io_oeb\[25\]
-analog_io\[19\]
io_in\[26\]
io_out\[26\]
io_oeb\[26\]
-analog_io\[20\]
io_in\[27\]
io_out\[27\]
io_oeb\[27\]
-analog_io\[21\]
io_in\[28\]
io_out\[28\]
io_oeb\[28\]
-analog_io\[22\]
io_in\[29\]
io_out\[29\]
io_oeb\[29\]
-analog_io\[23\]
io_in\[30\]
io_out\[30\]
io_oeb\[30\]
-analog_io\[24\]
io_in\[31\]
io_out\[31\]
io_oeb\[31\]
-analog_io\[25\]
io_in\[32\]
io_out\[32\]
io_oeb\[32\]
-analog_io\[26\]
io_in\[33\]
io_out\[33\]
io_oeb\[33\]
-analog_io\[27\]
io_in\[34\]
io_out\[34\]
io_oeb\[34\]
-analog_io\[28\]
io_in\[35\]
io_out\[35\]
io_oeb\[35\]
diff --git a/verilog/rtl/Sky130BLFSR.v b/verilog/rtl/Sky130BLFSR.v
new file mode 100644
index 0000000..488834f
--- /dev/null
+++ b/verilog/rtl/Sky130BLFSR.v
@@ -0,0 +1,519 @@
+// SPDX-FileCopyrightText: 2022 Wuhan University of Technology
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+module MaxPeriodFibonacciLFSR(
+ input clock,
+ input reset,
+ input io_increment,
+ output io_out_0,
+ output io_out_1,
+ output io_out_2,
+ output io_out_3,
+ output io_out_4,
+ output io_out_5,
+ output io_out_6,
+ output io_out_7,
+ output io_out_8,
+ output io_out_9,
+ output io_out_10,
+ output io_out_11,
+ output io_out_12,
+ output io_out_13,
+ output io_out_14,
+ output io_out_15
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+`endif // RANDOMIZE_REG_INIT
+ reg state_0; // @[PRNG.scala 55:49]
+ reg state_1; // @[PRNG.scala 55:49]
+ reg state_2; // @[PRNG.scala 55:49]
+ reg state_3; // @[PRNG.scala 55:49]
+ reg state_4; // @[PRNG.scala 55:49]
+ reg state_5; // @[PRNG.scala 55:49]
+ reg state_6; // @[PRNG.scala 55:49]
+ reg state_7; // @[PRNG.scala 55:49]
+ reg state_8; // @[PRNG.scala 55:49]
+ reg state_9; // @[PRNG.scala 55:49]
+ reg state_10; // @[PRNG.scala 55:49]
+ reg state_11; // @[PRNG.scala 55:49]
+ reg state_12; // @[PRNG.scala 55:49]
+ reg state_13; // @[PRNG.scala 55:49]
+ reg state_14; // @[PRNG.scala 55:49]
+ reg state_15; // @[PRNG.scala 55:49]
+ wire _T_2 = state_15 ^ state_13 ^ state_12 ^ state_10; // @[LFSR.scala 15:41]
+ wire _GEN_0 = io_increment ? _T_2 : state_0; // @[PRNG.scala 69:22 70:11 55:49]
+ assign io_out_0 = state_0; // @[PRNG.scala 78:10]
+ assign io_out_1 = state_1; // @[PRNG.scala 78:10]
+ assign io_out_2 = state_2; // @[PRNG.scala 78:10]
+ assign io_out_3 = state_3; // @[PRNG.scala 78:10]
+ assign io_out_4 = state_4; // @[PRNG.scala 78:10]
+ assign io_out_5 = state_5; // @[PRNG.scala 78:10]
+ assign io_out_6 = state_6; // @[PRNG.scala 78:10]
+ assign io_out_7 = state_7; // @[PRNG.scala 78:10]
+ assign io_out_8 = state_8; // @[PRNG.scala 78:10]
+ assign io_out_9 = state_9; // @[PRNG.scala 78:10]
+ assign io_out_10 = state_10; // @[PRNG.scala 78:10]
+ assign io_out_11 = state_11; // @[PRNG.scala 78:10]
+ assign io_out_12 = state_12; // @[PRNG.scala 78:10]
+ assign io_out_13 = state_13; // @[PRNG.scala 78:10]
+ assign io_out_14 = state_14; // @[PRNG.scala 78:10]
+ assign io_out_15 = state_15; // @[PRNG.scala 78:10]
+ always @(posedge clock) begin
+ state_0 <= reset | _GEN_0; // @[PRNG.scala 55:{49,49}]
+ if (reset) begin // @[PRNG.scala 55:49]
+ state_1 <= 1'h0; // @[PRNG.scala 55:49]
+ end else if (io_increment) begin // @[PRNG.scala 69:22]
+ state_1 <= state_0; // @[PRNG.scala 70:11]
+ end
+ if (reset) begin // @[PRNG.scala 55:49]
+ state_2 <= 1'h0; // @[PRNG.scala 55:49]
+ end else if (io_increment) begin // @[PRNG.scala 69:22]
+ state_2 <= state_1; // @[PRNG.scala 70:11]
+ end
+ if (reset) begin // @[PRNG.scala 55:49]
+ state_3 <= 1'h0; // @[PRNG.scala 55:49]
+ end else if (io_increment) begin // @[PRNG.scala 69:22]
+ state_3 <= state_2; // @[PRNG.scala 70:11]
+ end
+ if (reset) begin // @[PRNG.scala 55:49]
+ state_4 <= 1'h0; // @[PRNG.scala 55:49]
+ end else if (io_increment) begin // @[PRNG.scala 69:22]
+ state_4 <= state_3; // @[PRNG.scala 70:11]
+ end
+ if (reset) begin // @[PRNG.scala 55:49]
+ state_5 <= 1'h0; // @[PRNG.scala 55:49]
+ end else if (io_increment) begin // @[PRNG.scala 69:22]
+ state_5 <= state_4; // @[PRNG.scala 70:11]
+ end
+ if (reset) begin // @[PRNG.scala 55:49]
+ state_6 <= 1'h0; // @[PRNG.scala 55:49]
+ end else if (io_increment) begin // @[PRNG.scala 69:22]
+ state_6 <= state_5; // @[PRNG.scala 70:11]
+ end
+ if (reset) begin // @[PRNG.scala 55:49]
+ state_7 <= 1'h0; // @[PRNG.scala 55:49]
+ end else if (io_increment) begin // @[PRNG.scala 69:22]
+ state_7 <= state_6; // @[PRNG.scala 70:11]
+ end
+ if (reset) begin // @[PRNG.scala 55:49]
+ state_8 <= 1'h0; // @[PRNG.scala 55:49]
+ end else if (io_increment) begin // @[PRNG.scala 69:22]
+ state_8 <= state_7; // @[PRNG.scala 70:11]
+ end
+ if (reset) begin // @[PRNG.scala 55:49]
+ state_9 <= 1'h0; // @[PRNG.scala 55:49]
+ end else if (io_increment) begin // @[PRNG.scala 69:22]
+ state_9 <= state_8; // @[PRNG.scala 70:11]
+ end
+ if (reset) begin // @[PRNG.scala 55:49]
+ state_10 <= 1'h0; // @[PRNG.scala 55:49]
+ end else if (io_increment) begin // @[PRNG.scala 69:22]
+ state_10 <= state_9; // @[PRNG.scala 70:11]
+ end
+ if (reset) begin // @[PRNG.scala 55:49]
+ state_11 <= 1'h0; // @[PRNG.scala 55:49]
+ end else if (io_increment) begin // @[PRNG.scala 69:22]
+ state_11 <= state_10; // @[PRNG.scala 70:11]
+ end
+ if (reset) begin // @[PRNG.scala 55:49]
+ state_12 <= 1'h0; // @[PRNG.scala 55:49]
+ end else if (io_increment) begin // @[PRNG.scala 69:22]
+ state_12 <= state_11; // @[PRNG.scala 70:11]
+ end
+ if (reset) begin // @[PRNG.scala 55:49]
+ state_13 <= 1'h0; // @[PRNG.scala 55:49]
+ end else if (io_increment) begin // @[PRNG.scala 69:22]
+ state_13 <= state_12; // @[PRNG.scala 70:11]
+ end
+ if (reset) begin // @[PRNG.scala 55:49]
+ state_14 <= 1'h0; // @[PRNG.scala 55:49]
+ end else if (io_increment) begin // @[PRNG.scala 69:22]
+ state_14 <= state_13; // @[PRNG.scala 70:11]
+ end
+ if (reset) begin // @[PRNG.scala 55:49]
+ state_15 <= 1'h0; // @[PRNG.scala 55:49]
+ end else if (io_increment) begin // @[PRNG.scala 69:22]
+ state_15 <= state_14; // @[PRNG.scala 70:11]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ state_0 = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ state_1 = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ state_2 = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ state_3 = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ state_4 = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ state_5 = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ state_6 = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ state_7 = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ state_8 = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ state_9 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ state_10 = _RAND_10[0:0];
+ _RAND_11 = {1{`RANDOM}};
+ state_11 = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ state_12 = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ state_13 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ state_14 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ state_15 = _RAND_15[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Sky130BLFSR(
+ input clock,
+ input reset,
+ output [6:0] io_num_0,
+ output [6:0] io_num_1,
+ output [6:0] io_num_2,
+ output [6:0] io_num_3,
+ input io_lock
+);
+ wire lfsr_prng_clock; // @[PRNG.scala 91:22]
+ wire lfsr_prng_reset; // @[PRNG.scala 91:22]
+ wire lfsr_prng_io_increment; // @[PRNG.scala 91:22]
+ wire lfsr_prng_io_out_0; // @[PRNG.scala 91:22]
+ wire lfsr_prng_io_out_1; // @[PRNG.scala 91:22]
+ wire lfsr_prng_io_out_2; // @[PRNG.scala 91:22]
+ wire lfsr_prng_io_out_3; // @[PRNG.scala 91:22]
+ wire lfsr_prng_io_out_4; // @[PRNG.scala 91:22]
+ wire lfsr_prng_io_out_5; // @[PRNG.scala 91:22]
+ wire lfsr_prng_io_out_6; // @[PRNG.scala 91:22]
+ wire lfsr_prng_io_out_7; // @[PRNG.scala 91:22]
+ wire lfsr_prng_io_out_8; // @[PRNG.scala 91:22]
+ wire lfsr_prng_io_out_9; // @[PRNG.scala 91:22]
+ wire lfsr_prng_io_out_10; // @[PRNG.scala 91:22]
+ wire lfsr_prng_io_out_11; // @[PRNG.scala 91:22]
+ wire lfsr_prng_io_out_12; // @[PRNG.scala 91:22]
+ wire lfsr_prng_io_out_13; // @[PRNG.scala 91:22]
+ wire lfsr_prng_io_out_14; // @[PRNG.scala 91:22]
+ wire lfsr_prng_io_out_15; // @[PRNG.scala 91:22]
+ wire [7:0] lfsr_lo = {lfsr_prng_io_out_7,lfsr_prng_io_out_6,lfsr_prng_io_out_5,lfsr_prng_io_out_4,lfsr_prng_io_out_3,
+ lfsr_prng_io_out_2,lfsr_prng_io_out_1,lfsr_prng_io_out_0}; // @[PRNG.scala 95:17]
+ wire [15:0] lfsr = {lfsr_prng_io_out_15,lfsr_prng_io_out_14,lfsr_prng_io_out_13,lfsr_prng_io_out_12,
+ lfsr_prng_io_out_11,lfsr_prng_io_out_10,lfsr_prng_io_out_9,lfsr_prng_io_out_8,lfsr_lo}; // @[PRNG.scala 95:17]
+ wire _io_num_0_T_1 = lfsr[3:0] == 4'h0; // @[Sky130BLFSR.scala 56:27]
+ wire _io_num_0_T_3 = lfsr[3:0] == 4'h1; // @[Sky130BLFSR.scala 57:27]
+ wire _io_num_0_T_5 = lfsr[3:0] == 4'h2; // @[Sky130BLFSR.scala 58:27]
+ wire _io_num_0_T_7 = lfsr[3:0] == 4'h3; // @[Sky130BLFSR.scala 59:27]
+ wire _io_num_0_T_9 = lfsr[3:0] == 4'h4; // @[Sky130BLFSR.scala 60:27]
+ wire _io_num_0_T_11 = lfsr[3:0] == 4'h5; // @[Sky130BLFSR.scala 61:27]
+ wire _io_num_0_T_13 = lfsr[3:0] == 4'h6; // @[Sky130BLFSR.scala 62:27]
+ wire _io_num_0_T_15 = lfsr[3:0] == 4'h7; // @[Sky130BLFSR.scala 63:27]
+ wire _io_num_0_T_19 = lfsr[3:0] == 4'h9; // @[Sky130BLFSR.scala 65:27]
+ wire _io_num_0_T_21 = lfsr[3:0] == 4'ha; // @[Sky130BLFSR.scala 66:27]
+ wire _io_num_0_T_23 = lfsr[3:0] == 4'hb; // @[Sky130BLFSR.scala 67:27]
+ wire _io_num_0_T_25 = lfsr[3:0] == 4'hc; // @[Sky130BLFSR.scala 68:27]
+ wire _io_num_0_T_27 = lfsr[3:0] == 4'hd; // @[Sky130BLFSR.scala 69:27]
+ wire _io_num_0_T_29 = lfsr[3:0] == 4'he; // @[Sky130BLFSR.scala 70:27]
+ wire _io_num_0_T_31 = lfsr[3:0] == 4'hf; // @[Sky130BLFSR.scala 71:27]
+ wire [6:0] _io_num_0_T_32 = _io_num_0_T_1 ? 7'h40 : 7'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_0_T_33 = _io_num_0_T_3 ? 7'h79 : 7'h0; // @[Mux.scala 27:73]
+ wire [5:0] _io_num_0_T_34 = _io_num_0_T_5 ? 6'h24 : 6'h0; // @[Mux.scala 27:73]
+ wire [5:0] _io_num_0_T_35 = _io_num_0_T_7 ? 6'h30 : 6'h0; // @[Mux.scala 27:73]
+ wire [4:0] _io_num_0_T_36 = _io_num_0_T_9 ? 5'h19 : 5'h0; // @[Mux.scala 27:73]
+ wire [4:0] _io_num_0_T_37 = _io_num_0_T_11 ? 5'h12 : 5'h0; // @[Mux.scala 27:73]
+ wire [1:0] _io_num_0_T_38 = _io_num_0_T_13 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_0_T_39 = _io_num_0_T_15 ? 7'h78 : 7'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_0_T_41 = _io_num_0_T_19 ? 7'h6f : 7'h0; // @[Mux.scala 27:73]
+ wire [3:0] _io_num_0_T_42 = _io_num_0_T_21 ? 4'h8 : 4'h0; // @[Mux.scala 27:73]
+ wire [1:0] _io_num_0_T_43 = _io_num_0_T_23 ? 2'h3 : 2'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_0_T_44 = _io_num_0_T_25 ? 7'h46 : 7'h0; // @[Mux.scala 27:73]
+ wire [5:0] _io_num_0_T_45 = _io_num_0_T_27 ? 6'h21 : 6'h0; // @[Mux.scala 27:73]
+ wire [2:0] _io_num_0_T_46 = _io_num_0_T_29 ? 3'h6 : 3'h0; // @[Mux.scala 27:73]
+ wire [3:0] _io_num_0_T_47 = _io_num_0_T_31 ? 4'he : 4'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_0_T_48 = _io_num_0_T_32 | _io_num_0_T_33; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_4 = {{1'd0}, _io_num_0_T_34}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_0_T_49 = _io_num_0_T_48 | _GEN_4; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_5 = {{1'd0}, _io_num_0_T_35}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_0_T_50 = _io_num_0_T_49 | _GEN_5; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_6 = {{2'd0}, _io_num_0_T_36}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_0_T_51 = _io_num_0_T_50 | _GEN_6; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_7 = {{2'd0}, _io_num_0_T_37}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_0_T_52 = _io_num_0_T_51 | _GEN_7; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_8 = {{5'd0}, _io_num_0_T_38}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_0_T_53 = _io_num_0_T_52 | _GEN_8; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_0_T_54 = _io_num_0_T_53 | _io_num_0_T_39; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_0_T_56 = _io_num_0_T_54 | _io_num_0_T_41; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_9 = {{3'd0}, _io_num_0_T_42}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_0_T_57 = _io_num_0_T_56 | _GEN_9; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_10 = {{5'd0}, _io_num_0_T_43}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_0_T_58 = _io_num_0_T_57 | _GEN_10; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_0_T_59 = _io_num_0_T_58 | _io_num_0_T_44; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_11 = {{1'd0}, _io_num_0_T_45}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_0_T_60 = _io_num_0_T_59 | _GEN_11; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_12 = {{4'd0}, _io_num_0_T_46}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_0_T_61 = _io_num_0_T_60 | _GEN_12; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_13 = {{3'd0}, _io_num_0_T_47}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_0_T_62 = _io_num_0_T_61 | _GEN_13; // @[Mux.scala 27:73]
+ wire _io_num_1_T_1 = lfsr[7:4] == 4'h0; // @[Sky130BLFSR.scala 56:27]
+ wire _io_num_1_T_3 = lfsr[7:4] == 4'h1; // @[Sky130BLFSR.scala 57:27]
+ wire _io_num_1_T_5 = lfsr[7:4] == 4'h2; // @[Sky130BLFSR.scala 58:27]
+ wire _io_num_1_T_7 = lfsr[7:4] == 4'h3; // @[Sky130BLFSR.scala 59:27]
+ wire _io_num_1_T_9 = lfsr[7:4] == 4'h4; // @[Sky130BLFSR.scala 60:27]
+ wire _io_num_1_T_11 = lfsr[7:4] == 4'h5; // @[Sky130BLFSR.scala 61:27]
+ wire _io_num_1_T_13 = lfsr[7:4] == 4'h6; // @[Sky130BLFSR.scala 62:27]
+ wire _io_num_1_T_15 = lfsr[7:4] == 4'h7; // @[Sky130BLFSR.scala 63:27]
+ wire _io_num_1_T_19 = lfsr[7:4] == 4'h9; // @[Sky130BLFSR.scala 65:27]
+ wire _io_num_1_T_21 = lfsr[7:4] == 4'ha; // @[Sky130BLFSR.scala 66:27]
+ wire _io_num_1_T_23 = lfsr[7:4] == 4'hb; // @[Sky130BLFSR.scala 67:27]
+ wire _io_num_1_T_25 = lfsr[7:4] == 4'hc; // @[Sky130BLFSR.scala 68:27]
+ wire _io_num_1_T_27 = lfsr[7:4] == 4'hd; // @[Sky130BLFSR.scala 69:27]
+ wire _io_num_1_T_29 = lfsr[7:4] == 4'he; // @[Sky130BLFSR.scala 70:27]
+ wire _io_num_1_T_31 = lfsr[7:4] == 4'hf; // @[Sky130BLFSR.scala 71:27]
+ wire [6:0] _io_num_1_T_32 = _io_num_1_T_1 ? 7'h40 : 7'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_1_T_33 = _io_num_1_T_3 ? 7'h79 : 7'h0; // @[Mux.scala 27:73]
+ wire [5:0] _io_num_1_T_34 = _io_num_1_T_5 ? 6'h24 : 6'h0; // @[Mux.scala 27:73]
+ wire [5:0] _io_num_1_T_35 = _io_num_1_T_7 ? 6'h30 : 6'h0; // @[Mux.scala 27:73]
+ wire [4:0] _io_num_1_T_36 = _io_num_1_T_9 ? 5'h19 : 5'h0; // @[Mux.scala 27:73]
+ wire [4:0] _io_num_1_T_37 = _io_num_1_T_11 ? 5'h12 : 5'h0; // @[Mux.scala 27:73]
+ wire [1:0] _io_num_1_T_38 = _io_num_1_T_13 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_1_T_39 = _io_num_1_T_15 ? 7'h78 : 7'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_1_T_41 = _io_num_1_T_19 ? 7'h6f : 7'h0; // @[Mux.scala 27:73]
+ wire [3:0] _io_num_1_T_42 = _io_num_1_T_21 ? 4'h8 : 4'h0; // @[Mux.scala 27:73]
+ wire [1:0] _io_num_1_T_43 = _io_num_1_T_23 ? 2'h3 : 2'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_1_T_44 = _io_num_1_T_25 ? 7'h46 : 7'h0; // @[Mux.scala 27:73]
+ wire [5:0] _io_num_1_T_45 = _io_num_1_T_27 ? 6'h21 : 6'h0; // @[Mux.scala 27:73]
+ wire [2:0] _io_num_1_T_46 = _io_num_1_T_29 ? 3'h6 : 3'h0; // @[Mux.scala 27:73]
+ wire [3:0] _io_num_1_T_47 = _io_num_1_T_31 ? 4'he : 4'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_1_T_48 = _io_num_1_T_32 | _io_num_1_T_33; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_14 = {{1'd0}, _io_num_1_T_34}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_1_T_49 = _io_num_1_T_48 | _GEN_14; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_15 = {{1'd0}, _io_num_1_T_35}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_1_T_50 = _io_num_1_T_49 | _GEN_15; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_16 = {{2'd0}, _io_num_1_T_36}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_1_T_51 = _io_num_1_T_50 | _GEN_16; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_17 = {{2'd0}, _io_num_1_T_37}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_1_T_52 = _io_num_1_T_51 | _GEN_17; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_18 = {{5'd0}, _io_num_1_T_38}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_1_T_53 = _io_num_1_T_52 | _GEN_18; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_1_T_54 = _io_num_1_T_53 | _io_num_1_T_39; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_1_T_56 = _io_num_1_T_54 | _io_num_1_T_41; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_19 = {{3'd0}, _io_num_1_T_42}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_1_T_57 = _io_num_1_T_56 | _GEN_19; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_20 = {{5'd0}, _io_num_1_T_43}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_1_T_58 = _io_num_1_T_57 | _GEN_20; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_1_T_59 = _io_num_1_T_58 | _io_num_1_T_44; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_21 = {{1'd0}, _io_num_1_T_45}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_1_T_60 = _io_num_1_T_59 | _GEN_21; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_22 = {{4'd0}, _io_num_1_T_46}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_1_T_61 = _io_num_1_T_60 | _GEN_22; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_23 = {{3'd0}, _io_num_1_T_47}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_1_T_62 = _io_num_1_T_61 | _GEN_23; // @[Mux.scala 27:73]
+ wire _io_num_2_T_1 = lfsr[11:8] == 4'h0; // @[Sky130BLFSR.scala 56:27]
+ wire _io_num_2_T_3 = lfsr[11:8] == 4'h1; // @[Sky130BLFSR.scala 57:27]
+ wire _io_num_2_T_5 = lfsr[11:8] == 4'h2; // @[Sky130BLFSR.scala 58:27]
+ wire _io_num_2_T_7 = lfsr[11:8] == 4'h3; // @[Sky130BLFSR.scala 59:27]
+ wire _io_num_2_T_9 = lfsr[11:8] == 4'h4; // @[Sky130BLFSR.scala 60:27]
+ wire _io_num_2_T_11 = lfsr[11:8] == 4'h5; // @[Sky130BLFSR.scala 61:27]
+ wire _io_num_2_T_13 = lfsr[11:8] == 4'h6; // @[Sky130BLFSR.scala 62:27]
+ wire _io_num_2_T_15 = lfsr[11:8] == 4'h7; // @[Sky130BLFSR.scala 63:27]
+ wire _io_num_2_T_19 = lfsr[11:8] == 4'h9; // @[Sky130BLFSR.scala 65:27]
+ wire _io_num_2_T_21 = lfsr[11:8] == 4'ha; // @[Sky130BLFSR.scala 66:27]
+ wire _io_num_2_T_23 = lfsr[11:8] == 4'hb; // @[Sky130BLFSR.scala 67:27]
+ wire _io_num_2_T_25 = lfsr[11:8] == 4'hc; // @[Sky130BLFSR.scala 68:27]
+ wire _io_num_2_T_27 = lfsr[11:8] == 4'hd; // @[Sky130BLFSR.scala 69:27]
+ wire _io_num_2_T_29 = lfsr[11:8] == 4'he; // @[Sky130BLFSR.scala 70:27]
+ wire _io_num_2_T_31 = lfsr[11:8] == 4'hf; // @[Sky130BLFSR.scala 71:27]
+ wire [6:0] _io_num_2_T_32 = _io_num_2_T_1 ? 7'h40 : 7'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_2_T_33 = _io_num_2_T_3 ? 7'h79 : 7'h0; // @[Mux.scala 27:73]
+ wire [5:0] _io_num_2_T_34 = _io_num_2_T_5 ? 6'h24 : 6'h0; // @[Mux.scala 27:73]
+ wire [5:0] _io_num_2_T_35 = _io_num_2_T_7 ? 6'h30 : 6'h0; // @[Mux.scala 27:73]
+ wire [4:0] _io_num_2_T_36 = _io_num_2_T_9 ? 5'h19 : 5'h0; // @[Mux.scala 27:73]
+ wire [4:0] _io_num_2_T_37 = _io_num_2_T_11 ? 5'h12 : 5'h0; // @[Mux.scala 27:73]
+ wire [1:0] _io_num_2_T_38 = _io_num_2_T_13 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_2_T_39 = _io_num_2_T_15 ? 7'h78 : 7'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_2_T_41 = _io_num_2_T_19 ? 7'h6f : 7'h0; // @[Mux.scala 27:73]
+ wire [3:0] _io_num_2_T_42 = _io_num_2_T_21 ? 4'h8 : 4'h0; // @[Mux.scala 27:73]
+ wire [1:0] _io_num_2_T_43 = _io_num_2_T_23 ? 2'h3 : 2'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_2_T_44 = _io_num_2_T_25 ? 7'h46 : 7'h0; // @[Mux.scala 27:73]
+ wire [5:0] _io_num_2_T_45 = _io_num_2_T_27 ? 6'h21 : 6'h0; // @[Mux.scala 27:73]
+ wire [2:0] _io_num_2_T_46 = _io_num_2_T_29 ? 3'h6 : 3'h0; // @[Mux.scala 27:73]
+ wire [3:0] _io_num_2_T_47 = _io_num_2_T_31 ? 4'he : 4'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_2_T_48 = _io_num_2_T_32 | _io_num_2_T_33; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_24 = {{1'd0}, _io_num_2_T_34}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_2_T_49 = _io_num_2_T_48 | _GEN_24; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_25 = {{1'd0}, _io_num_2_T_35}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_2_T_50 = _io_num_2_T_49 | _GEN_25; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_26 = {{2'd0}, _io_num_2_T_36}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_2_T_51 = _io_num_2_T_50 | _GEN_26; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_27 = {{2'd0}, _io_num_2_T_37}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_2_T_52 = _io_num_2_T_51 | _GEN_27; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_28 = {{5'd0}, _io_num_2_T_38}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_2_T_53 = _io_num_2_T_52 | _GEN_28; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_2_T_54 = _io_num_2_T_53 | _io_num_2_T_39; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_2_T_56 = _io_num_2_T_54 | _io_num_2_T_41; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_29 = {{3'd0}, _io_num_2_T_42}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_2_T_57 = _io_num_2_T_56 | _GEN_29; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_30 = {{5'd0}, _io_num_2_T_43}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_2_T_58 = _io_num_2_T_57 | _GEN_30; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_2_T_59 = _io_num_2_T_58 | _io_num_2_T_44; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_31 = {{1'd0}, _io_num_2_T_45}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_2_T_60 = _io_num_2_T_59 | _GEN_31; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_32 = {{4'd0}, _io_num_2_T_46}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_2_T_61 = _io_num_2_T_60 | _GEN_32; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_33 = {{3'd0}, _io_num_2_T_47}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_2_T_62 = _io_num_2_T_61 | _GEN_33; // @[Mux.scala 27:73]
+ wire _io_num_3_T_1 = lfsr[15:12] == 4'h0; // @[Sky130BLFSR.scala 56:27]
+ wire _io_num_3_T_3 = lfsr[15:12] == 4'h1; // @[Sky130BLFSR.scala 57:27]
+ wire _io_num_3_T_5 = lfsr[15:12] == 4'h2; // @[Sky130BLFSR.scala 58:27]
+ wire _io_num_3_T_7 = lfsr[15:12] == 4'h3; // @[Sky130BLFSR.scala 59:27]
+ wire _io_num_3_T_9 = lfsr[15:12] == 4'h4; // @[Sky130BLFSR.scala 60:27]
+ wire _io_num_3_T_11 = lfsr[15:12] == 4'h5; // @[Sky130BLFSR.scala 61:27]
+ wire _io_num_3_T_13 = lfsr[15:12] == 4'h6; // @[Sky130BLFSR.scala 62:27]
+ wire _io_num_3_T_15 = lfsr[15:12] == 4'h7; // @[Sky130BLFSR.scala 63:27]
+ wire _io_num_3_T_19 = lfsr[15:12] == 4'h9; // @[Sky130BLFSR.scala 65:27]
+ wire _io_num_3_T_21 = lfsr[15:12] == 4'ha; // @[Sky130BLFSR.scala 66:27]
+ wire _io_num_3_T_23 = lfsr[15:12] == 4'hb; // @[Sky130BLFSR.scala 67:27]
+ wire _io_num_3_T_25 = lfsr[15:12] == 4'hc; // @[Sky130BLFSR.scala 68:27]
+ wire _io_num_3_T_27 = lfsr[15:12] == 4'hd; // @[Sky130BLFSR.scala 69:27]
+ wire _io_num_3_T_29 = lfsr[15:12] == 4'he; // @[Sky130BLFSR.scala 70:27]
+ wire _io_num_3_T_31 = lfsr[15:12] == 4'hf; // @[Sky130BLFSR.scala 71:27]
+ wire [6:0] _io_num_3_T_32 = _io_num_3_T_1 ? 7'h40 : 7'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_3_T_33 = _io_num_3_T_3 ? 7'h79 : 7'h0; // @[Mux.scala 27:73]
+ wire [5:0] _io_num_3_T_34 = _io_num_3_T_5 ? 6'h24 : 6'h0; // @[Mux.scala 27:73]
+ wire [5:0] _io_num_3_T_35 = _io_num_3_T_7 ? 6'h30 : 6'h0; // @[Mux.scala 27:73]
+ wire [4:0] _io_num_3_T_36 = _io_num_3_T_9 ? 5'h19 : 5'h0; // @[Mux.scala 27:73]
+ wire [4:0] _io_num_3_T_37 = _io_num_3_T_11 ? 5'h12 : 5'h0; // @[Mux.scala 27:73]
+ wire [1:0] _io_num_3_T_38 = _io_num_3_T_13 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_3_T_39 = _io_num_3_T_15 ? 7'h78 : 7'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_3_T_41 = _io_num_3_T_19 ? 7'h6f : 7'h0; // @[Mux.scala 27:73]
+ wire [3:0] _io_num_3_T_42 = _io_num_3_T_21 ? 4'h8 : 4'h0; // @[Mux.scala 27:73]
+ wire [1:0] _io_num_3_T_43 = _io_num_3_T_23 ? 2'h3 : 2'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_3_T_44 = _io_num_3_T_25 ? 7'h46 : 7'h0; // @[Mux.scala 27:73]
+ wire [5:0] _io_num_3_T_45 = _io_num_3_T_27 ? 6'h21 : 6'h0; // @[Mux.scala 27:73]
+ wire [2:0] _io_num_3_T_46 = _io_num_3_T_29 ? 3'h6 : 3'h0; // @[Mux.scala 27:73]
+ wire [3:0] _io_num_3_T_47 = _io_num_3_T_31 ? 4'he : 4'h0; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_3_T_48 = _io_num_3_T_32 | _io_num_3_T_33; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_34 = {{1'd0}, _io_num_3_T_34}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_3_T_49 = _io_num_3_T_48 | _GEN_34; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_35 = {{1'd0}, _io_num_3_T_35}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_3_T_50 = _io_num_3_T_49 | _GEN_35; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_36 = {{2'd0}, _io_num_3_T_36}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_3_T_51 = _io_num_3_T_50 | _GEN_36; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_37 = {{2'd0}, _io_num_3_T_37}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_3_T_52 = _io_num_3_T_51 | _GEN_37; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_38 = {{5'd0}, _io_num_3_T_38}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_3_T_53 = _io_num_3_T_52 | _GEN_38; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_3_T_54 = _io_num_3_T_53 | _io_num_3_T_39; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_3_T_56 = _io_num_3_T_54 | _io_num_3_T_41; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_39 = {{3'd0}, _io_num_3_T_42}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_3_T_57 = _io_num_3_T_56 | _GEN_39; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_40 = {{5'd0}, _io_num_3_T_43}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_3_T_58 = _io_num_3_T_57 | _GEN_40; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_3_T_59 = _io_num_3_T_58 | _io_num_3_T_44; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_41 = {{1'd0}, _io_num_3_T_45}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_3_T_60 = _io_num_3_T_59 | _GEN_41; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_42 = {{4'd0}, _io_num_3_T_46}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_3_T_61 = _io_num_3_T_60 | _GEN_42; // @[Mux.scala 27:73]
+ wire [6:0] _GEN_43 = {{3'd0}, _io_num_3_T_47}; // @[Mux.scala 27:73]
+ wire [6:0] _io_num_3_T_62 = _io_num_3_T_61 | _GEN_43; // @[Mux.scala 27:73]
+ MaxPeriodFibonacciLFSR lfsr_prng ( // @[PRNG.scala 91:22]
+ .clock(lfsr_prng_clock),
+ .reset(lfsr_prng_reset),
+ .io_increment(lfsr_prng_io_increment),
+ .io_out_0(lfsr_prng_io_out_0),
+ .io_out_1(lfsr_prng_io_out_1),
+ .io_out_2(lfsr_prng_io_out_2),
+ .io_out_3(lfsr_prng_io_out_3),
+ .io_out_4(lfsr_prng_io_out_4),
+ .io_out_5(lfsr_prng_io_out_5),
+ .io_out_6(lfsr_prng_io_out_6),
+ .io_out_7(lfsr_prng_io_out_7),
+ .io_out_8(lfsr_prng_io_out_8),
+ .io_out_9(lfsr_prng_io_out_9),
+ .io_out_10(lfsr_prng_io_out_10),
+ .io_out_11(lfsr_prng_io_out_11),
+ .io_out_12(lfsr_prng_io_out_12),
+ .io_out_13(lfsr_prng_io_out_13),
+ .io_out_14(lfsr_prng_io_out_14),
+ .io_out_15(lfsr_prng_io_out_15)
+ );
+ assign io_num_0 = io_lock ? 7'h7f : _io_num_0_T_62; // @[Sky130BLFSR.scala 52:21 53:17 55:17]
+ assign io_num_1 = io_lock ? 7'h7f : _io_num_1_T_62; // @[Sky130BLFSR.scala 52:21 53:17 55:17]
+ assign io_num_2 = io_lock ? 7'h7f : _io_num_2_T_62; // @[Sky130BLFSR.scala 52:21 53:17 55:17]
+ assign io_num_3 = io_lock ? 7'h7f : _io_num_3_T_62; // @[Sky130BLFSR.scala 52:21 53:17 55:17]
+ assign lfsr_prng_clock = clock;
+ assign lfsr_prng_reset = reset;
+ assign lfsr_prng_io_increment = ~io_lock; // @[Sky130BLFSR.scala 48:23]
+endmodule
diff --git a/verilog/rtl/rift2Fake.v b/verilog/rtl/rift2Fake.v
new file mode 100644
index 0000000..4a11fd2
--- /dev/null
+++ b/verilog/rtl/rift2Fake.v
@@ -0,0 +1,96 @@
+// SPDX-FileCopyrightText: 2022 Wuhan University of Technology
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+module rift2Wrap(
+`ifdef USE_POWER_PINS
+ inout vdd, // User area 5.0V supply
+ inout vss, // User area ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [63:0] la_data_in,
+ output [63:0] la_data_out,
+ input [63:0] la_oenb,
+
+ // IOs
+ input [38-1:0] io_in,
+ output [38-1:0] io_out,
+ output [38-1:0] io_oeb,
+
+
+
+ // Independent clock (on independent integer divider)
+ input user_clock2,
+
+ // User maskable interrupt signals
+ output [2:0] user_irq
+
+);
+
+wire clock;
+
+wire [6:0] io_num_0;
+wire [6:0] io_num_1;
+wire [6:0] io_num_2;
+wire [6:0] io_num_3;
+wire io_lock;
+
+
+
+assign clock = wb_clk_i;
+
+
+
+
+Sky130BLFSR i_fake(
+ .clock(clock),
+ .reset(wb_rst_i),
+ .io_num_0(io_num_0),
+ .io_num_1(io_num_1),
+ .io_num_2(io_num_2),
+ .io_num_3(io_num_3),
+ .io_lock(io_lock)
+);
+
+
+
+assign io_oeb[27:0] = 28'b0;
+assign io_out[27:0] = {io_num_3, io_num_2, io_num_1, io_num_0};
+assign la_data_out[27:0] = {io_num_3, io_num_2, io_num_1, io_num_0};
+
+//lock input
+assign io_oeb[28] = 1'b1;
+assign io_lock = (~la_oenb[0]) ? la_data_in[0] : io_in[28];
+assign io_out[28] = 1'b0;
+
+
+assign io_oeb[37:29] = 9'b0;
+assign io_out[37:29] = 9'b0;
+
+
+endmodule
+
diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v
index d16d493..0f767a6 100644
--- a/verilog/rtl/user_defines.v
+++ b/verilog/rtl/user_defines.v
@@ -50,41 +50,41 @@
// up in a state that can be used immediately without depending on
// the management SoC to run a startup program to configure the GPIOs.
-`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_INVALID
+`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
// Configurations of GPIO 14 to 24 are used on caravel but not caravan.
-`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_INVALID
+`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
-`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_29_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_INVALID
+`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_29_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
`endif // __USER_DEFINES_H
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 78cd884..f68fdb4 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -65,101 +65,63 @@
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,
- // IRQ
- output [2:0] irq
-);
- wire clk;
- wire rst;
- wire [`MPRJ_IO_PADS-1:0] io_in;
- wire [`MPRJ_IO_PADS-1:0] io_out;
- wire [`MPRJ_IO_PADS-1:0] io_oeb;
-
- wire [31:0] rdata;
- wire [31:0] wdata;
- wire [BITS-1:0] count;
-
- wire valid;
- wire [3:0] wstrb;
- wire [31:0] la_write;
-
- // WB MI A
- assign valid = wbs_cyc_i && wbs_stb_i;
- assign wstrb = wbs_sel_i & {4{wbs_we_i}};
- assign wbs_dat_o = rdata;
- assign wdata = wbs_dat_i;
-
- // IO
- assign io_out = count;
- assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
+ input user_clock2,
// IRQ
- assign irq = 3'b000; // Unused
-
- // LA
- assign la_data_out = {{(127-BITS){1'b0}}, count};
- // Assuming LA probes [63:32] are for controlling the count register
- assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
- // Assuming LA probes [65:64] are for controlling the count clk & reset
- assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
- assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
-
- counter #(
- .BITS(BITS)
- ) counter(
- .clk(clk),
- .reset(rst),
- .ready(wbs_ack_o),
- .valid(valid),
- .rdata(rdata),
- .wdata(wbs_dat_i),
- .wstrb(wstrb),
- .la_write(la_write),
- .la_input(la_data_in[63:32]),
- .count(count)
- );
-
-endmodule
-
-module counter #(
- parameter BITS = 32
-)(
- input clk,
- input reset,
- input valid,
- input [3:0] wstrb,
- input [BITS-1:0] wdata,
- input [BITS-1:0] la_write,
- input [BITS-1:0] la_input,
- output ready,
- output [BITS-1:0] rdata,
- output [BITS-1:0] count
+ output [2:0] user_irq
);
- reg ready;
- reg [BITS-1:0] count;
- reg [BITS-1:0] rdata;
- always @(posedge clk) begin
- if (reset) begin
- count <= 0;
- ready <= 0;
- end else begin
- ready <= 1'b0;
- if (~|la_write) begin
- count <= count + 1;
- end
- if (valid && !ready) begin
- ready <= 1'b1;
- rdata <= count;
- if (wstrb[0]) count[7:0] <= wdata[7:0];
- if (wstrb[1]) count[15:8] <= wdata[15:8];
- if (wstrb[2]) count[23:16] <= wdata[23:16];
- if (wstrb[3]) count[31:24] <= wdata[31:24];
- end else if (|la_write) begin
- count <= la_write & la_input;
- end
- end
+
+
+ assign wbs_ack_o = 1'b1;
+ assign wbs_dat_o = 32'b0;
+ assign la_data_out = 64'b0;
+ assign io_out[7:0] = 8'b0;
+ assign io_out[37:22] = 16'b0;
+ assign io_oeb = 38'b0;
+ assign user_irq = 3'b0;
+
+HC138 i_hc138(
+ .A(io_in[10:8]),
+ .G(io_in[13:11]),
+ .Y(io_out[21:14])
+);
+
+ reg [5:0] temp_reg;
+ always @(posedge wb_clk_i ) begin
+ temp_reg <= io_in[13:8];
end
+ assign io_out[13:8] = temp_reg;
+
endmodule
+
+
+
+
+module HC138(
+ input [2:0] A,
+ input [2:0] G,
+ output [7:0] Y
+);
+
+assign Y[0] = ~((G == 3'b100) & (A == 3'b000));
+assign Y[1] = ~((G == 3'b100) & (A == 3'b001));
+assign Y[2] = ~((G == 3'b100) & (A == 3'b010));
+assign Y[3] = ~((G == 3'b100) & (A == 3'b011));
+assign Y[4] = ~((G == 3'b100) & (A == 3'b100));
+assign Y[5] = ~((G == 3'b100) & (A == 3'b101));
+assign Y[6] = ~((G == 3'b100) & (A == 3'b110));
+assign Y[7] = ~((G == 3'b100) & (A == 3'b111));
+
+
+
+
+
+
+endmodule
+
+
+
`default_nettype wire
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 146877d..f7dc145 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -70,7 +70,7 @@
/* User project is instantiated here */
/*--------------------------------------*/
-user_proj_example mprj (
+rift2Wrap i_rift2Wrap (
`ifdef USE_POWER_PINS
.vdd(vdd), // User area 1 1.8V power
.vss(vss), // User area 1 digital ground
@@ -102,8 +102,10 @@
.io_out(io_out),
.io_oeb(io_oeb),
+
+ .user_clock2(user_clock2),
// IRQ
- .irq(user_irq)
+ .user_irq(user_irq)
);
endmodule // user_project_wrapper
