| # VerilogBoy GFMPW0 |
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| Uses VerilogBoy design from https://github.com/zephray/VerilogBoy. |
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| VerilogBoy is a GameBoy-compatible system design in synthesizable Verilog RTL. The submission for GFMPW0 includes the following components: |
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| - SM83 (GBZ80) CPU core |
| - Pixel processing unit |
| - Programmable sound generator |
| - Timer |
| - Stereo PDM audio output |
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| To form a complete GB system, users need to provide the following additional components: |
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| - Generic 16KB Async SRAM |
| - Some buttons for input |
| - 160x144 LCD |
| - Low pass filter and audio amplifier |
| - Unmodified GameBoy game cartridge |
| - Small amount of glue logic |
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| The simtop.v maybe used as a reference on external components required. |
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| A Verilator-based testbench is provided in verilog/sim. |
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| ## Implementation Results |
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| The implementation has 43% ultilization of a 1.5mm x 1.5 mm core area. The Fmax is around 20MHz at typical corner, 3.3V with no hold violation. The design is supposed to run up to 4MHz at 5V. |
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| ## License |
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| Unless otherwise stated, HDL codes are licensed under OHDL 1.0, and software codes are licensed under MIT. |
