)]}'
{
  "commit": "ea993b96f1d000dac820f2a6179295b225fc9b35",
  "tree": "64a73ccc8e88bcb30c59801fe123d48889125a10",
  "parents": [
    "7cb1b88314024241002d67955ba1e626bc6673a7"
  ],
  "author": {
    "name": "Wenting Zhang",
    "email": "zephray@outlook.com",
    "time": "Fri Nov 25 20:17:40 2022 -0500"
  },
  "committer": {
    "name": "Wenting Zhang",
    "email": "zephray@outlook.com",
    "time": "Fri Nov 25 20:17:40 2022 -0500"
  },
  "message": "Multiplex main RAM, cartridge, and video RAM access on the same bus\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "09a78860a406148b903c76241ecf612cd8217feb",
      "new_mode": 33188,
      "new_path": "verilog/rtl/README.md"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "89765e61e32f3560b42161087c6b2dd4ae9fecd7",
      "new_mode": 33188,
      "new_path": "verilog/rtl/async_ram.v"
    },
    {
      "type": "modify",
      "old_id": "69c2d65e5432fc1d3b2dc5680e1bfcd6d7b6f1bf",
      "old_mode": 33188,
      "old_path": "verilog/rtl/boy.v",
      "new_id": "b437e098d74183b77870a93769aaa127e8073abd",
      "new_mode": 33188,
      "new_path": "verilog/rtl/boy.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "ffceb0c120ce1867487755e58bfc2e9ae2c03480",
      "new_mode": 33188,
      "new_path": "verilog/rtl/chip.v"
    },
    {
      "type": "modify",
      "old_id": "6b5998296d332cd5b78cf9d051c132a1aacb7860",
      "old_mode": 33188,
      "old_path": "verilog/rtl/cpu.v",
      "new_id": "cd6df6b30607e2ca8418ae2c3eaf8aae60eaff6d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/cpu.v"
    },
    {
      "type": "modify",
      "old_id": "5aaadaae6900884388265234ef5f045f2854019f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/dma.v",
      "new_id": "d384a5339b8470b4d34e29802f3ec54650b07591",
      "new_mode": 33188,
      "new_path": "verilog/rtl/dma.v"
    },
    {
      "type": "modify",
      "old_id": "bf4e1e8b439691379db49fcd4b5fa980121d0c76",
      "old_mode": 33188,
      "old_path": "verilog/rtl/ppu.v",
      "new_id": "01ab72e9831825cf1085fa9b1d4555499a4b0fbb",
      "new_mode": 33188,
      "new_path": "verilog/rtl/ppu.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "64a5070c3252ad85d98a2609dae7b37f95f3cfa2",
      "new_mode": 33188,
      "new_path": "verilog/rtl/simtop.v"
    },
    {
      "type": "modify",
      "old_id": "415ae0a01b2af5405eba1da7e6dea43b2ac1c184",
      "old_mode": 33188,
      "old_path": "verilog/sim/Makefile",
      "new_id": "eb563308ecf818e04d7e0f2e9383c12cc68f7ef6",
      "new_mode": 33188,
      "new_path": "verilog/sim/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "e4e13d435151a7a8bff37abd67ef85e86b6d3d4a",
      "new_mode": 40960,
      "new_path": "verilog/sim/bootrom.mif"
    },
    {
      "type": "modify",
      "old_id": "c181510c026e5c9679fb1842a81d32345c55506a",
      "old_mode": 33188,
      "old_path": "verilog/sim/main.cpp",
      "new_id": "a7d33bd6fcf7cee2d21ac7d696770900b70bb797",
      "new_mode": 33188,
      "new_path": "verilog/sim/main.cpp"
    },
    {
      "type": "modify",
      "old_id": "0cbf3b0c379f2c0c54a89dad060408474dc8d7f5",
      "old_mode": 33188,
      "old_path": "verilog/sim/memsim.cpp",
      "new_id": "bf79380b3c772d281656de6070973f6e12e604c2",
      "new_mode": 33188,
      "new_path": "verilog/sim/memsim.cpp"
    },
    {
      "type": "modify",
      "old_id": "8ce05d2c1ed506d40a957fdb21c4623b8d5f16c3",
      "old_mode": 33188,
      "old_path": "verilog/sim/memsim.h",
      "new_id": "8457d32a6041beeddc7c567a6f8cd494168e4273",
      "new_mode": 33188,
      "new_path": "verilog/sim/memsim.h"
    },
    {
      "type": "modify",
      "old_id": "fdc9c72d89a936ee1af738feb167b6f1f4e35a2b",
      "old_mode": 33188,
      "old_path": "verilog/sim/rtl.mk",
      "new_id": "024e74e7abe7bf4c661bc2fe3379fc8757dbe70a",
      "new_mode": 33188,
      "new_path": "verilog/sim/rtl.mk"
    }
  ]
}
