2022-12-06 01:52:01 - [INFO] - {{Project Git Info}} Repository: https://github.com/zephray/vb-gfmpw0.git | Branch: vb | Commit: 699f293d3fd3f96ec7fd01e478b46622dbf2f95c
2022-12-06 01:52:01 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: verilogboy
2022-12-06 01:52:01 - [INFO] - {{Project Type Info}} digital
2022-12-06 01:52:02 - [INFO] - {{Project GDS Info}} user_project_wrapper: fdfb37681ec10a1fb3db136742362d859390fabf
2022-12-06 01:52:02 - [INFO] - {{Tools Info}} KLayout: v0.27.12 | Magic: v8.3.340
2022-12-06 01:52:02 - [INFO] - {{PDKs Info}} GF180MCUC: a897aa30369d3bcec87d9d50ce9b01f320f854ef | Open PDKs: 120b0bd69c745825a0b8b76f364043a1cd08bb6a
2022-12-06 01:52:02 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'verilogboy/jobs/mpw_precheck/63ed808a-ad87-4282-b2bf-68f023be6959/logs'
2022-12-06 01:52:02 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, GPIO-Defines, XOR, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density]
2022-12-06 01:52:02 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 7: License
2022-12-06 01:52:03 - [INFO] - An approved LICENSE (Apache-2.0) was found in verilogboy.
2022-12-06 01:52:03 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2022-12-06 01:52:04 - [INFO] - An approved LICENSE (Apache-2.0) was found in verilogboy.
2022-12-06 01:52:04 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2022-12-06 01:52:05 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in verilogboy/verilog/sim/bootrom.mif
2022-12-06 01:52:05 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 59 non-compliant file(s) with the SPDX Standard.
2022-12-06 01:52:05 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['verilogboy/lib/user_project_wrapper.lib', 'verilogboy/lib/vb_wrapper.lib', 'verilogboy/sdc/user_project_wrapper.sdc', 'verilogboy/sdc/vb_wrapper.sdc', 'verilogboy/sdf/user_project_wrapper.sdf', 'verilogboy/sdf/vb_wrapper.sdf', 'verilogboy/spef/user_project_wrapper.spef', 'verilogboy/spef/vb_wrapper.spef', 'verilogboy/verilog/includes/includes.gl+sdf.caravel_user_project', 'verilogboy/verilog/includes/includes.gl.caravel_user_project', 'verilogboy/verilog/includes/includes.rtl.caravel_user_project', 'verilogboy/verilog/rtl/alu.v', 'verilogboy/verilog/rtl/async_ram.v', 'verilogboy/verilog/rtl/bin2v.py', 'verilogboy/verilog/rtl/boy.v']
2022-12-06 01:52:05 - [INFO] - For the full SPDX compliance report check: verilogboy/jobs/mpw_precheck/63ed808a-ad87-4282-b2bf-68f023be6959/logs/spdx_compliance_report.log
2022-12-06 01:52:05 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 7: GPIO-Defines
2022-12-06 01:52:05 - [INFO] - GPIO-DEFINES: Checking verilog/rtl/user_defines.v, parsing files: ['/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_base.v', 'verilogboy/verilog/rtl/user_defines.v', '/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_observe.v']
2022-12-06 01:52:06 - [INFO] - GPIO-DEFINES report path: verilogboy/jobs/mpw_precheck/63ed808a-ad87-4282-b2bf-68f023be6959/outputs/reports/gpio_defines.report
2022-12-06 01:52:06 - [INFO] - {{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid.
2022-12-06 01:52:06 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 7: XOR
2022-12-06 01:52:33 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view verilogboy/jobs/mpw_precheck/63ed808a-ad87-4282-b2bf-68f023be6959/outputs/user_project_wrapper.xor.gds
2022-12-06 01:52:33 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2022-12-06 01:52:33 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 7: Klayout FEOL
2022-12-06 01:52:33 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-06 01:52:33 - [INFO] - run: klayout -b -r /opt/checks/tech-files/gf180mcuC_mr.drc -rd input=verilogboy/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=verilogboy/jobs/mpw_precheck/63ed808a-ad87-4282-b2bf-68f023be6959/outputs/reports/klayout_feol_check.xml -rd feol=true -rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd conn_drc=true >& verilogboy/jobs/mpw_precheck/63ed808a-ad87-4282-b2bf-68f023be6959/logs/klayout_feol_check.log
2022-12-06 02:45:06 - [INFO] - No DRC Violations found
2022-12-06 02:45:06 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-06 02:45:06 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 7: Klayout BEOL
2022-12-06 02:45:06 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-06 02:45:06 - [INFO] - run: klayout -b -r /opt/checks/tech-files/gf180mcuC_mr.drc -rd input=verilogboy/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=verilogboy/jobs/mpw_precheck/63ed808a-ad87-4282-b2bf-68f023be6959/outputs/reports/klayout_beol_check.xml -rd beol=true -rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd conn_drc=true >& verilogboy/jobs/mpw_precheck/63ed808a-ad87-4282-b2bf-68f023be6959/logs/klayout_beol_check.log
2022-12-06 03:13:19 - [INFO] - No DRC Violations found
2022-12-06 03:13:19 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-06 03:13:19 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 7: Klayout Offgrid
2022-12-06 03:13:19 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-06 03:13:19 - [INFO] - run: klayout -b -r /opt/checks/tech-files/gf180mcuC_mr.drc -rd input=verilogboy/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=verilogboy/jobs/mpw_precheck/63ed808a-ad87-4282-b2bf-68f023be6959/outputs/reports/klayout_offgrid_check.xml -rd offgrid=true -rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd conn_drc=true >& verilogboy/jobs/mpw_precheck/63ed808a-ad87-4282-b2bf-68f023be6959/logs/klayout_offgrid_check.log
2022-12-06 03:35:44 - [INFO] - No DRC Violations found
2022-12-06 03:35:44 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-06 03:35:44 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 7: Klayout Metal Minimum Clear Area Density
2022-12-06 03:35:44 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-06 03:35:44 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/gf180mcu_density.lydrc -rd input=verilogboy/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=verilogboy/jobs/mpw_precheck/63ed808a-ad87-4282-b2bf-68f023be6959/outputs/reports/klayout_met_min_ca_density_check.xml >& verilogboy/jobs/mpw_precheck/63ed808a-ad87-4282-b2bf-68f023be6959/logs/klayout_met_min_ca_density_check.log
2022-12-06 03:35:47 - [INFO] - No DRC Violations found
2022-12-06 03:35:47 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-06 03:35:47 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'verilogboy/jobs/mpw_precheck/63ed808a-ad87-4282-b2bf-68f023be6959/logs'
2022-12-06 03:35:47 - [INFO] - {{SUCCESS}} All Checks Passed !!!