diff --git a/verilog/rtl/chip.v b/verilog/rtl/chip.v
index eab7503..02e76de 100644
--- a/verilog/rtl/chip.v
+++ b/verilog/rtl/chip.v
@@ -27,17 +27,17 @@
     output reg cs, // Cartridge chip select
     output wire hsync, // LCD horizontal sync
     output wire vsync, // LCD vertical sync
+    output wire csync, // LCD composite sync
     output wire pvalid, // LCD pixel valid/ clock gate
     output wire [1:0] pixel, // LCD pixel output
     input wire skey, // Serial key input
-    output wire audiol, // Audio left output
-    output wire audior, // Audio right output
-    input wire mode, // Test mode
+    output wire audiolr, // Audio left/right output
     // For testbench only
     output wire done,
     output wire fault
 );
     wire rst = !rstn;
+
     wire [1:0] ct;
     wire [15:0] cpu_a;
     wire [7:0] cpu_dout;
@@ -86,6 +86,7 @@
         .fault(fault)
     );
 
+    assign csync = hsync ^ vsync;
     assign ppu_a[15:13] = 3'b100;
 
     // Internal SRAM (WRAM + VRAM, 16KB)
@@ -147,9 +148,23 @@
     end
 
     // Audio PDM
+    reg lrck;
+    always @(posedge clk) begin
+        if (rst) begin
+            lrck <= 1'b0;
+        end
+        else begin
+            lrck <= ~lrck;
+        end
+    end
+
+    wire audiol;
+    wire audior;
+
     sdm1b #(.W(9)) sdm_left (
         .clk_fast(clk),
-        .rst_n(rstn),
+        .rst(rst),
+        .enable(lrck),
         .din(left[14:6]),
         .error(),
         .dout(audiol)
@@ -157,17 +172,20 @@
 
     sdm1b #(.W(9)) sdm_right (
         .clk_fast(clk),
-        .rst_n(rstn),
+        .rst(rst),
+        .enable(!lrck),
         .din(right[14:6]),
         .error(),
         .dout(audior)
     );
 
+    assign audiolr = (lrck) ? (audiol) : (audior);
+
     // Key serial to parallel
     reg [7:0] key_sr;
     reg [3:0] counter;
     always @(posedge clk) begin
-        if (hsync) begin
+        if (csync) begin
             counter <= 4'b0;
         end
         else begin
diff --git a/verilog/rtl/lfsr_prbs_gen.v b/verilog/rtl/lfsr_prbs_gen.v
index 4f66086..3bd5ca1 100644
--- a/verilog/rtl/lfsr_prbs_gen.v
+++ b/verilog/rtl/lfsr_prbs_gen.v
@@ -43,7 +43,7 @@
     parameter STYLE = "AUTO"
 ) (
     input  wire                  clk,
-    input  wire                  rst_n,
+    input  wire                  rst,
     input  wire                  enable,
     output wire [DATA_WIDTH-1:0] data_out
 );
@@ -154,14 +154,14 @@
 
     always @* begin
         if (INVERT) begin
-            output_reg <= ~lfsr_data;
+            output_reg = ~lfsr_data;
         end else begin
-            output_reg <= lfsr_data;
+            output_reg = lfsr_data;
         end
     end
 
-    always @(posedge clk or negedge rst_n) begin
-        if (~rst_n) begin
+    always @(posedge clk) begin
+        if (rst) begin
             state_reg <= LFSR_INIT;
         end else begin
             if (enable) begin
diff --git a/verilog/rtl/ppu.v b/verilog/rtl/ppu.v
index 662fbb1..c230c1a 100644
--- a/verilog/rtl/ppu.v
+++ b/verilog/rtl/ppu.v
@@ -157,12 +157,12 @@
     reg [7:0] oam_rd_addr_int;
     wire [7:0] oam_rd_addr;
     wire [7:0] oam_wr_addr;
-    reg [15:0] oam_data_out;
+    wire [15:0] oam_data_out;
     wire [7:0] oam_data_out_byte;
     wire [7:0] oam_data_in;
     wire oam_we;
     
-    always @ (negedge clk)
+    always @ (posedge clk)
     begin
         if (oam_we) begin
             if (oam_wr_addr[0])
@@ -170,10 +170,8 @@
             else
                 oam_l[oam_wr_addr[7:1]] <= oam_data_in;
         end
-        else begin
-            oam_data_out <= {oam_u[oam_rd_addr[7:1]], oam_l[oam_rd_addr[7:1]]};
-        end
     end
+    assign oam_data_out = {oam_u[oam_rd_addr[7:1]], oam_l[oam_rd_addr[7:1]]};
     
     assign oam_wr_addr = oam_a[7:0];
     assign oam_rd_addr = (oam_access_ext) ? (oam_a[7:0]) : (oam_rd_addr_int); 
diff --git a/verilog/rtl/sdm1b.v b/verilog/rtl/sdm1b.v
index 2fd3ce9..748ab3e 100644
--- a/verilog/rtl/sdm1b.v
+++ b/verilog/rtl/sdm1b.v
@@ -30,7 +30,8 @@
     parameter integer ADD_NOISE = 1
 ) (
     input          clk_fast,
-    input          rst_n,
+    input          rst,
+    input          enable,
     input  [W-1:0] din,
     output [W-1:0] error,
     output         dout
@@ -44,19 +45,21 @@
         .STYLE     ("AUTO")
     ) u_LFSR(
         .clk     (clk_fast),
-        .rst_n   (rst_n),
-        .enable  (1'b1),
+        .rst     (rst),
+        .enable  (enable),
         .data_out(lfsr_bit)
     );
     reg [W:0] acc_r = 0;
     assign dout  = acc_r[W];
     assign error = acc_r[W-1:0];
-    always @(posedge clk_fast or negedge rst_n) begin
-        if (~rst_n) begin
+    always @(posedge clk_fast) begin
+        if (rst) begin
             acc_r <= 0;
         end else begin
-            if(ADD_NOISE) acc_r <= din + error ^ lfsr_bit[0];
-            else          acc_r <= din + error;
+            if (enable) begin
+                if(ADD_NOISE) acc_r <= din + error ^ lfsr_bit[0];
+                else          acc_r <= din + error;
+            end
         end
     end
 endmodule  /* sdm1b */
\ No newline at end of file
diff --git a/verilog/rtl/simtop.v b/verilog/rtl/simtop.v
index ad1072e..9e65f34 100644
--- a/verilog/rtl/simtop.v
+++ b/verilog/rtl/simtop.v
@@ -27,8 +27,8 @@
     output wire [1:0] pixel,
     output wire valid,
     // Audio output
-    output wire audiol,
-    output wire audior,
+    output reg audiol,
+    output reg audior,
     // For testbench only
     output wire done,
     output wire fault
@@ -41,7 +41,9 @@
     wire bus_wr;
     wire bus_cale;
     wire bus_cs;
+    wire csync;
     wire skey;
+    wire audiolr;
 
     chip chip(
         .clk(clk),
@@ -51,20 +53,30 @@
         .din(bus_din),
         .doe(bus_doe),
         .wr(bus_wr),
-        .cale(bus_cale),
-        .cs(bus_cs),
         .hsync(hs),
         .vsync(vs),
+        .csync(csync),
         .pvalid(valid),
         .pixel(pixel),
         .skey(skey),
-        .audiol(audiol),
-        .audior(audior),
-        .mode(1'b0),
+        .audiolr(audiolr),
         .done(done),
         .fault(fault)
     );
 
+    reg [1:0] ct;
+    always @(posedge clk) begin
+        if (rst) begin
+            ct <= 2'd0;
+        end
+        else begin
+            ct <= ct + 1;
+        end
+    end
+
+    assign bus_cale = ct == 2'b00;
+    assign bus_cs = (ct == 2'b10) && (!bus_a[15] || (bus_a[15:13] == 3'b101));
+
     wire sram_we;
     wire [7:0] sram_dout;
     async_ram #(.WORDS(16384), .ABITS(14)) sram(
@@ -90,7 +102,7 @@
     // Key parallel to serial
     reg [7:0] key_sr;
     always @(posedge clk) begin
-        if (hs) begin
+        if (csync) begin
             key_sr <= key;
         end
         else if (valid) begin
@@ -99,4 +111,20 @@
     end
     assign skey = key_sr[7];
 
+    reg lrck;
+    always @(posedge clk) begin
+        if (rst) begin
+            lrck <= 1'b0;
+        end
+        else begin
+            lrck <= ~lrck;
+            if (lrck) begin
+                audiol <= audiolr;
+            end
+            else begin
+                audior <= audiolr;
+            end
+        end
+    end
+
 endmodule