diff --git a/verilog/rtl/edgedet.v b/verilog/rtl/edgedet.v
new file mode 100644
index 0000000..c5c9721
--- /dev/null
+++ b/verilog/rtl/edgedet.v
@@ -0,0 +1,27 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Wenting Zhang
+// 
+// Create Date:    21:19:04 04/08/2018 
+// Module Name:    edgedet
+// Project Name:   VerilogBoy
+// Description: 
+//
+// Dependencies: 
+//
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module edgedet(
+    input wire clk,
+    input wire i,
+    output wire o
+);
+
+    reg last_i;
+    always @(posedge clk)
+        last_i <= i;
+    assign o = (!last_i) && i;
+
+endmodule
diff --git a/verilog/rtl/simtop.v b/verilog/rtl/simtop.v
index 12f7b52..ad1072e 100644
--- a/verilog/rtl/simtop.v
+++ b/verilog/rtl/simtop.v
@@ -26,6 +26,9 @@
     output wire vs,
     output wire [1:0] pixel,
     output wire valid,
+    // Audio output
+    output wire audiol,
+    output wire audior,
     // For testbench only
     output wire done,
     output wire fault
@@ -55,8 +58,8 @@
         .pvalid(valid),
         .pixel(pixel),
         .skey(skey),
-        .audiol(),
-        .audior(),
+        .audiol(audiol),
+        .audior(audior),
         .mode(1'b0),
         .done(done),
         .fault(fault)
diff --git a/verilog/rtl/sound.v b/verilog/rtl/sound.v
index 2cabe88..cd02616 100644
--- a/verilog/rtl/sound.v
+++ b/verilog/rtl/sound.v
@@ -188,32 +188,25 @@
         end
     end
     
-    // Clocks
-    wire clk_frame; // 512Hz Base Clock
+    // Clock Enables (not clock)
     wire clk_length_ctr; // 256Hz Length Control Clock
     wire clk_vol_env; // 64Hz Volume Enevelope Clock
     wire clk_sweep; // 128Hz Sweep Clock
-    wire clk_freq_div; // 1048576Hz Frequency Division Clock
-    
-    clk_div #(.WIDTH(15), .DIV(8192)) frame_div(
-        .i(clk),
-        .o(clk_frame)
-    );
-    
-    reg [2:0] sequencer_state = 3'b0;
-    always@(posedge clk_frame)
-    begin
-        sequencer_state <= sequencer_state + 1'b1;
-    end
-    
-    assign clk_length_ctr = (sequencer_state[0]) ? 1'b0 : 1'b1;
-    assign clk_vol_env = (sequencer_state == 3'd7) ? 1'b1 : 1'b0;
-    assign clk_sweep = ((sequencer_state == 3'd2) || (sequencer_state == 3'd6)) ? 1'b1 : 1'b0;
+    wire clk_freq_div; // 2097152Hz Frequency Division Clock
 
-    clk_div #(.WIDTH(2), .DIV(2)) freq_div(
-        .i(clk),
-        .o(clk_freq_div)
-    );
+    reg [15:0] clk_div;
+    always @(posedge clk) begin
+        if (rst) begin
+            clk_div <= 0;
+        end
+        else begin
+            clk_div <= clk_div + 1;
+        end
+    end
+    assign clk_length_ctr = clk_div[13:0] == {14{1'b1}};
+    assign clk_vol_env = clk_div[15:0] == {16{1'b1}};
+    assign clk_sweep = clk_div[14:0] == {15{1'b1}};
+    assign clk_freq_div = clk_div[0] == 1'b1;
 
     // Channels
     wire [3:0] ch1;
diff --git a/verilog/rtl/sound_length_ctr.v b/verilog/rtl/sound_length_ctr.v
index 3a1452a..110c546 100644
--- a/verilog/rtl/sound_length_ctr.v
+++ b/verilog/rtl/sound_length_ctr.v
@@ -13,9 +13,10 @@
 // Additional Comments: 
 //   Channel 3 has a different length
 //////////////////////////////////////////////////////////////////////////////////
-module sound_length_ctr(rst, clk_length_ctr, start, single, length, enable);
+module sound_length_ctr(clk, rst, clk_length_ctr, start, single, length, enable);
     parameter WIDTH = 6; // 6bit for Ch124, 8bit for Ch3
-    
+
+    input clk;
     input rst;
     input clk_length_ctr;
     input start;
@@ -26,17 +27,13 @@
     reg [WIDTH-1:0] length_left = {WIDTH{1'b1}}; // Upcounter from length to 255
 
     // Length Control
-    always @(posedge clk_length_ctr, posedge start, posedge rst)
+    always @(posedge clk)
     begin
-        if (rst) begin
-            enable <= 1'b0;
-            length_left <= 0;
-        end
-        else if (start) begin
+        if (start) begin
             enable <= 1'b1;
             length_left <= (length == 0) ? ({WIDTH{1'b1}}) : (length);
         end
-        else begin
+        else if (clk_length_ctr) begin
             if (single) begin
                 if (length_left != {WIDTH{1'b1}})
                     length_left <= length_left + 1'b1;
@@ -44,6 +41,11 @@
                     enable <= 1'b0;
             end
         end
+
+        if (rst) begin
+            enable <= 1'b0;
+            length_left <= 0;
+        end
     end
 
 endmodule
diff --git a/verilog/rtl/sound_noise.v b/verilog/rtl/sound_noise.v
index a836bcf..a496c5b 100644
--- a/verilog/rtl/sound_noise.v
+++ b/verilog/rtl/sound_noise.v
@@ -14,7 +14,7 @@
 //
 //////////////////////////////////////////////////////////////////////////////////
 module sound_noise(
-    input rst, // Async reset
+    input rst, // Sync reset
     input clk, // CPU Clock
     input clk_length_ctr, // Length control clock
     input clk_vol_env, // Volume Envelope clock
@@ -30,34 +30,34 @@
     output [3:0] level,
     output enable
     );
+    wire start_posedge;
+    edgedet start_edgedet (
+        .clk(clk),
+        .i(start),
+        .o(start_posedge)
+    );
     
     // Dividing ratio from 4MHz is (r * 8), for the divier to work, the comparator shoud
     // compare with (dividing_factor / 2 - 1), so it becomes (r * 4 - 1)
-    reg [4:0] adjusted_freq_dividing_ratio;
+    reg [5:0] adjusted_freq_dividing_ratio;
     reg [3:0] latched_shift_clock_freq;
     
     wire [3:0] target_vol;
     
-    reg clk_div = 0;
     wire clk_shift;
     
-    reg [4:0] clk_divider = 5'b0; // First stage
+    reg [5:0] clk_divider = 6'b0; // First stage
+    reg [13:0] clk_shifter = 14'b0; // Second stage
     always @(posedge clk)
     begin
         if (clk_divider == adjusted_freq_dividing_ratio) begin
-            clk_div <= ~clk_div;
+            clk_shifter <= clk_shifter + 1'b1;
             clk_divider <= 0;
         end
         else
             clk_divider <= clk_divider + 1'b1;
     end
     
-    reg [13:0] clk_shifter = 14'b0; // Second stage
-    always @(posedge clk_div)
-    begin
-        clk_shifter <= clk_shifter + 1'b1;
-    end
-    
     assign clk_shift = clk_shifter[latched_shift_clock_freq];
     
     reg [14:0] lfsr = {15{1'b1}};
@@ -67,26 +67,36 @@
         (counter_width == 0) ? ({(lfsr[0] ^ lfsr[1]), lfsr[14:1]}) :
                                ({8'b0, (lfsr[0] ^ lfsr[1]), lfsr[6:1]});
     
-    always@(posedge start)
+    wire clk_shift_posedge;
+    edgedet clk_shift_edgedet (
+        .clk(clk),
+        .i(clk_shift),
+        .o(clk_shift_posedge)
+    );
+
+    always @(posedge clk)
     begin
-        adjusted_freq_dividing_ratio <=
-                (freq_dividing_ratio == 3'b0) ? (5'd1) : ((freq_dividing_ratio * 4) - 1);
-        latched_shift_clock_freq <= shift_clock_freq;
+        if (start_posedge) begin
+            adjusted_freq_dividing_ratio <=
+                    (freq_dividing_ratio == 3'b0) ? (6'd1) : ((freq_dividing_ratio * 8) - 1);
+            latched_shift_clock_freq <= shift_clock_freq;
+        end
     end
     
-    always@(posedge clk_shift, posedge start)
+    always @(posedge clk)
     begin
-        if (start) begin
+        if (start_posedge) begin
             lfsr <= {15{1'b1}};
         end
-        else begin
+        else if (clk_shift_posedge) begin
             lfsr <= lfsr_next;
-        end    
+        end
     end
     
     sound_vol_env sound_vol_env(
+        .clk(clk),
         .clk_vol_env(clk_vol_env),
-        .start(start),
+        .start(start_posedge),
         .initial_volume(initial_volume),
         .envelope_increasing(envelope_increasing),
         .num_envelope_sweeps(num_envelope_sweeps),
@@ -94,9 +104,10 @@
     );
 
     sound_length_ctr #(6) sound_length_ctr(
+        .clk(clk),
         .rst(rst),
         .clk_length_ctr(clk_length_ctr),
-        .start(start),
+        .start(start_posedge),
         .single(single),
         .length(length),
         .enable(enable)
diff --git a/verilog/rtl/sound_square.v b/verilog/rtl/sound_square.v
index 8f85838..2f1660b 100644
--- a/verilog/rtl/sound_square.v
+++ b/verilog/rtl/sound_square.v
@@ -22,7 +22,7 @@
 //   the design I am using here.
 //////////////////////////////////////////////////////////////////////////////////
 module sound_square(
-    input rst, // Async reset
+    input rst, // Sync reset
     input clk, // CPU Clock
     input clk_length_ctr, // Length control clock
     input clk_vol_env, // Volume Envelope clock
@@ -42,6 +42,12 @@
     output [3:0] level, // Sound output
     output enable // Internal enable flag
     );
+    wire start_posedge;
+    edgedet start_edgedet (
+        .clk(clk),
+        .i(start),
+        .o(start_posedge)
+    );
     
     //Sweep: X(t) = X(t-1) +/- X(t-1)/2^n
     
@@ -52,12 +58,12 @@
     wire [3:0] target_vol;
     reg [2:0] sweep_left; // Number of sweeps need to be done
 
-    always @(posedge clk_freq_div, posedge start)
+    always @(posedge clk)
     begin
-        if (start) begin
+        if (start_posedge) begin
             divider <= target_freq;
         end
-        else begin
+        else if (clk_freq_div) begin
             if (divider == 11'd2047) begin
                 octo_freq_out <= ~octo_freq_out;
                 divider <= target_freq;
@@ -82,14 +88,14 @@
            
     // Frequency Sweep
     reg overflow;
-    always @(posedge clk_sweep, posedge start)
+    always @(posedge clk)
     begin
-        if (start) begin
+        if (start_posedge) begin
             target_freq <= frequency;
             sweep_left <= sweep_time;
             overflow <= 0;
         end
-        else begin
+        else if (clk_sweep) begin
             if (sweep_left != 3'b0) begin
                 sweep_left <= sweep_left - 1'b1;
                 if (sweep_decreasing) 
@@ -102,14 +108,11 @@
             end
         end
     end 
-    /*always@(posedge start)
-    begin
-        target_freq <= frequency;
-    end*/
 
     sound_vol_env sound_vol_env(
+        .clk(clk),
         .clk_vol_env(clk_vol_env),
-        .start(start),
+        .start(start_posedge),
         .initial_volume(initial_volume),
         .envelope_increasing(envelope_increasing),
         .num_envelope_sweeps(num_envelope_sweeps),
@@ -119,9 +122,10 @@
     wire enable_length;
 
     sound_length_ctr #(6) sound_length_ctr(
+        .clk(clk),
         .rst(rst),
         .clk_length_ctr(clk_length_ctr),
-        .start(start),
+        .start(start_posedge),
         .single(single),
         .length(length),
         .enable(enable_length)
diff --git a/verilog/rtl/sound_vol_env.v b/verilog/rtl/sound_vol_env.v
index 81cc07f..9aa5ec1 100644
--- a/verilog/rtl/sound_vol_env.v
+++ b/verilog/rtl/sound_vol_env.v
@@ -14,6 +14,7 @@
 //
 //////////////////////////////////////////////////////////////////////////////////
 module sound_vol_env(
+    input clk,
     input clk_vol_env,
     input start,
     input [3:0] initial_volume,
@@ -26,13 +27,13 @@
     wire enve_enabled = (num_envelope_sweeps == 3'd0) ? 0 : 1;
     
     // Volume Envelope
-    always @(posedge clk_vol_env, posedge start)
+    always @(posedge clk)
     begin
         if (start) begin
             target_vol <= initial_volume;
             enve_left <= num_envelope_sweeps;
         end
-        else begin
+        else if (clk_vol_env) begin
             if (enve_left != 3'b0) begin
                 enve_left <= enve_left - 1'b1;
             end
diff --git a/verilog/rtl/sound_wave.v b/verilog/rtl/sound_wave.v
index 22bd632..c8d8afa 100644
--- a/verilog/rtl/sound_wave.v
+++ b/verilog/rtl/sound_wave.v
@@ -29,9 +29,14 @@
     output [3:0] level,
     output enable
     );
-    
+    wire start_posedge;
+    edgedet start_edgedet (
+        .clk(clk),
+        .i(start),
+        .o(start_posedge)
+    );
+
     // Freq = 64kHz / (2048 - frequency)
-    // Why????????
     
     wire [3:0] current_sample;
     
@@ -40,44 +45,29 @@
     assign wave_a[3:0] = current_pointer[4:1];
     assign current_sample[3:0] = (current_pointer[0]) ?
         (wave_d[3:0]) : (wave_d[7:4]);
-    
-    wire clk_wave_base = clk; // base clock
-    /*clk_div #(.WIDTH(6), .DIV(32)) freq_div(
-        .i(clk),
-        .o(clk_wave_base)
-    );*/
-    
-    
-    reg clk_pointer_inc = 1'b0; // Clock for pointer to increment
-    reg [10:0] divider = 11'b0;
-    always @(posedge clk_wave_base, posedge start)
+
+    reg [11:0] divider = 12'b0;
+    always @(posedge clk)
     begin
-        if (start) begin
-            divider <= frequency;
+        if (start_posedge) begin
+            divider <= frequency * 2;
+            current_pointer <= 5'd0;
         end
         else begin
-            if (divider == 11'd2047) begin
-                clk_pointer_inc <= ~clk_pointer_inc;
-                divider <= frequency;
+            if (divider == 12'd4095) begin
+                if (on) begin
+                    current_pointer <= current_pointer + 1'b1;
+                end
+                divider <= frequency * 2;
             end
             else begin
                 divider <= divider + 1'b1;
             end
         end
     end
-        
-    always @(posedge clk_pointer_inc, posedge start)
-    begin
-        if (start) begin
-            current_pointer <= 5'b0;
-        end
-        else begin
-            if (on)
-                current_pointer <= current_pointer + 1'b1;
-        end
-    end
     
     sound_length_ctr #(8) sound_length_ctr(
+        .clk(clk),
         .rst(rst),
         .clk_length_ctr(clk_length_ctr),
         .start(start),