diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
index 14b9bb4..8ace564 100644
--- a/openlane/user_proj_example/config.json
+++ b/openlane/user_proj_example/config.json
@@ -1,9 +1,6 @@
 {
     "DESIGN_NAME": "user_proj_example",
-    "VERILOG_FILES": "dir::verilog/rtl/defines.v dir::verilog/rtl/user_proj_example.v",
-
-
-
+    "VERILOG_FILES": ["dir::verilog/rtl/defines.v","dir::verilog/rtl/user_proj_example.v"],
     "CLOCK_PERIOD": 10,
     "CLOCK_PORT": "wb_clk_i",
     "CLOCK_NET": "counter.clk",
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
new file mode 100644
index 0000000..fa584e8
--- /dev/null
+++ b/openlane/user_project_wrapper/config.json
@@ -0,0 +1,39 @@
+{
+    "DESIGN_NAME": "user_project_wrapper",
+    "VERILOG_FILES": ["dir::verilog/rtl/defines.v","dir::verilog/rtl/user_project_wrapper.v"],
+    "CLOCK_PERIOD": 10,
+    "CLOCK_PORT": "wb_clk_i",
+    "CLOCK_NET": "counter.clk",
+    "FP_SIZING": "absolute",
+    "DIE_AREA": "0 0 900 600",
+    "FP_PIN_ORDER_CFG": "pin_order.cfg",
+    "PL_BASIC_PLACEMENT": 0,
+    "PL_TARGET_DENSITY": 0.55,
+    "RT_MAX_LAYER": "{met4}",
+    "pdk::sky130*": {
+        "FP_CORE_UTIL": 45,
+        "scl::sky130_fd_sc_hd": {
+            "CLOCK_PERIOD": 10
+        },
+        "scl::sky130_fd_sc_hdll": {
+            "CLOCK_PERIOD": 10
+        },
+        "scl::sky130_fd_sc_hs": {
+            "CLOCK_PERIOD": 8
+        },
+        "scl::sky130_fd_sc_ls": {
+            "CLOCK_PERIOD": 10,
+            "SYNTH_MAX_FANOUT": 5
+        },
+        "scl::sky130_fd_sc_ms": {
+            "CLOCK_PERIOD": 10
+        }
+    },
+    "pdk::gf180mcuC": {
+        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
+        "CLOCK_PERIOD": 24.0,
+        "FP_CORE_UTIL": 40,
+        "SYNTH_MAX_FANOUT": 4,
+        "PL_TARGET_DENSITY": 0.45
+    }
+}
\ No newline at end of file