)]}'
{
  "commit": "96ec33565961055b2cdeabdf0e09bacbfb543373",
  "tree": "00874e4315a8642b1e7887d6a38c0a4550a6e82c",
  "parents": [
    "ea993b96f1d000dac820f2a6179295b225fc9b35"
  ],
  "author": {
    "name": "Wenting Zhang",
    "email": "zephray@outlook.com",
    "time": "Sat Nov 26 11:36:01 2022 -0500"
  },
  "committer": {
    "name": "Wenting Zhang",
    "email": "zephray@outlook.com",
    "time": "Sat Nov 26 11:36:01 2022 -0500"
  },
  "message": "Fix CPU/DMA OAM access\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b437e098d74183b77870a93769aaa127e8073abd",
      "old_mode": 33188,
      "old_path": "verilog/rtl/boy.v",
      "new_id": "819131da5b825d7ec9ee0fd4768c15aa679bbff0",
      "new_mode": 33188,
      "new_path": "verilog/rtl/boy.v"
    },
    {
      "type": "modify",
      "old_id": "d384a5339b8470b4d34e29802f3ec54650b07591",
      "old_mode": 33188,
      "old_path": "verilog/rtl/dma.v",
      "new_id": "2b0d924e010107f20c3fab3c766080934a37c38b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/dma.v"
    }
  ]
}