|author||Wenting Zhang <email@example.com>||Mon Dec 05 20:48:26 2022 -0500|
|committer||Wenting Zhang <firstname.lastname@example.org>||Mon Dec 05 20:48:26 2022 -0500|
Uses VerilogBoy design from https://github.com/zephray/VerilogBoy.
VerilogBoy is a GameBoy-compatible system design in synthesizable Verilog RTL. The submission for GFMPW0 includes the following components:
To form a complete GB system, users need to provide the following additional components:
The simtop.v maybe used as a reference on external components required.
A Verilator-based testbench is provided in verilog/sim.
The implementation has 43% ultilization of a 1.5mm x 1.5 mm core area. The Fmax is around 20MHz at typical corner, 3.3V with no hold violation. The design is supposed to run up to 4MHz at 5V.
Unless otherwise stated, HDL codes are licensed under OHDL 1.0, and software codes are licensed under MIT.