diff --git a/Makefile b/Makefile
index 7072c14..b7ca8c1 100644
--- a/Makefile
+++ b/Makefile
@@ -29,7 +29,7 @@
 CARAVEL_LITE?=1
 
 # PDK switch varient
-export PDK_VARIENT?=sky130B
+export PDK?=sky130B
 
 MPW_TAG ?= mpw-5c
 
@@ -86,7 +86,7 @@
 		-e CARAVEL_ROOT=${CARAVEL_ROOT} \
 		-e TOOLS=/opt/riscv32i \
 		-e DESIGNS=$(TARGET_PATH) \
-		-e PDK_VARIENT=$(PDK_VARIENT) \
+		-e PDK=$(PDK) \
 		-e CORE_VERILOG_PATH=$(TARGET_PATH)/mgmt_core_wrapper/verilog \
 		-e GCC_PREFIX=riscv32-unknown-elf \
 		-e MCW_ROOT=$(MCW_ROOT) \
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index ca5feba..b216984 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -13,7 +13,7 @@
 # limitations under the License.
 # SPDX-License-Identifier: Apache-2.0
 
-set ::env(PDK) $::env(PDK_VARIENT)
+set ::env(PDK) $::env(PDK)
 set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
 
 set script_dir [file dirname [file normalize [info script]]]
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 6c723b4..f0d44fa 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -16,7 +16,7 @@
 # Base Configurations. Don't Touch
 # section begin
 
-set ::env(PDK) $::env(PDK_VARIENT)
+set ::env(PDK) $::env(PDK)
 set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
 
 # YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS