commit ef36958736bf4f7acf5b05cd48bbd79f39e8c444
author Ryan Price <91754608+RyanMPrice@users.noreply.github.com> Wed Nov 16 14:50:57 2022 -0700
committer Ryan Price <91754608+RyanMPrice@users.noreply.github.com> Wed Nov 16 14:50:57 2022 -0700
tree 72ca5fbf36ed99b1909568f21538037f9b5dfabc
parent 938c19df78af7ffadedbbd383a78f470064ef526

Fixed scb

verilog/rtl/Minx16/scb.v

diff --git a/verilog/rtl/Minx16/scb.v b/verilog/rtl/Minx16/scb.v
index a652719..07564c8 100644
--- a/verilog/rtl/Minx16/scb.v
+++ b/verilog/rtl/Minx16/scb.v
@@ -80,12 +80,12 @@
 endmodule
 
 module dfsimpleram #(
-  parameter A = 8
+  parameter M = 8
 , parameter D = 8
 ) (
   input              CLK
 
-, input      [A-1:0] A
+, input      [M-1:0] A
 , input      [D-1:0] D
 , output reg [D-1:0] Q
 , input              CEN
@@ -93,7 +93,7 @@
 , input      [D-1:0] WEN
 );
   
-  reg [D-1:0] mem [2**A-1:0];
+  reg [D-1:0] mem [(2**M)-1:0];
   
   always @ (posedge clk)
     if( cen == 1'b0 )