| module DiffDigota (INmb, |
| INpb, |
| OUTm, |
| OUTp, |
| cmnmos, |
| cmpmos, |
| oe, |
| omnmos, |
| ompmos, |
| opnmos, |
| oppmos, |
| vdd, |
| vss); |
| input INmb; |
| input INpb; |
| input OUTm; |
| input OUTp; |
| output cmnmos; |
| output cmpmos; |
| input oe; |
| output omnmos; |
| output ompmos; |
| output opnmos; |
| output oppmos; |
| input vdd; |
| input vss; |
| |
| wire _00_; |
| wire _01_; |
| wire _02_; |
| wire _03_; |
| wire _04_; |
| wire _05_; |
| wire _06_; |
| wire net1; |
| wire net2; |
| wire net3; |
| wire net4; |
| wire net5; |
| wire net6; |
| wire net7; |
| wire net8; |
| wire net9; |
| wire net10; |
| wire net11; |
| |
| gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _07_ (.I(net1), |
| .Z(_00_), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _08_ (.I(net2), |
| .Z(_01_), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__nand3_1 _09_ (.A1(net5), |
| .A2(_00_), |
| .A3(_01_), |
| .ZN(net7), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _10_ (.I(net5), |
| .ZN(_02_), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__nor3_1 _11_ (.A1(_02_), |
| .A2(_00_), |
| .A3(_01_), |
| .ZN(net6), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__oai21_1 _12_ (.A1(net4), |
| .A2(net3), |
| .B(net1), |
| .ZN(_03_), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _13_ (.A1(_01_), |
| .A2(_03_), |
| .B(_02_), |
| .ZN(net9), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _14_ (.A1(net4), |
| .A2(net3), |
| .B(net1), |
| .ZN(_04_), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__nor3_1 _15_ (.A1(_02_), |
| .A2(_01_), |
| .A3(_04_), |
| .ZN(net8), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__oai21_1 _16_ (.A1(net4), |
| .A2(net3), |
| .B(net2), |
| .ZN(_05_), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__nand3_1 _17_ (.A1(net5), |
| .A2(_00_), |
| .A3(_05_), |
| .ZN(net11), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _18_ (.A1(net4), |
| .A2(net3), |
| .B(net2), |
| .ZN(_06_), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__oai21_1 _19_ (.A1(_00_), |
| .A2(_06_), |
| .B(net5), |
| .ZN(net10), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_0 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_1 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_2 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_3 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_4 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_5 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_6 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_7 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_8 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_9 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_10 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_11 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_12 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_13 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_14 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_15 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_16 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_17 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_18 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_19 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_20 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_21 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_22 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__endcap PHY_23 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_24 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_25 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_26 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_27 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_28 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_29 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_30 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_31 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_32 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_33 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_34 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_35 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_36 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_37 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_38 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_39 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_40 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_41 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_42 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_43 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__filltie TAP_44 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__dlyb_1 input1 (.I(INmb), |
| .Z(net1), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__dlyb_1 input2 (.I(INpb), |
| .Z(net2), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 input3 (.I(OUTm), |
| .Z(net3), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 input4 (.I(OUTp), |
| .Z(net4), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 input5 (.I(oe), |
| .Z(net5), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 output6 (.I(net6), |
| .Z(cmnmos), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 output7 (.I(net7), |
| .Z(cmpmos), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 output8 (.I(net8), |
| .Z(omnmos), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 output9 (.I(net9), |
| .Z(ompmos), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 output10 (.I(net10), |
| .Z(opnmos), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 output11 (.I(net11), |
| .Z(oppmos), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_input1_I (.I(INmb), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_input2_I (.I(INpb), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_input3_I (.I(OUTm), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_input4_I (.I(OUTp), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_input5_I (.I(oe), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__19__B (.I(net5), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__17__A1 (.I(net5), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__10__I (.I(net5), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__09__A1 (.I(net5), |
| .VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_2 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_20 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_26 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_34 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_37 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_54 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_58 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_66 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_0_72 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_80 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_90 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_98 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_102 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_104 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_0_107 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_115 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_1_2 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_1_17 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_1_21 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_1_29 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_1_39 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_1_49 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_1_59 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_1_67 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_1_73 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_1_89 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_1_92 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_1_108 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_2_2 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_2_5 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_2_21 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_2_32 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_2_34 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_2_37 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_2_49 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_2_81 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_2_97 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_2_105 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_2_108 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_3_2 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_3_36 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_3_40 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_3_48 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_3_52 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_3_54 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_3_59 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_3_63 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_3_73 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_3_105 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_3_113 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_3_115 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_4_2 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_4_18 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_4_26 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_4_34 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_4_37 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_4_47 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_4_51 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_4_83 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_4_99 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_4_103 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_4_105 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_4_108 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_5_2 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_5_18 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_5_26 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_5_36 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_5_44 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_5_46 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_5_55 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_5_65 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_5_69 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_5_73 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_5_105 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_5_113 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_5_115 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_6_2 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_6_34 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_6_37 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_6_101 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_6_105 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_6_108 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_7_2 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_7_66 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_7_70 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_7_73 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_7_105 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_7_113 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_7_115 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_8_2 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_8_34 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_8_37 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_8_101 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_8_105 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_8_108 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_9_2 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_9_66 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_9_70 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_9_73 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_9_105 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_9_113 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_9_115 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_10_2 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_10_17 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_33 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_10_37 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_10_69 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_10_77 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_81 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_10_83 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_10_98 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_10_108 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_11_2 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_11_6 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_11_21 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_11_29 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_11_33 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_11_37 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_11_41 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_11_56 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_11_64 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_11_68 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_11_72 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_11_76 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_11_91 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_11_99 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_11_103 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_11_107 (.VDD(vdd), |
| .VSS(vss)); |
| gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_11_115 (.VDD(vdd), |
| .VSS(vss)); |
| endmodule |
