commit a549ca40a4f9314262b6966ccc4508e6fcdd6e33
author Ryan Price <91754608+RyanMPrice@users.noreply.github.com> Wed Nov 16 14:52:23 2022 -0700
committer Ryan Price <91754608+RyanMPrice@users.noreply.github.com> Wed Nov 16 14:52:23 2022 -0700
tree e61026f681335c10016b80a7b8469e71294de721
parent ef36958736bf4f7acf5b05cd48bbd79f39e8c444

Update scb.v

verilog/rtl/Minx16/scb.v

diff --git a/verilog/rtl/Minx16/scb.v b/verilog/rtl/Minx16/scb.v
index 07564c8..598a778 100644
--- a/verilog/rtl/Minx16/scb.v
+++ b/verilog/rtl/Minx16/scb.v
@@ -81,19 +81,19 @@
 
 module dfsimpleram #(
   parameter M = 8
-, parameter D = 8
+, parameter L = 8
 ) (
   input              CLK
 
 , input      [M-1:0] A
-, input      [D-1:0] D
-, output reg [D-1:0] Q
+, input      [L-1:0] D
+, output reg [L-1:0] Q
 , input              CEN
 , input              GWEN
-, input      [D-1:0] WEN
+, input      [L-1:0] WEN
 );
   
-  reg [D-1:0] mem [(2**M)-1:0];
+  reg [L-1:0] mem [(2**M)-1:0];
   
   always @ (posedge clk)
     if( cen == 1'b0 )