Merged Lanes
Merged Minx16 into UserProjectExample openlane scripts for CPU build flow. Simulated Dflop mem for ram macros. Macro ram to be included in near future
diff --git a/openlane/user_Minx16/config.json b/openlane/user_Minx16/config.json
deleted file mode 100644
index 055b66d..0000000
--- a/openlane/user_Minx16/config.json
+++ /dev/null
@@ -1,49 +0,0 @@
-{
- "DESIGN_NAME": "Minx16Top",
- "DESIGN_IS_CORE": 0,
- "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/Minx16/*"],
- "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
- "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/gf180mcu_fd_ip_sram/gf180mcu_fd_ip_sram__sram512x8m8wm1.v"],
- "EXTRA_LEFS": "dir::../../lef/gf180mcu_fd_ip_sram__sram512x8m8wm1.lef",
- "EXTRA_GDS_FILES": "dir::../../gds/gf180mcu_fd_ip_sram__sram512x8m8wm1.gds",
- "CLOCK_PERIOD": 100,
- "CLOCK_PORT": "clk_i",
- "CLOCK_NET": "Minx16Top.clk_i",
- "FP_SIZING": "absolute",
- "DIE_AREA": "0 0 2000 2000",
- "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
- "PL_BASIC_PLACEMENT": 0,
- "PL_TARGET_DENSITY": 0.50,
- "VDD_NETS": ["vccd1"],
- "GND_NETS": ["vssd1"],
- "DIODE_INSERTION_STRATEGY": 4,
- "RUN_CVC": 1,
- "pdk::sky130*": {
- "FP_CORE_UTIL": 45,
- "RT_MAX_LAYER": "met4",
- "scl::sky130_fd_sc_hd": {
- "CLOCK_PERIOD": 10
- },
- "scl::sky130_fd_sc_hdll": {
- "CLOCK_PERIOD": 10
- },
- "scl::sky130_fd_sc_hs": {
- "CLOCK_PERIOD": 8
- },
- "scl::sky130_fd_sc_ls": {
- "CLOCK_PERIOD": 10,
- "SYNTH_MAX_FANOUT": 5
- },
- "scl::sky130_fd_sc_ms": {
- "CLOCK_PERIOD": 10
- }
- },
- "pdk::gf180mcuC": {
- "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
- "CLOCK_PERIOD": 50.0,
- "FP_CORE_UTIL": 40,
- "RT_MAX_LAYER": "Metal4",
- "SYNTH_MAX_FANOUT": 4,
- "PL_TARGET_DENSITY": 0.45
- }
-}
\ No newline at end of file
diff --git a/openlane/user_Minx16/macro.cfg b/openlane/user_Minx16/macro.cfg
deleted file mode 100644
index d1567a8..0000000
--- a/openlane/user_Minx16/macro.cfg
+++ /dev/null
@@ -1,4 +0,0 @@
-oddMemHigh 250.0000 250.00 N
-oddMemLow 250.0000 1000.00 N
-evenMemHigh 1000.0000 250.00 N
-evenMemLow 1000.0000 1000.00 N
diff --git a/openlane/user_Minx16/pin_order.cfg b/openlane/user_Minx16/pin_order.cfg
deleted file mode 100644
index 603257a..0000000
--- a/openlane/user_Minx16/pin_order.cfg
+++ /dev/null
@@ -1,76 +0,0 @@
-#BUS_SORT
-
-#N
-dbus_ADBus_i\[7\]
-dbus_ADBus_o\[7\]
-dbus_ADBus_e\[7\]
-dbus_ADBus_i\[6\]
-dbus_ADBus_o\[6\]
-dbus_ADBus_e\[6\]
-dbus_ADBus_i\[5\]
-dbus_ADBus_o\[5\]
-dbus_ADBus_e\[5\]
-dbus_ADBus_i\[4\]
-dbus_ADBus_o\[4\]
-dbus_ADBus_e\[4\]
-dbus_ADBus_i\[3\]
-dbus_ADBus_o\[3\]
-dbus_ADBus_e\[3\]
-dbus_ADBus_i\[2\]
-dbus_ADBus_o\[2\]
-dbus_ADBus_e\[2\]
-dbus_ADBus_i\[1\]
-dbus_ADBus_o\[1\]
-dbus_ADBus_e\[1\]
-dbus_ADBus_i\[0\]
-dbus_ADBus_o\[0\]
-dbus_ADBus_e\[0\]
-dbus_ale_o
-dbus_ale_e
-
-#W
-dbus_dle_o
-dbus_dle_e
-dbus_stb_o\[1\]
-dbus_stb_e\[1\]
-dbus_stb_o\[0\]
-dbus_stb_e\[0\]
-dbus_rd_o
-dbus_rd_e
-dbus_wr_o
-dbus_wr_e
-dbus_rdy_i
-dbus_req_i
-dbus_ack_o
-intr_i
-inta_o
-
-#E
-dbus_ADBus_i\[8\]
-dbus_ADBus_o\[8\]
-dbus_ADBus_e\[8\]
-dbus_ADBus_i\[9\]
-dbus_ADBus_o\[9\]
-dbus_ADBus_e\[9\]
-dbus_ADBus_i\[10\]
-dbus_ADBus_o\[10\]
-dbus_ADBus_e\[10\]
-dbus_ADBus_i\[11\]
-dbus_ADBus_o\[11\]
-dbus_ADBus_e\[11\]
-dbus_ADBus_i\[12\]
-dbus_ADBus_o\[12\]
-dbus_ADBus_e\[12\]
-dbus_ADBus_i\[13\]
-dbus_ADBus_o\[13\]
-dbus_ADBus_e\[13\]
-dbus_ADBus_i\[14\]
-dbus_ADBus_o\[14\]
-dbus_ADBus_e\[14\]
-dbus_ADBus_i\[15\]
-dbus_ADBus_o\[15\]
-dbus_ADBus_e\[15\]
-rst_i
-clk_i
-nmir_i
-nmia_o
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
index 370d74c..dc0104c 100644
--- a/openlane/user_proj_example/config.json
+++ b/openlane/user_proj_example/config.json
@@ -1,12 +1,12 @@
{
"DESIGN_NAME": "user_proj_example",
"DESIGN_IS_CORE": 0,
- "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
- "CLOCK_PERIOD": 10,
- "CLOCK_PORT": "wb_clk_i",
- "CLOCK_NET": "counter.clk",
+ "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v", "dir::../../verilog/rtl/Minx16/*"],
+ "CLOCK_PERIOD": 50,
+ "CLOCK_PORT": "wb_clk_i, clk_i",
+ "CLOCK_NET": "counter.clk, cpu16.clk_i",
"FP_SIZING": "absolute",
- "DIE_AREA": "0 0 900 600",
+ "DIE_AREA": "0 0 2300 2300",
"FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
"PL_BASIC_PLACEMENT": 0,
"PL_TARGET_DENSITY": 0.55,
@@ -36,7 +36,7 @@
},
"pdk::gf180mcuC": {
"STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
- "CLOCK_PERIOD": 24.0,
+ "CLOCK_PERIOD": 50.0,
"FP_CORE_UTIL": 40,
"RT_MAX_LAYER": "Metal4",
"SYNTH_MAX_FANOUT": 4,
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/user_proj_example/pin_order.cfg
index 2fda806..c6f0dc8 100644
--- a/openlane/user_proj_example/pin_order.cfg
+++ b/openlane/user_proj_example/pin_order.cfg
@@ -7,4 +7,124 @@
irq.*
#N
-io_.*
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+
+#W
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+
+#E
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]
+io_in\[38\]
+io_out\[38\]
+io_oeb\[38\]
diff --git a/verilog/rtl/Minx16/scb.v b/verilog/rtl/Minx16/scb.v
index 0327be0..a652719 100644
--- a/verilog/rtl/Minx16/scb.v
+++ b/verilog/rtl/Minx16/scb.v
@@ -1,4 +1,5 @@
-//Design for 1024x16 or 2kb of onboard memory scratchpad
+//Design for 0x0800 of onboard memory scratchpad
+//
module SCB_memory (
input clk_i
, input rst_i
@@ -32,7 +33,8 @@
assign scb_rdy_o = 1'b1;
assign scb_Data_o = (highSelect) ? dboh :dbol;
- gf180mcu_fd_ip_sram__sram512x8m8wm1 oddMemLow (
+ //gf180mcu_fd_ip_sram__sram512x8m8wm1 oddMemLow (
+ dfsimpleram #(9, 8) oddMemLow (
.CLK (clk_i)
, .CEN (~(oddSelect & lowSelect))
, .GWEN(~scb_ce_i | scb_wr_i)
@@ -42,7 +44,8 @@
, .Q (dbolo)
);
- gf180mcu_fd_ip_sram__sram512x8m8wm1 oddMemHigh (
+ //gf180mcu_fd_ip_sram__sram512x8m8wm1 oddMemHigh (
+ dfsimpleram #(9, 8) oddMemHigh (
.CLK (clk_i)
, .CEN (~(oddSelect & highSelect))
, .GWEN(~scb_ce_i | scb_wr_i)
@@ -52,7 +55,8 @@
, .Q (dbohi)
);
- gf180mcu_fd_ip_sram__sram512x8m8wm1 evenMemLow (
+ //gf180mcu_fd_ip_sram__sram512x8m8wm1 evenMemLow (
+ dfsimpleram #(9, 8) evenMemLow (
.CLK (clk_i)
, .CEN (~(evenSelect & lowSelect))
, .GWEN(~scb_ce_i | scb_wr_i)
@@ -62,7 +66,8 @@
, .Q (dbelo)
);
- gf180mcu_fd_ip_sram__sram512x8m8wm1 evenMemHigh(
+ //gf180mcu_fd_ip_sram__sram512x8m8wm1 evenMemHigh (
+ dfsimpleram #(9, 8) evenMemHigh(
.CLK (clk_i)
, .CEN (~(evenSelect & highSelect))
, .GWEN(~scb_ce_i | scb_wr_i)
@@ -74,3 +79,28 @@
endmodule
+module dfsimpleram #(
+ parameter A = 8
+, parameter D = 8
+) (
+ input CLK
+
+, input [A-1:0] A
+, input [D-1:0] D
+, output reg [D-1:0] Q
+, input CEN
+, input GWEN
+, input [D-1:0] WEN
+);
+
+ reg [D-1:0] mem [2**A-1:0];
+
+ always @ (posedge clk)
+ if( cen == 1'b0 )
+ dbo = mem[addr];
+
+ always @ (posedge clk)
+ if( gwen == 1'b0 && cen == 1'b0 )
+ mem[addr] = dbi;
+
+endmodule
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 95654f8..f07e702 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -104,9 +104,10 @@
wire [`MPRJ_IO_PADS-1:0] io_oeb;
wire [1:0] mode = io_in[37:36];
+ wire clk_i = io_in [33];
Minx16Top cpu16 (
- .clk_i (io_in [33])
+ .clk_i (clk_i)
, .rst_i (io_in [32])
, .dbus_ADBus_i(io_in [31:16])
@@ -135,37 +136,6 @@
endmodule
-(* blackbox *)
-module Minx16Top (
- input clk_i
-, input rst_i
-
-, input [15:0] dbus_ADBus_i
-, output wire [15:0] dbus_ADBus_o
-, output wire [15:0] dbus_ADBus_e
-, output wire dbus_ale_o
-, output wire dbus_ale_e
-, output wire dbus_dle_o
-, output wire dbus_dle_e
-, output wire [ 1:0] dbus_stb_o
-, output wire [ 1:0] dbus_stb_e
-, output wire dbus_rd_o
-, output wire dbus_rd_e
-, output wire dbus_wr_o
-, output wire dbus_wr_e
-, input dbus_rdy_i
-
-, input dbus_req_i
-, output wire dbus_ack_o
-
-, input intr_i
-, output wire inta_o
-, input nmir_i
-, output wire nmia_o
-);
-
-endmodule
-
module counter #(
parameter BITS = 32
)(
