diff --git a/Makefile b/Makefile
index b8cb5c7..a343216 100644
--- a/Makefile
+++ b/Makefile
@@ -24,8 +24,8 @@
 CARAVEL_LITE?=1
 
 # PDK switch varient
-export PDK?=sky130B
-#export PDK?=gf180mcuC
+#export PDK?=sky130B
+export PDK?=gf180mcuC
 export PDKPATH?=$(PDK_ROOT)/$(PDK)
 
 
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/user_proj_example/pin_order.cfg
index 3244e18..5d76d53 100644
--- a/openlane/user_proj_example/pin_order.cfg
+++ b/openlane/user_proj_example/pin_order.cfg
@@ -34,7 +34,7 @@
 io_out\[15\]
 io_oeb\[15\]
 
-#W
+#E
 io_in\[14\]
 io_out\[14\]
 io_oeb\[14\]
@@ -81,7 +81,7 @@
 io_out\[0\]
 io_oeb\[0\]
 
-#E
+#W
 io_in\[24\]
 io_out\[24\]
 io_oeb\[24\]
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 31ab09b..da61268 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,5 +1,17 @@
 # Caravel user project includes
 -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
 -v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
-
+-v $(USER_PROJECT_VERILOG)/rtl/Minx16/Alu.v
+-v $(USER_PROJECT_VERILOG)/rtl/Minx16/Biu16.v
+-v $(USER_PROJECT_VERILOG)/rtl/Minx16/Controller.v
+-v $(USER_PROJECT_VERILOG)/rtl/Minx16/FlagRegister.v
+-v $(USER_PROJECT_VERILOG)/rtl/Minx16/Minx16Cpu.v
+-v $(USER_PROJECT_VERILOG)/rtl/Minx16/Minx16Top.v
+-v $(USER_PROJECT_VERILOG)/rtl/Minx16/MinxFoldedBus1616.v
+-v $(USER_PROJECT_VERILOG)/rtl/Minx16/ParametricRegister.v
+-v $(USER_PROJECT_VERILOG)/rtl/Minx16/ProgramCounter.v
+-v $(USER_PROJECT_VERILOG)/rtl/Minx16/RegFile.v
+-v $(USER_PROJECT_VERILOG)/rtl/Minx16/scb.v
+-v $(USER_PROJECT_VERILOG)/rtl/Minx16/StackPointer.v
+-v $(USER_PROJECT_VERILOG)/rtl/Minx16/trapAddr.v
  
\ No newline at end of file