diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 04421fe..95654f8 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -56,14 +56,55 @@
     output [2:0] irq
 );
   
+  wire clk;
+  wire rst;
+
+  wire [31:0] rdata; 
+  wire [31:0] wdata;
+  wire [BITS-1:0] count;
+
+  wire valid;
+  wire [3:0] wstrb;
+  wire [31:0] la_write;
+
+  // WB MI A
+  assign valid = wbs_cyc_i && wbs_stb_i; 
+  assign wstrb = wbs_sel_i & {4{wbs_we_i}};
+  assign wbs_dat_o = rdata;
+  assign wdata = wbs_dat_i;
+
+  // IRQ
+  assign irq = 3'b000;	// Unused
+
+  // LA
+  assign la_data_out = {{(127-BITS){1'b0}}, count};
+  // Assuming LA probes [63:32] are for controlling the count register  
+  assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
+  // Assuming LA probes [65:64] are for controlling the count clk & reset  
+  assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
+  assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
+  
+  counter #(
+    .BITS(BITS)
+  ) counter(
+    .clk(clk),
+    .reset(rst),
+    .ready(wbs_ack_o),
+    .valid(valid),
+    .rdata(rdata),
+    .wdata(wbs_dat_i),
+    .wstrb(wstrb),
+    .la_write(la_write),
+    .la_input(la_data_in[63:32]),
+    .count(count)
+  );
+  
   wire [`MPRJ_IO_PADS-1:0] io_in;
   wire [`MPRJ_IO_PADS-1:0] io_out;
   wire [`MPRJ_IO_PADS-1:0] io_oeb;
   
   wire [1:0] mode = io_in[37:36];
   
-  
-  
   Minx16Top cpu16 (
       .clk_i       (io_in [33])
     , .rst_i       (io_in [32])
@@ -125,4 +166,46 @@
 
 endmodule
 
+module counter #(
+    parameter BITS = 32
+)(
+    input clk,
+    input reset,
+    input valid,
+    input [3:0] wstrb,
+    input [BITS-1:0] wdata,
+    input [BITS-1:0] la_write,
+    input [BITS-1:0] la_input,
+    output ready,
+    output [BITS-1:0] rdata,
+    output [BITS-1:0] count
+);
+    reg ready;
+    reg [BITS-1:0] count;
+    reg [BITS-1:0] rdata;
+
+    always @(posedge clk) begin
+        if (reset) begin
+            count <= 0;
+            ready <= 0;
+        end else begin
+            ready <= 1'b0;
+            if (~|la_write) begin
+                count <= count + 1;
+            end
+            if (valid && !ready) begin
+                ready <= 1'b1;
+                rdata <= count;
+                if (wstrb[0]) count[7:0]   <= wdata[7:0];
+                if (wstrb[1]) count[15:8]  <= wdata[15:8];
+                if (wstrb[2]) count[23:16] <= wdata[23:16];
+                if (wstrb[3]) count[31:24] <= wdata[31:24];
+            end else if (|la_write) begin
+                count <= la_write & la_input;
+            end
+        end
+    end
+
+endmodule
+
 `default_nettype wire