diff --git a/.gitignore b/.gitignore
index 01ea346..1bc8313 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,3 +7,4 @@
 *.vcd
 *.gtkw
 caravel/
+mgmt_core_wrapper/
diff --git a/Makefile b/Makefile
index b8cb5c7..a343216 100644
--- a/Makefile
+++ b/Makefile
@@ -24,8 +24,8 @@
 CARAVEL_LITE?=1
 
 # PDK switch varient
-export PDK?=sky130B
-#export PDK?=gf180mcuC
+#export PDK?=sky130B
+export PDK?=gf180mcuC
 export PDKPATH?=$(PDK_ROOT)/$(PDK)
 
 
diff --git a/verilog/rtl/Minx16/scb.v b/verilog/rtl/Minx16/scb.v
index a541d67..c1f213f 100644
--- a/verilog/rtl/Minx16/scb.v
+++ b/verilog/rtl/Minx16/scb.v
@@ -45,15 +45,15 @@
   //);
   
   //gf180mcu_fd_ip_sram__sram512x8m8wm1 oddMemHigh (
-  dfsimpleram #(9, 8) oddMemHigh (
-    .CLK (clk_i)
-  , .CEN (~(oddSelect & highSelect))
-  , .GWEN(~scb_ce_i | scb_wr_i)
-  , .WEN (8'h00)
-  , .A   (addr)
-  , .D   (dbhi)
-  , .Q   (dbohi)
-  );
+  //dfsimpleram #(9, 8) oddMemHigh (
+  //  .CLK (clk_i)
+  //, .CEN (~(oddSelect & highSelect))
+  //, .GWEN(~scb_ce_i | scb_wr_i)
+  //, .WEN (8'h00)
+  //, .A   (addr)
+  //, .D   (dbhi)
+  //, .Q   (dbohi)
+  //);
   
   //gf180mcu_fd_ip_sram__sram512x8m8wm1 evenMemLow (
   //dfsimpleram #(9, 8) evenMemLow (
@@ -67,40 +67,40 @@
   //);
   
   //gf180mcu_fd_ip_sram__sram512x8m8wm1 evenMemHigh (
-  dfsimpleram #(9, 8) evenMemHigh(
-    .CLK (clk_i)
-  , .CEN (~(evenSelect & highSelect))
-  , .GWEN(~scb_ce_i | scb_wr_i)
-  , .WEN (8'h00)
-  , .A   (addr)
-  , .D   (dblo)
-  , .Q   (dbehi)
-  );
+  //dfsimpleram #(9, 8) evenMemHigh(
+  //  .CLK (clk_i)
+  //, .CEN (~(evenSelect & highSelect))
+  //, .GWEN(~scb_ce_i | scb_wr_i)
+  //, .WEN (8'h00)
+  //, .A   (addr)
+  //, .D   (dblo)
+  //, .Q   (dbehi)
+  //);
   
 endmodule
 
-module dfsimpleram #(
-  parameter M = 8
-, parameter L = 8
-) (
-  input              CLK
-
-, input      [M-1:0] A
-, input      [L-1:0] D
-, output reg [L-1:0] Q
-, input              CEN
-, input              GWEN
-, input      [L-1:0] WEN
-);
-  
-  reg [L-1:0] mem [(2**M)-1:0];
-  
-  always @ (posedge clk)
-    if( cen == 1'b0 )
-      dbo = mem[addr];
-  
-  always @ (posedge clk)
-    if( gwen == 1'b0 && cen == 1'b0 )
-      mem[addr] = dbi;
-  
-endmodule
+//module dfsimpleram #(
+//  parameter M = 8
+//, parameter L = 8
+//) (
+//  input              CLK
+//
+//, input      [M-1:0] A
+//, input      [L-1:0] D
+//, output reg [L-1:0] Q
+//, input              CEN
+//, input              GWEN
+//, input      [L-1:0] WEN
+//);
+//  
+//  reg [L-1:0] mem [(2**M)-1:0];
+//  
+//  always @ (posedge clk)
+//    if( cen == 1'b0 )
+//      dbo = mem[addr];
+//  
+//  always @ (posedge clk)
+//    if( gwen == 1'b0 && cen == 1'b0 )
+//      mem[addr] = dbi;
+//  
+//endmodule