diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
new file mode 100644
index 0000000..e6b0789
--- /dev/null
+++ b/openlane/user_proj_example/config.tcl
@@ -0,0 +1,98 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set ::env(PDK) "gf180mcuC"
+set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0"
+
+set ::env(DESIGN_NAME) user_proj_example
+
+set ::env(VERILOG_FILES) "\
+	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+	$::env(DESIGN_DIR)/../../verilog/rtl/Wishbone/WishboneSlave.v \
+	$::env(DESIGN_DIR)/../../verilog/rtl/user_proj_example.v"
+
+set ::env(DESIGN_IS_CORE) 0
+
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_NET) "clk"
+set ::env(CLOCK_PERIOD) "24.0"
+
+#set ::env(FP_SIZING) absolute
+#set ::env(DIE_AREA) "0 0 900 600"
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(PL_BASIC_PLACEMENT) 0
+set ::env(PL_TARGET_DENSITY) 0.50
+
+set ::env(FP_CORE_UTIL) 40
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+### Macro PDN Connections
+set ::env(FP_PDN_MACRO_HOOKS) "\
+	mprj vdd vss vdd vss"
+
+### Black-box verilog and views
+set ::env(VERILOG_FILES_BLACKBOX) "\
+	$::env(DESIGN_DIR)/../../verilog/rtl/defines.v \
+	$::env(DESIGN_DIR)/../../verilog/rtl/DIGOTA/DiffDigota.v \
+	$::env(DESIGN_DIR)/../../verilog/rtl/DIGOTA/DIGOTA.v \
+	$::env(DESIGN_DIR)/../../verilog/rtl/Clocks/clkgate.v \
+	$::env(DESIGN_DIR)/../../verilog/rtl/Clocks/clkmux2.v \
+	$::env(DESIGN_DIR)/../../verilog/rtl/WaveTbl/WavePWM.v"
+
+set ::env(EXTRA_LEFS) "\
+	$::env(DESIGN_DIR)/../../lef/DiffDigota.lef \
+	$::env(DESIGN_DIR)/../../lef/DIGOTA.lef \
+	$::env(DESIGN_DIR)/../../lef/clkgate.lef \
+	$::env(DESIGN_DIR)/../../lef/clkmux2.lef \
+	$::env(DESIGN_DIR)/../../lef/WavePWM.lef"
+
+set ::env(EXTRA_GDS_FILES) "\
+	$::env(DESIGN_DIR)/../../gds/DiffDigota.gds \
+	$::env(DESIGN_DIR)/../../gds/DIGOTA.gds \
+	$::env(DESIGN_DIR)/../../gds/clkgate.gds \
+	$::env(DESIGN_DIR)/../../gds/clkmux2.gds \
+	$::env(DESIGN_DIR)/../../gds/WavePWM.gds"
+
+set ::env(EXTRA_LIBS) "\
+    $::env(DESIGN_DIR)/../../lib/DiffDigota.lib \
+    $::env(DESIGN_DIR)/../../lib/DIGOTA.lib \
+    $::env(DESIGN_DIR)/../../lib/clkgate.lib\
+    $::env(DESIGN_DIR)/../../lib/clkmux2.lib\
+    $::env(DESIGN_DIR)/../../lib/WavePWM.lib"
+
+set ::env(RT_MAX_LAYER) {Metal4}
+
+# disable pdn check nodes becuase it hangs with multiple power domains.
+# any issue with pdn connections will be flagged with LVS so it is not a critical check.
+set ::env(FP_PDN_CHECK_NODES) 0
+
+
+# Maximum layer used for routing is metal 4.
+# This is because this macro will be inserted in a top level (user_project_wrapper) 
+# where the PDN is planned on metal 5. So, to avoid having shorts between routes
+# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4.  
+# 
+set ::env(RT_MAX_LAYER) {Metal4}
+
+# You can draw more power domains if you need to 
+set ::env(VDD_NETS) [list {vdd}]
+set ::env(GND_NETS) [list {vss}]
+
+set ::env(DIODE_INSERTION_STRATEGY) 4 
+# If you're going to use multiple power domains, then disable cvc run.
+set ::env(RUN_CVC) 1
\ No newline at end of file
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/user_proj_example/pin_order.cfg
new file mode 100644
index 0000000..c671b89
--- /dev/null
+++ b/openlane/user_proj_example/pin_order.cfg
@@ -0,0 +1,127 @@
+#BUS_SORT
+#NR
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
+
+#S
+wb_.*
+wbs_.*
+la_.*
+user_clock2
+user_irq.*
+
+#E
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+
+#WR
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index cf51caf..df19160 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -30,49 +30,32 @@
 ## Source Verilog Files
 set ::env(VERILOG_FILES) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$::env(CARAVEL_ROOT)/verilog/rtl/Wishbone/WishboneSlave.v \
 	$::env(DESIGN_DIR)/../../verilog/rtl/user_project_wrapper.v"
 
 ## Clock configurations
 set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "clk"
+set ::env(CLOCK_NET) "mprj.clk"
 
-set ::env(CLOCK_PERIOD) "24.0"
+set ::env(CLOCK_PERIOD) "10"
 
 ## Internal Macros
 ### Macro PDN Connections
 set ::env(FP_PDN_MACRO_HOOKS) "\
 	mprj vdd vss vdd vss"
 
+### Macro Placement
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
+
 ### Black-box verilog and views
 set ::env(VERILOG_FILES_BLACKBOX) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$::env(CARAVEL_ROOT)/verilog/rtl/DIGOTA/DiffDigota.v \
-	$::env(CARAVEL_ROOT)/verilog/rtl/DIGOTA/DIGOTA.v \
-	$::env(CARAVEL_ROOT)/verilog/rtl/Clocks/clkgate.v \
-	$::env(CARAVEL_ROOT)/verilog/rtl/Clocks/clkmux2.v \
-	$::env(CARAVEL_ROOT)/verilog/rtl/WaveTbl/WavePWM.v"
+	$::env(DESIGN_DIR)/../../verilog/rtl/user_proj_example.v"
 
 set ::env(EXTRA_LEFS) "\
-	$::env(CARAVEL_ROOT)/../../lef/DiffDigota.lef \
-	$::env(CARAVEL_ROOT)/../../lef/DIGOTA.lef \
-	$::env(CARAVEL_ROOT)/../../lef/clkgate.lef \
-	$::env(CARAVEL_ROOT)/../../lef/clkmux2.lef \
-	$::env(CARAVEL_ROOT)/../../lef/WavePWM.lef"
+	$::env(DESIGN_DIR)/../../lef/user_proj_example.lef"
 
 set ::env(EXTRA_GDS_FILES) "\
-	$::env(CARAVEL_ROOT)/../../gds/DiffDigota.gds \
-	$::env(CARAVEL_ROOT)/../../gds/DIGOTA.gds \
-	$::env(CARAVEL_ROOT)/../../gds/clkgate.gds \
-	$::env(CARAVEL_ROOT)/../../gds/clkmux2.gds \
-	$::env(CARAVEL_ROOT)/../../gds/WavePWM.gds"
-
-set ::env(EXTRA_LIBS) "\
-    $::env(DESIGN_DIR)/../../lib/DiffDigota.lib \
-    $::env(DESIGN_DIR)/../../lib/DIGOTA.lib \
-    $::env(CARAVEL_ROOT)/../../lib/clkgate.lib\
-    $::env(CARAVEL_ROOT)/../../lib/clkmux2.lib\
-    $::env(CARAVEL_ROOT)/../../lib/WavePWM.lib"
+	$::env(DESIGN_DIR)/../../gds/user_proj_example.gds"
 
 set ::env(RT_MAX_LAYER) {Metal4}
 
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
new file mode 100644
index 0000000..9bca792
--- /dev/null
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -0,0 +1 @@
+mprj 1000 1000 N
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
new file mode 100644
index 0000000..42c8145
--- /dev/null
+++ b/verilog/rtl/user_proj_example.v
@@ -0,0 +1,204 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_proj_example
+ *
+ * This is an example of a (trivially simple) user project,
+ * showing how the user project can connect to the logic
+ * analyzer, the wishbone bus, and the I/O pads.
+ *
+ * This project generates an integer count, which is output
+ * on the user area GPIO pads (digital output only).  The
+ * wishbone connection allows the project to be controlled
+ * (start and stop) from the management SoC program.
+ *
+ * See the testbenches in directory "mprj_counter" for the
+ * example programs that drive this user project.  The three
+ * testbenches are "io_ports", "la_test1", and "la_test2".
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_proj_example #(
+    parameter BITS = 32
+)(
+`ifdef USE_POWER_PINS
+    inout vdd,	// User area 1 1.8V supply
+    inout vss,	// User area 1 digital ground
+`endif
+
+    // Wishbone Slave ports (WB MI A)
+    input wb_clk_i,
+    input wb_rst_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
+    input wbs_we_i,
+    input [3:0] wbs_sel_i,
+    input [31:0] wbs_dat_i,
+    input [31:0] wbs_adr_i,
+    output wbs_ack_o,
+    output [31:0] wbs_dat_o,
+    
+    // Logic Analyzer Signals
+    input  [63:0] la_data_in,
+    output [63:0] la_data_out,
+    input  [63:0] la_oenb,
+
+    // IOs
+    input  [`MPRJ_IO_PADS-1:0] io_in,
+    output [`MPRJ_IO_PADS-1:0] io_out,
+    output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+    // IRQ
+    output [2:0] irq
+);
+  
+  WishboneSlave #(
+      .BASE_ADDRESS(32'h3000_0010)
+    , .CNTR_ADDRESS(32'h3000_0020)
+  ) wishSlave (
+      .wb_clk_i  (wb_clk_i)
+    , .wb_rst_i  (wb_rst_i)
+    , .wb_stb_i  (wbs_stb_i)
+    , .wb_cyc_i  (wbs_cyc_i)
+    , .wb_we_i   (wbs_we_i)
+    , .wb_sel_i  (wbs_sel_i)
+    , .wb_adr_i  (wbs_adr_i)
+    , .wb_dat_i  (wbs_dat_i)
+    , .wb_ack_o  (wbs_ack_o)
+    , .wb_stall_o()
+    , .wb_dat_o  (wbs_dat_o)
+    
+    //Signals out of slave to design
+    , .conf_in   (conf)
+    , .conf_out  (confo)
+    , .conf_udp  (confi)
+  );
+  
+  assign io_oeb[37]  = 1'b1;
+  wire clk = io_in[37];
+  assign io_oeb[36]  = 1'b1;
+  wire rst = io_in[36];
+  assign io_oeb[35]  = 1'b1;
+  wire den = io_in[35];
+  
+  wire confi;
+  reg [31:0] conf;
+  always @ (posedge clk or negedge rst)
+    if( rst == 1'b0 )
+      conf = 32'hffffffff;
+    else if( confi )
+      conf = confo;
+    else
+      conf = conf;
+  
+  assign io_oeb[5]  = 1'b1;
+  assign io_oeb[6]  = 1'b1;
+  assign io_oeb[7]  = 1'b0;
+  assign io_oeb[8]  = 1'b0;
+  assign io_oeb[9]  = 1'b0;
+  assign io_oeb[10] = 1'b0;
+  //Analog  2 pins : 2 in
+  //Digital 5 pins : 1 in, 4 out
+  DIGOTA duuta (
+      .INpb  (io_in    [5]) //Analog io_in[7]
+    , .INmb  (io_in    [6]) //Analog io_in[8]
+    , .oe    (den         ) //Digital
+    
+    , .opmos (io_out   [7]) //Digital
+    , .onmos (io_out   [8]) //Digital
+    , .cmpmos(io_out   [9]) //Digital
+    , .cmnmos(io_out   [10]) //Digital
+  );
+  
+  assign io_oeb[11] = 1'b1;
+  assign io_oeb[12] = 1'b1;
+  assign io_oeb[13] = 1'b1;
+  assign io_oeb[14] = 1'b1;
+  assign io_oeb[15] = 1'b0;
+  assign io_oeb[16] = 1'b0;
+  assign io_oeb[17] = 1'b0;
+  assign io_oeb[18] = 1'b0;
+  assign io_oeb[19] = 1'b0;
+  assign io_oeb[20] = 1'b0;
+  //Analog  2 pins : 2 in
+  //Digital 9 pins : 3 in, 6 out
+  DiffDigota duutb ( 
+    .INpb    (io_in    [11]) //Analog io_in[11]
+  , .INmb    (io_in    [12]) //Analog io_in[12]
+  , .OUTp    (io_in    [13]) //Digital
+  , .OUTm    (io_in    [14]) //Digital
+  , .oe      (enable       ) //Digital
+  
+  , .ompmos  (io_out   [15]) //Digital
+  , .omnmos  (io_out   [16]) //Digital
+  , .oppmos  (io_out   [17]) //Digital
+  , .opnmos  (io_out   [18]) //Digital
+  , .cmpmos  (io_out   [19]) //Digital
+  , .cmnmos  (io_out   [20]) //Digital
+  );
+  
+  assign io_oeb[21] = 1'b1;
+  assign io_oeb[22] = 1'b1;
+  assign io_oeb[23] = 1'b0;
+  assign io_oeb[24] = 1'b0;
+  clkmux2 tmux (
+      .clka  (clk       )
+    , .clkb  (io_in [21])
+    , .select(io_in [22])
+    , .gclk  (io_out[23])
+  );
+  
+  clkgate tgate (
+      .clk   (clk       )
+    , .gate  (io_in [22])
+    , .gclk  (io_out[24])
+  );
+  
+  assign io_oeb[28:25] = 1'b1;
+  assign io_oeb[29] = 1'b0;
+  assign io_oeb[30] = 1'b0;
+  assign io_oeb[31] = 1'b0;
+  WavePWM dsynth ( 
+      .clk     (clk      )
+    , .rst     (rst      )
+    
+    , .enable  (enable)
+    , .divSel  (io_in[28:25])
+    
+    , .qcos    (io_out[31])
+    , .qsin    (io_out[30])
+    , .qcomplex(io_out[29])
+  );
+  
+  assign io_oeb[0]  = 1'b1;
+  assign io_oeb[1]  = 1'b1;
+  assign io_oeb[2]  = 1'b1;
+  assign io_oeb[3]  = 1'b1;
+  assign io_oeb[4]  = 1'b1;
+  assign io_out[32] = conf[ 0];
+  assign io_oeb[32] = conf[ 7];
+  assign io_out[33] = conf[ 8];
+  assign io_oeb[33] = conf[15];
+  assign io_out[34] = conf[16];
+  assign io_oeb[34] = conf[23];
+
+endmodule
+
+`default_nettype wire
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 9327f6b..146877d 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -31,22 +31,22 @@
 
 module user_project_wrapper #(
     parameter BITS = 32
-) (
+)(
 `ifdef USE_POWER_PINS
     inout vdd,		// User area 5.0V supply
     inout vss,		// User area ground
 `endif
-    
+
     // Wishbone Slave ports (WB MI A)
-    input         wb_clk_i,
-    input         wb_rst_i,
-    input         wbs_stb_i,
-    input         wbs_cyc_i,
-    input         wbs_we_i,
-    input   [3:0] wbs_sel_i,
-    input  [31:0] wbs_dat_i,
-    input  [31:0] wbs_adr_i,
-    output        wbs_ack_o,
+    input wb_clk_i,
+    input wb_rst_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
+    input wbs_we_i,
+    input [3:0] wbs_sel_i,
+    input [31:0] wbs_dat_i,
+    input [31:0] wbs_adr_i,
+    output wbs_ack_o,
     output [31:0] wbs_dat_o,
 
     // Logic Analyzer Signals
@@ -65,137 +65,47 @@
     // User maskable interrupt signals
     output [2:0] user_irq
 );
-  
-  WishboneSlave #(
-      .BASE_ADDRESS(32'h3000_0010)
-    , .CNTR_ADDRESS(32'h3000_0020)
-  ) wishSlave (
-      .wb_clk_i  (wb_clk_i)
-    , .wb_rst_i  (wb_rst_i)
-    , .wb_stb_i  (wbs_stb_i)
-    , .wb_cyc_i  (wbs_cyc_i)
-    , .wb_we_i   (wbs_we_i)
-    , .wb_sel_i  (wbs_sel_i)
-    , .wb_adr_i  (wbs_adr_i)
-    , .wb_dat_i  (wbs_dat_i)
-    , .wb_ack_o  (wbs_ack_o)
-    , .wb_stall_o()
-    , .wb_dat_o  (wbs_dat_o)
-    
-    //Signals out of slave to design
-    , .conf_in   (conf)
-    , .conf_out  (confo)
-    , .conf_udp  (confi)
-  );
-  
-  assign io_oeb[37]  = 1'b1;
-  wire clk = io_in[37];
-  assign io_oeb[36]  = 1'b1;
-  wire rst = io_in[36];
-  assign io_oeb[35]  = 1'b1;
-  wire den = io_in[35];
-  
-  wire confi;
-  reg [31:0] conf;
-  always @ (posedge clk or negedge rst)
-    if( rst == 1'b0 )
-      conf = 32'hffffffff;
-    else if( confi )
-      conf = confo;
-    else
-      conf = conf;
-  
-  assign io_oeb[5]  = 1'b1;
-  assign io_oeb[6]  = 1'b1;
-  assign io_oeb[7]  = 1'b0;
-  assign io_oeb[8]  = 1'b0;
-  assign io_oeb[9]  = 1'b0;
-  assign io_oeb[10] = 1'b0;
-  //Analog  2 pins : 2 in
-  //Digital 5 pins : 1 in, 4 out
-  DIGOTA duuta (
-      .INpb  (io_in    [5]) //Analog io_in[7]
-    , .INmb  (io_in    [6]) //Analog io_in[8]
-    , .oe    (den         ) //Digital
-    
-    , .opmos (io_out   [7]) //Digital
-    , .onmos (io_out   [8]) //Digital
-    , .cmpmos(io_out   [9]) //Digital
-    , .cmnmos(io_out   [10]) //Digital
-  );
-  
-  assign io_oeb[11] = 1'b1;
-  assign io_oeb[12] = 1'b1;
-  assign io_oeb[13] = 1'b1;
-  assign io_oeb[14] = 1'b1;
-  assign io_oeb[15] = 1'b0;
-  assign io_oeb[16] = 1'b0;
-  assign io_oeb[17] = 1'b0;
-  assign io_oeb[18] = 1'b0;
-  assign io_oeb[19] = 1'b0;
-  assign io_oeb[20] = 1'b0;
-  //Analog  2 pins : 2 in
-  //Digital 9 pins : 3 in, 6 out
-  DiffDIGOTA duutb ( 
-    .INpb    (io_in    [11]) //Analog io_in[11]
-  , .INmb    (io_in    [12]) //Analog io_in[12]
-  , .OUTp    (io_in    [13]) //Digital
-  , .OUTm    (io_in    [14]) //Digital
-  , .oe      (enable       ) //Digital
-  
-  , .ompmos  (io_out   [15]) //Digital
-  , .omnmos  (io_out   [16]) //Digital
-  , .oppmos  (io_out   [17]) //Digital
-  , .opnmos  (io_out   [18]) //Digital
-  , .cmpmos  (io_out   [19]) //Digital
-  , .cmnmos  (io_out   [20]) //Digital
-  );
-  
-  assign io_oeb[21] = 1'b1;
-  assign io_oeb[22] = 1'b1;
-  assign io_oeb[23] = 1'b0;
-  assign io_oeb[24] = 1'b0;
-  clkmux2 tmux (
-      .clka  (clk       )
-    , .clkb  (io_in [21])
-    , .select(io_in [22])
-    , .gclk  (io_out[23])
-  );
-  
-  clkgate tgate (
-      .clk   (clk       )
-    , .gate  (io_in [22])
-    , .gclk  (io_out[24])
-  );
-  
-  assign io_oeb[28:25] = 1'b1;
-  assign io_oeb[29] = 1'b0;
-  assign io_oeb[30] = 1'b0;
-  assign io_oeb[31] = 1'b0;
-  WavePWM dsynth ( 
-      .clk     (clk      )
-    , .rst     (rst      )
-    
-    , .enable  (enable)
-    , .divSel  (io_in[28:25])
-    
-    , .qcos    (io_out[31])
-    , .qsin    (io_out[30])
-    , .qcomplex(io_out[29])
-  );
-  
-  assign io_oeb[0]  = 1'b1;
-  assign io_oeb[1]  = 1'b1;
-  assign io_oeb[2]  = 1'b1;
-  assign io_oeb[3]  = 1'b1;
-  assign io_oeb[4]  = 1'b1;
-  assign io_out[32] = conf[ 0];
-  assign io_oeb[32] = conf[ 7];
-  assign io_out[33] = conf[ 8];
-  assign io_oeb[33] = conf[15];
-  assign io_out[34] = conf[16];
-  assign io_oeb[34] = conf[23];
-  
+
+/*--------------------------------------*/
+/* User project is instantiated  here   */
+/*--------------------------------------*/
+
+user_proj_example mprj (
+`ifdef USE_POWER_PINS
+	.vdd(vdd),	// User area 1 1.8V power
+	.vss(vss),	// User area 1 digital ground
+`endif
+
+    .wb_clk_i(wb_clk_i),
+    .wb_rst_i(wb_rst_i),
+
+    // MGMT SoC Wishbone Slave
+
+    .wbs_cyc_i(wbs_cyc_i),
+    .wbs_stb_i(wbs_stb_i),
+    .wbs_we_i(wbs_we_i),
+    .wbs_sel_i(wbs_sel_i),
+    .wbs_adr_i(wbs_adr_i),
+    .wbs_dat_i(wbs_dat_i),
+    .wbs_ack_o(wbs_ack_o),
+    .wbs_dat_o(wbs_dat_o),
+
+    // Logic Analyzer
+
+    .la_data_in(la_data_in),
+    .la_data_out(la_data_out),
+    .la_oenb (la_oenb),
+
+    // IO Pads
+
+    .io_in (io_in),
+    .io_out(io_out),
+    .io_oeb(io_oeb),
+
+    // IRQ
+    .irq(user_irq)
+);
+
 endmodule	// user_project_wrapper
 
 `default_nettype wire