commit	0f440ab6f2931b5c09defb903a689f39bf778e61	[log] [tgz]
author	Ryan Price <91754608+RyanMPrice@users.noreply.github.com>	Mon Dec 05 09:52:54 2022 -0700
committer	Ryan Price <91754608+RyanMPrice@users.noreply.github.com>	Mon Dec 05 09:52:54 2022 -0700
tree	5f1c6ef2f0ce84c44e45226afc4750ac2fefdc86
parent	63d79277c1045608ed00e11dce353b92e4ebb4b6 [diff]

Final before Tape

.github/workflows/user_project_ci.yml[diff]
.gitignore[diff]
Makefile[diff]
def/user_proj_example.def[Deleted - diff]
def/user_project_wrapper.def[Deleted - diff]
docs/source/index.rst[diff]
docs/source/quickstart.rst[Deleted - diff]
gds/user_proj_example.gds[Deleted - diff]
gds/user_project_wrapper.gds[Deleted - diff]
lef/user_proj_example.lef[Deleted - diff]
lef/user_project_wrapper.lef[Deleted - diff]
mag/user_proj_example.mag[Deleted - diff]
mag/user_project_wrapper.mag[Deleted - diff]
maglef/user_proj_example.mag[Deleted - diff]
maglef/user_project_wrapper.mag[Deleted - diff]
openlane/Makefile[diff]
openlane/user_BinMult/config.tcl[Added - diff]
openlane/user_BinMult/pin_order.cfg[Added - diff]
openlane/user_DiffDigota/config.tcl[Added - diff]
openlane/user_DiffDigota/pin_order.cfg[Added - diff]
openlane/user_Digota/config.tcl[Added - diff]
openlane/user_Digota/pin_order.cfg[Added - diff]
openlane/user_WaveTbl/config.tcl[Added - diff]
openlane/user_WaveTbl/pin_order.cfg[Added - diff]
openlane/user_clkgate/config.tcl[Added - diff]
openlane/user_clkgate/pin_order.cfg[Added - diff]
openlane/user_clkmux2/config.tcl[Added - diff]
openlane/user_clkmux2/pin_order.cfg[Added - diff]
openlane/user_proj_example/config.json[Deleted - diff]
openlane/user_proj_example/pin_order.cfg[Deleted - diff]
openlane/user_project_wrapper/config.json[Deleted - diff]
openlane/user_project_wrapper/config.tcl[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl[diff]
openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl[diff]
openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper_gf180mcu.def[diff]
openlane/user_project_wrapper/macro.cfg[Deleted - diff]
signoff/user_proj_example/OPENLANE_VERSION[Deleted - diff]
signoff/user_proj_example/PDK_SOURCES[Deleted - diff]
signoff/user_project_wrapper/OPENLANE_VERSION[Deleted - diff]
signoff/user_project_wrapper/PDK_SOURCES[Deleted - diff]
spi/lvs/user_proj_example.spice[Deleted - diff]
spi/lvs/user_project_wrapper.spice[Deleted - diff]
verilog/dv/Makefile[Deleted - diff]
verilog/dv/README.md[Deleted - diff]
verilog/dv/io_ports/Makefile[Deleted - diff]
verilog/dv/io_ports/io_ports.c[Deleted - diff]
verilog/dv/io_ports/io_ports_tb.v[Deleted - diff]
verilog/dv/la_test1/Makefile[Deleted - diff]
verilog/dv/la_test1/la_test1.c[Deleted - diff]
verilog/dv/la_test1/la_test1_tb.v[Deleted - diff]
verilog/dv/la_test2/Makefile[Deleted - diff]
verilog/dv/la_test2/la_test2.c[Deleted - diff]
verilog/dv/la_test2/la_test2_tb.v[Deleted - diff]
verilog/dv/local-install.md[Deleted - diff]
verilog/dv/mprj_stimulus/Makefile[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Deleted - diff]
verilog/dv/wb_port/Makefile[Deleted - diff]
verilog/dv/wb_port/wb_port.c[Deleted - diff]
verilog/dv/wb_port/wb_port_tb.v[Deleted - diff]
verilog/gl/user_proj_example.v[Deleted - diff]
verilog/gl/user_project_wrapper.v[Deleted - diff]
verilog/rtl/BinMult/BinMultiplier.v[Added - diff]
verilog/rtl/Clocks/clkgate.v[Added - diff]
verilog/rtl/Clocks/clkmux2.v[Added - diff]
verilog/rtl/DIGOTA/DIGOTA.v[Added - diff]
verilog/rtl/DIGOTA/DiffDIGOTA.v[Added - diff]
verilog/rtl/Minx16/Alu.v[Deleted - diff]
verilog/rtl/Minx16/Biu16.v[Deleted - diff]
verilog/rtl/Minx16/Controller.v[Deleted - diff]
verilog/rtl/Minx16/FlagRegister.v[Deleted - diff]
verilog/rtl/Minx16/Minx16Cpu.v[Deleted - diff]
verilog/rtl/Minx16/Minx16Top.v[Deleted - diff]
verilog/rtl/Minx16/MinxFoldedBus1616.v[Deleted - diff]
verilog/rtl/Minx16/ParametricRegister.v[Deleted - diff]
verilog/rtl/Minx16/ProgramCounter.v[Deleted - diff]
verilog/rtl/Minx16/RegFile.v[Deleted - diff]
verilog/rtl/Minx16/StackPointer.v[Deleted - diff]
verilog/rtl/Minx16/scb.v[Deleted - diff]
verilog/rtl/Minx16/trapAddr.v[Deleted - diff]
verilog/rtl/WaveTbl/WavePWM.v[Added - diff]
verilog/rtl/WaveTbl/WaveTblCosSin.v[Added - diff]
verilog/rtl/WaveTbl/WaveTblSig.v[Added - diff]
verilog/rtl/Wishbone/WishboneSlave.v[Added - diff]
verilog/rtl/uprj_netlists.v[diff]
verilog/rtl/user_defines.v[diff]
verilog/rtl/user_proj_example.v[Deleted - diff]
verilog/rtl/user_project_wrapper.v[diff]
verilog/rtl/yosysStdCell/gf180mcu_fd_ip_sram__sram128x8m8wm1.v[Added - diff]
verilog/rtl/yosysStdCell/gf180mcu_fd_ip_sram__sram512x8m8wm1.v[Renamed from verilog/rtl/gf180mcu_fd_ip_sram/gf180mcu_fd_ip_sram__sram512x8m8wm1.v - diff]
verilog/rtl/yosysStdCell/latch_map.v[Added - diff]

91 files changed

tree: 5f1c6ef2f0ce84c44e45226afc4750ac2fefdc86

README.md

Caravel User Project

:exclamation: Important Note

Refer to README for a quickstart of how to use caravel_user_project Refer to README for this sample project documentation.

:exclamation: Important MAKE!

This design uses design rules for the gf180mcuC PDK.

This project implements a 16 bit RISC themed processor for educational purposes.

Since the number of IO pins are limited the Address/Databus are merged into a single external bus.

More documentation to come in the following days!