sdc/BinMultiplier.sdc

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# Created by write_sdc
# Mon Dec  5 17:18:22 2022
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current_design BinMultiplier
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# Timing Constraints
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create_clock -name clk -period 50.0000 [get_ports {clk}]
set_clock_transition 0.1500 [get_clocks {clk}]
set_clock_uncertainty 0.2500 clk
set_propagated_clock [get_clocks {clk}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dba[0]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dba[10]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dba[11]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dba[12]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dba[13]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dba[14]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dba[15]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dba[1]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dba[2]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dba[3]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dba[4]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dba[5]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dba[6]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dba[7]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dba[8]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dba[9]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbb[0]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbb[10]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbb[11]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbb[12]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbb[13]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbb[14]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbb[15]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbb[1]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbb[2]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbb[3]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbb[4]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbb[5]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbb[6]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbb[7]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbb[8]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dbb[9]}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {enable}]
set_input_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rst}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[0]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[10]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[11]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[12]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[13]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[14]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[15]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[16]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[17]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[18]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[19]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[1]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[20]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[21]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[22]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[23]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[24]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[25]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[26]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[27]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[28]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[29]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[2]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[30]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[31]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[3]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[4]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[5]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[6]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[7]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[8]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {Y[9]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {done}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yA[0]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yA[10]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yA[11]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yA[12]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yA[13]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yA[14]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yA[15]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yA[1]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yA[2]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yA[3]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yA[4]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yA[5]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yA[6]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yA[7]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yA[8]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yA[9]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yB[0]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yB[10]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yB[11]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yB[12]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yB[13]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yB[14]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yB[15]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yB[1]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yB[2]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yB[3]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yB[4]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yB[5]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yB[6]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yB[7]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yB[8]}]
set_output_delay 10.0000 -clock [get_clocks {clk}] -add_delay [get_ports {yB[9]}]
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# Environment
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set_load -pin_load 0.0729 [get_ports {done}]
set_load -pin_load 0.0729 [get_ports {Y[31]}]
set_load -pin_load 0.0729 [get_ports {Y[30]}]
set_load -pin_load 0.0729 [get_ports {Y[29]}]
set_load -pin_load 0.0729 [get_ports {Y[28]}]
set_load -pin_load 0.0729 [get_ports {Y[27]}]
set_load -pin_load 0.0729 [get_ports {Y[26]}]
set_load -pin_load 0.0729 [get_ports {Y[25]}]
set_load -pin_load 0.0729 [get_ports {Y[24]}]
set_load -pin_load 0.0729 [get_ports {Y[23]}]
set_load -pin_load 0.0729 [get_ports {Y[22]}]
set_load -pin_load 0.0729 [get_ports {Y[21]}]
set_load -pin_load 0.0729 [get_ports {Y[20]}]
set_load -pin_load 0.0729 [get_ports {Y[19]}]
set_load -pin_load 0.0729 [get_ports {Y[18]}]
set_load -pin_load 0.0729 [get_ports {Y[17]}]
set_load -pin_load 0.0729 [get_ports {Y[16]}]
set_load -pin_load 0.0729 [get_ports {Y[15]}]
set_load -pin_load 0.0729 [get_ports {Y[14]}]
set_load -pin_load 0.0729 [get_ports {Y[13]}]
set_load -pin_load 0.0729 [get_ports {Y[12]}]
set_load -pin_load 0.0729 [get_ports {Y[11]}]
set_load -pin_load 0.0729 [get_ports {Y[10]}]
set_load -pin_load 0.0729 [get_ports {Y[9]}]
set_load -pin_load 0.0729 [get_ports {Y[8]}]
set_load -pin_load 0.0729 [get_ports {Y[7]}]
set_load -pin_load 0.0729 [get_ports {Y[6]}]
set_load -pin_load 0.0729 [get_ports {Y[5]}]
set_load -pin_load 0.0729 [get_ports {Y[4]}]
set_load -pin_load 0.0729 [get_ports {Y[3]}]
set_load -pin_load 0.0729 [get_ports {Y[2]}]
set_load -pin_load 0.0729 [get_ports {Y[1]}]
set_load -pin_load 0.0729 [get_ports {Y[0]}]
set_load -pin_load 0.0729 [get_ports {yA[15]}]
set_load -pin_load 0.0729 [get_ports {yA[14]}]
set_load -pin_load 0.0729 [get_ports {yA[13]}]
set_load -pin_load 0.0729 [get_ports {yA[12]}]
set_load -pin_load 0.0729 [get_ports {yA[11]}]
set_load -pin_load 0.0729 [get_ports {yA[10]}]
set_load -pin_load 0.0729 [get_ports {yA[9]}]
set_load -pin_load 0.0729 [get_ports {yA[8]}]
set_load -pin_load 0.0729 [get_ports {yA[7]}]
set_load -pin_load 0.0729 [get_ports {yA[6]}]
set_load -pin_load 0.0729 [get_ports {yA[5]}]
set_load -pin_load 0.0729 [get_ports {yA[4]}]
set_load -pin_load 0.0729 [get_ports {yA[3]}]
set_load -pin_load 0.0729 [get_ports {yA[2]}]
set_load -pin_load 0.0729 [get_ports {yA[1]}]
set_load -pin_load 0.0729 [get_ports {yA[0]}]
set_load -pin_load 0.0729 [get_ports {yB[15]}]
set_load -pin_load 0.0729 [get_ports {yB[14]}]
set_load -pin_load 0.0729 [get_ports {yB[13]}]
set_load -pin_load 0.0729 [get_ports {yB[12]}]
set_load -pin_load 0.0729 [get_ports {yB[11]}]
set_load -pin_load 0.0729 [get_ports {yB[10]}]
set_load -pin_load 0.0729 [get_ports {yB[9]}]
set_load -pin_load 0.0729 [get_ports {yB[8]}]
set_load -pin_load 0.0729 [get_ports {yB[7]}]
set_load -pin_load 0.0729 [get_ports {yB[6]}]
set_load -pin_load 0.0729 [get_ports {yB[5]}]
set_load -pin_load 0.0729 [get_ports {yB[4]}]
set_load -pin_load 0.0729 [get_ports {yB[3]}]
set_load -pin_load 0.0729 [get_ports {yB[2]}]
set_load -pin_load 0.0729 [get_ports {yB[1]}]
set_load -pin_load 0.0729 [get_ports {yB[0]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_4 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {enable}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dba[15]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dba[14]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dba[13]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dba[12]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dba[11]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dba[10]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dba[9]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dba[8]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dba[7]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dba[6]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dba[5]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dba[4]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dba[3]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dba[2]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dba[1]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dba[0]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbb[15]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbb[14]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbb[13]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbb[12]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbb[11]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbb[10]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbb[9]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbb[8]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbb[7]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbb[6]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbb[5]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbb[4]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbb[3]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbb[2]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbb[1]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbb[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
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# Design Rules
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set_max_fanout 8.0000 [current_design]