verilog: remove backticks

verilog/rtl/tiny_user_project.v

diff --git a/verilog/rtl/tiny_user_project.v b/verilog/rtl/tiny_user_project.v
index 64e032b..e883560 100644
--- a/verilog/rtl/tiny_user_project.v
+++ b/verilog/rtl/tiny_user_project.v
@@ -20,7 +20,7 @@
   output [`MPRJ_IO_PADS-1:0] io_oeb
 );
 
-// pass input and output pins defined in  user_defines.v`
+// pass input and output pins defined in user_defines.v
 user_module module (
     .io_in (io_in[19:12]),
     .io_out(io_out[27:20])