harden project [skip ci]
diff --git a/gds/tiny_user_project.gds b/gds/tiny_user_project.gds
index b23676a..3c2255f 100644
--- a/gds/tiny_user_project.gds
+++ b/gds/tiny_user_project.gds
Binary files differ
diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds
index 0d8a783..0763f29 100644
--- a/gds/user_project_wrapper.gds
+++ b/gds/user_project_wrapper.gds
Binary files differ
diff --git a/mag/tiny_user_project.mag b/mag/tiny_user_project.mag
index 16a0874..93c44a6 100644
--- a/mag/tiny_user_project.mag
+++ b/mag/tiny_user_project.mag
@@ -1,7 +1,7 @@
magic
tech gf180mcuC
magscale 1 10
-timestamp 1669063275
+timestamp 1669307669
<< metal1 >>
rect 32274 46398 32286 46450
rect 32338 46447 32350 46450
diff --git a/mag/user_project_wrapper.mag b/mag/user_project_wrapper.mag
index 1132cba..cc4f792 100644
--- a/mag/user_project_wrapper.mag
+++ b/mag/user_project_wrapper.mag
@@ -1,7 +1,7 @@
magic
tech gf180mcuC
magscale 1 5
-timestamp 1669063331
+timestamp 1669307745
<< metal2 >>
rect 4900 299796 5012 300480
rect 4900 299760 5026 299796
diff --git a/maglef/tiny_user_project.mag b/maglef/tiny_user_project.mag
index cd05389..7c74382 100644
--- a/maglef/tiny_user_project.mag
+++ b/maglef/tiny_user_project.mag
@@ -1,7 +1,7 @@
magic
tech gf180mcuC
magscale 1 5
-timestamp 1669063276
+timestamp 1669307670
<< obsm1 >>
rect 672 855 24304 23225
<< metal2 >>
@@ -562,7 +562,7 @@
string LEFclass BLOCK
string LEFview TRUE
string GDS_END 318490
-string GDS_FILE /home/runner/work/tiny_user_project/tiny_user_project/openlane/tiny_user_project/runs/22_11_21_20_40/results/signoff/tiny_user_project.magic.gds
+string GDS_FILE /home/runner/work/tiny_user_project/tiny_user_project/openlane/tiny_user_project/runs/22_11_24_16_33/results/signoff/tiny_user_project.magic.gds
string GDS_START 48106
<< end >>
diff --git a/maglef/user_project_wrapper.mag b/maglef/user_project_wrapper.mag
index 78961d4..2b901e1 100644
--- a/maglef/user_project_wrapper.mag
+++ b/maglef/user_project_wrapper.mag
@@ -1,7 +1,7 @@
magic
tech gf180mcuC
magscale 1 5
-timestamp 1669063334
+timestamp 1669307750
<< obsm1 >>
rect 69422 69605 93054 91975
<< metal2 >>
@@ -3099,7 +3099,7 @@
string LEFclass BLOCK
string LEFview TRUE
string GDS_END 3465908
-string GDS_FILE /home/runner/work/tiny_user_project/tiny_user_project/openlane/user_project_wrapper/runs/22_11_21_20_41/results/signoff/user_project_wrapper.magic.gds
+string GDS_FILE /home/runner/work/tiny_user_project/tiny_user_project/openlane/user_project_wrapper/runs/22_11_24_16_34/results/signoff/user_project_wrapper.magic.gds
string GDS_START 318544
<< end >>
diff --git a/sdc/tiny_user_project.sdc b/sdc/tiny_user_project.sdc
index 9481866..c014850 100644
--- a/sdc/tiny_user_project.sdc
+++ b/sdc/tiny_user_project.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Mon Nov 21 20:41:03 2022
+# Thu Nov 24 16:34:12 2022
###############################################################################
current_design tiny_user_project
###############################################################################
diff --git a/sdc/user_project_wrapper.sdc b/sdc/user_project_wrapper.sdc
index 8d2e1dd..213da1d 100644
--- a/sdc/user_project_wrapper.sdc
+++ b/sdc/user_project_wrapper.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Mon Nov 21 20:41:41 2022
+# Thu Nov 24 16:35:05 2022
###############################################################################
current_design user_project_wrapper
###############################################################################
diff --git a/sdf/multicorner/nom/user_project_wrapper.ff.sdf b/sdf/multicorner/nom/user_project_wrapper.ff.sdf
index 0b79f2a..3175435 100644
--- a/sdf/multicorner/nom/user_project_wrapper.ff.sdf
+++ b/sdf/multicorner/nom/user_project_wrapper.ff.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "user_project_wrapper")
- (DATE "Mon Nov 21 20:42:08 2022")
+ (DATE "Thu Nov 24 16:35:41 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.2")
diff --git a/sdf/multicorner/nom/user_project_wrapper.ss.sdf b/sdf/multicorner/nom/user_project_wrapper.ss.sdf
index 94690ee..3f0335d 100644
--- a/sdf/multicorner/nom/user_project_wrapper.ss.sdf
+++ b/sdf/multicorner/nom/user_project_wrapper.ss.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "user_project_wrapper")
- (DATE "Mon Nov 21 20:42:08 2022")
+ (DATE "Thu Nov 24 16:35:41 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.2")
diff --git a/sdf/multicorner/nom/user_project_wrapper.tt.sdf b/sdf/multicorner/nom/user_project_wrapper.tt.sdf
index 2beb93d..4b55885 100644
--- a/sdf/multicorner/nom/user_project_wrapper.tt.sdf
+++ b/sdf/multicorner/nom/user_project_wrapper.tt.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "user_project_wrapper")
- (DATE "Mon Nov 21 20:42:08 2022")
+ (DATE "Thu Nov 24 16:35:41 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.2")
diff --git a/sdf/tiny_user_project.sdf b/sdf/tiny_user_project.sdf
index 0ead5ca..2cb3daa 100644
--- a/sdf/tiny_user_project.sdf
+++ b/sdf/tiny_user_project.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "tiny_user_project")
- (DATE "Mon Nov 21 20:41:15 2022")
+ (DATE "Thu Nov 24 16:34:29 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.2")
diff --git a/sdf/user_project_wrapper.sdf b/sdf/user_project_wrapper.sdf
index 430a143..84a9f13 100644
--- a/sdf/user_project_wrapper.sdf
+++ b/sdf/user_project_wrapper.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "user_project_wrapper")
- (DATE "Mon Nov 21 20:42:10 2022")
+ (DATE "Thu Nov 24 16:35:44 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.2")
diff --git a/signoff/tiny_user_project/metrics.csv b/signoff/tiny_user_project/metrics.csv
index 296e6aa..ff8e1bc 100644
--- a/signoff/tiny_user_project/metrics.csv
+++ b/signoff/tiny_user_project/metrics.csv
@@ -1,2 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
-/home/runner/work/tiny_user_project/tiny_user_project/openlane/tiny_user_project,tiny_user_project,22_11_21_20_40,flow completed,0h1m11s0ms,0h0m56s0ms,608.0,0.25,304.0,1.35,451.69,76,0,0,0,0,0,0,0,-1,0,-1,-1,984,135,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1869935.0,0.0,0.62,0.49,0.0,-1,0.37,26,151,26,151,0,0,0,0,0,0,0,0,0,0,0,0,-1,-1,-1,110,313,0,423,50950.592,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,10.0,100.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0.3,gf180mcu_fd_sc_mcu7t5v0,4
+/home/runner/work/tiny_user_project/tiny_user_project/openlane/tiny_user_project,tiny_user_project,22_11_24_16_33,flow completed,0h1m43s0ms,0h1m22s0ms,608.0,0.25,304.0,1.35,437.29,76,0,0,0,0,0,0,0,-1,0,-1,-1,984,135,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1869935.0,0.0,0.62,0.49,0.0,-1,0.37,26,151,26,151,0,0,0,0,0,0,0,0,0,0,0,0,-1,-1,-1,110,313,0,423,50950.592,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,10.0,100.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0.3,gf180mcu_fd_sc_mcu7t5v0,4
diff --git a/signoff/user_project_wrapper/metrics.csv b/signoff/user_project_wrapper/metrics.csv
index 577d0fc..db4790b 100644
--- a/signoff/user_project_wrapper/metrics.csv
+++ b/signoff/user_project_wrapper/metrics.csv
@@ -1,2 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
-/home/runner/work/tiny_user_project/tiny_user_project/openlane/user_project_wrapper,user_project_wrapper,22_11_21_20_41,flow completed,0h1m8s0ms,0h0m38s0ms,-2.0,-1,-1,-1,559.59,1,0,0,0,0,0,0,0,-1,0,-1,-1,295283,363,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,0.0,-1,0.0,1.37,1.64,0.04,-1,1.06,19,637,19,637,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,8862200.2112,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,10.0,100.0,10,AREA 0,10,50,1,180,180,0.55,0.3,gf180mcu_fd_sc_mcu7t5v0,0
+/home/runner/work/tiny_user_project/tiny_user_project/openlane/user_project_wrapper,user_project_wrapper,22_11_24_16_34,flow completed,0h1m31s0ms,0h0m52s0ms,-2.0,-1,-1,-1,560.5,1,0,0,0,0,0,0,0,-1,0,-1,-1,295283,363,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,0.0,-1,0.0,1.37,1.64,0.04,-1,1.06,19,637,19,637,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,8862200.2112,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,10.0,100.0,10,AREA 0,10,50,1,180,180,0.55,0.3,gf180mcu_fd_sc_mcu7t5v0,0
diff --git a/verilog/rtl/tiny_user_project.v b/verilog/rtl/tiny_user_project.v
new file mode 100644
index 0000000..f8e3149
--- /dev/null
+++ b/verilog/rtl/tiny_user_project.v
@@ -0,0 +1,20 @@
+// generated by configure.py
+`default_nettype none
+
+module tiny_user_project(
+ input [`MPRJ_IO_PADS-1:0] io_in,
+ output [`MPRJ_IO_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-1:0] io_oeb
+);
+
+// pass input and output pins defined in user_defines.v
+user_module_334445762078310996 mod (
+ io_in[19:12],
+ io_out[27:20]
+);
+// all output enabled
+assign io_oeb[27:20] = 8'b0;
+
+endmodule // tiny_user_project
+
+`default_nettype wire
\ No newline at end of file
diff --git a/verilog/rtl/user_module_334445762078310996.v b/verilog/rtl/user_module_334445762078310996.v
new file mode 100644
index 0000000..aea8267
--- /dev/null
+++ b/verilog/rtl/user_module_334445762078310996.v
@@ -0,0 +1,88 @@
+/* Automatically generated from https://wokwi.com/projects/334445762078310996 */
+
+`default_nettype none
+
+module user_module_334445762078310996(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = 1'b1;
+ wire net2 = 1'b0;
+ wire net3;
+ wire net4;
+ wire net5;
+ wire net6;
+ wire net7;
+ wire net8 = 1'b1;
+ wire net9 = 1'b0;
+ wire net10;
+ wire net11;
+ wire net12 = 1'b1;
+ wire net13 = 1'b0;
+ wire net14;
+ wire net15 = 1'b1;
+ wire net16 = 1'b0;
+ wire net17;
+ wire net18 = 1'b0;
+ wire net19 = 1'b1;
+ wire net20;
+ wire net21 = 1'b1;
+ wire net22;
+ wire net23;
+ wire net24 = 1'b0;
+ wire net25 = 1'b0;
+
+ and_cell gate1 (
+ .a (net3)
+ );
+ or_cell gate2 (
+
+ );
+ xor_cell gate3 (
+
+ );
+ nand_cell gate4 (
+ .a (net4),
+ .b (net5),
+ .out (net6)
+ );
+ not_cell gate5 (
+ .in (net7),
+ .out (net5)
+ );
+ buffer_cell gate6 (
+
+ );
+ mux_cell mux1 (
+ .a (net8),
+ .b (net9),
+ .sel (net10),
+ .out (net11)
+ );
+ dff_cell flipflop1 (
+
+ );
+ mux_cell mux2 (
+ .a (net12),
+ .b (net13),
+ .sel (net10),
+ .out (net14)
+ );
+ mux_cell mux3 (
+ .a (net15),
+ .b (net16),
+ .sel (net10),
+ .out (net17)
+ );
+ mux_cell mux4 (
+ .a (net18),
+ .b (net19),
+ .sel (net10),
+ .out (net20)
+ );
+ and_cell gate7 (
+ .a (net22),
+ .b (net23),
+ .out (net4)
+ );
+endmodule
diff --git a/verilog/rtl/wokwi_diagram.json b/verilog/rtl/wokwi_diagram.json
new file mode 100644
index 0000000..357c5bd
--- /dev/null
+++ b/verilog/rtl/wokwi_diagram.json
@@ -0,0 +1,167 @@
+{
+ "version": 1,
+ "author": "Uri Shaked",
+ "editor": "wokwi",
+ "parts": [
+ {
+ "type": "wokwi-dip-switch-8",
+ "id": "sw1",
+ "top": 31.3,
+ "left": -45.8,
+ "rotate": 90,
+ "attrs": {}
+ },
+ { "type": "wokwi-vcc", "id": "pwr1", "top": -124.04, "left": -134.4, "attrs": {} },
+ { "type": "wokwi-gnd", "id": "gnd1", "top": 67.2, "left": 681, "attrs": {} },
+ { "type": "wokwi-gate-and-2", "id": "gate1", "top": -211.2, "left": -96, "attrs": {} },
+ { "type": "wokwi-gate-or-2", "id": "gate2", "top": -276.8, "left": 148.67, "attrs": {} },
+ { "type": "wokwi-gate-xor-2", "id": "gate3", "top": -276.8, "left": 13.2, "attrs": {} },
+ { "type": "wokwi-gate-nand-2", "id": "gate4", "top": 364.8, "left": 201.6, "attrs": {} },
+ { "type": "wokwi-gate-not", "id": "gate5", "top": 393.6, "left": 96, "attrs": {} },
+ { "type": "wokwi-gate-buffer", "id": "gate6", "top": -181.2, "left": 55.2, "attrs": {} },
+ { "type": "wokwi-mux-2", "id": "mux1", "top": -67.2, "left": 86.4, "attrs": {} },
+ {
+ "type": "wokwi-flip-flop-d",
+ "id": "flipflop1",
+ "top": -323.6,
+ "left": -244.13,
+ "attrs": {}
+ },
+ {
+ "type": "wokwi-clock-generator",
+ "id": "clkgen1",
+ "top": -256.93,
+ "left": -250,
+ "attrs": {}
+ },
+ {
+ "type": "wokwi-led-bar-graph",
+ "id": "bargraph1",
+ "top": -62.4,
+ "left": 600,
+ "attrs": { "color": "lime" }
+ },
+ { "type": "wokwi-vcc", "id": "pwr2", "top": -124.04, "left": 57.6, "attrs": {} },
+ { "type": "wokwi-vcc", "id": "pwr3", "top": -268.04, "left": -28.8, "attrs": {} },
+ { "type": "wokwi-gnd", "id": "gnd2", "top": -18.71, "left": 76.2, "attrs": {} },
+ { "type": "wokwi-mux-2", "id": "mux2", "top": -9.6, "left": 172.8, "attrs": {} },
+ { "type": "wokwi-mux-2", "id": "mux3", "top": 57.6, "left": 240, "attrs": {} },
+ { "type": "wokwi-mux-2", "id": "mux4", "top": 144, "left": 326.4, "attrs": {} },
+ { "type": "wokwi-vcc", "id": "pwr4", "top": 19.96, "left": 230.4, "attrs": {} },
+ { "type": "wokwi-vcc", "id": "pwr5", "top": 165.84, "left": 317, "rotate": 180, "attrs": {} },
+ { "type": "wokwi-vcc", "id": "pwr6", "top": -37.64, "left": 163.2, "attrs": {} },
+ { "type": "wokwi-gnd", "id": "gnd3", "top": 28.8, "left": 162.6, "attrs": {} },
+ { "type": "wokwi-gnd", "id": "gnd4", "top": 96, "left": 229.8, "attrs": {} },
+ { "type": "wokwi-gnd", "id": "gnd5", "top": 101, "left": 325.2, "rotate": 180, "attrs": {} },
+ {
+ "type": "wokwi-dip-switch-8",
+ "id": "sw2",
+ "top": 342.76,
+ "left": -65.04,
+ "rotate": 90,
+ "attrs": {}
+ },
+ { "type": "wokwi-vcc", "id": "pwr7", "top": 298.36, "left": -67.2, "attrs": {} },
+ { "type": "wokwi-gate-and-2", "id": "gate7", "top": 326.4, "left": 96, "attrs": {} },
+ {
+ "type": "wokwi-resistor",
+ "id": "r1",
+ "top": -27.98,
+ "left": 9.21,
+ "rotate": 90,
+ "attrs": { "value": "1000" }
+ },
+ {
+ "type": "wokwi-gnd",
+ "id": "gnd7",
+ "top": -95.97,
+ "left": -1.54,
+ "rotate": 180,
+ "attrs": {}
+ },
+ {
+ "type": "wokwi-resistor",
+ "id": "r2",
+ "top": 278.2,
+ "left": -2.2,
+ "rotate": 90,
+ "attrs": { "value": "1000" }
+ },
+ {
+ "type": "wokwi-resistor",
+ "id": "r3",
+ "top": 278.2,
+ "left": 26.6,
+ "rotate": 90,
+ "attrs": { "value": "1000" }
+ },
+ {
+ "type": "wokwi-resistor",
+ "id": "r4",
+ "top": 278.2,
+ "left": 55.4,
+ "rotate": 90,
+ "attrs": { "value": "1000" }
+ },
+ { "type": "wokwi-gnd", "id": "gnd8", "top": 216.2, "left": 47.8, "rotate": 180, "attrs": {} }
+ ],
+ "connections": [
+ [ "mux1:OUT", "bargraph1:A1", "green", [ "v0" ] ],
+ [ "pwr1:VCC", "sw1:1a", "red", [ "v0" ] ],
+ [ "pwr2:VCC", "mux1:A", "red", [ "v0" ] ],
+ [ "mux1:B", "gnd2:GND", "green", [ "h0" ] ],
+ [ "bargraph1:C1", "bargraph1:C2", "green", [ "v0" ] ],
+ [ "bargraph1:C2", "bargraph1:C3", "green", [ "h0" ] ],
+ [ "bargraph1:C3", "bargraph1:C4", "green", [ "h0" ] ],
+ [ "bargraph1:C4", "bargraph1:C5", "green", [ "h0" ] ],
+ [ "bargraph1:C5", "bargraph1:C6", "green", [ "h0" ] ],
+ [ "bargraph1:C6", "bargraph1:C7", "green", [ "h0" ] ],
+ [ "bargraph1:C7", "bargraph1:C8", "green", [ "h0" ] ],
+ [ "bargraph1:C8", "bargraph1:C9", "green", [ "h0" ] ],
+ [ "bargraph1:C10", "bargraph1:C9", "green", [ "h0" ] ],
+ [ "bargraph1:C10", "gnd1:GND", "green", [ "h0" ] ],
+ [ "sw1:1b", "mux1:SEL", "green", [ "h0" ] ],
+ [ "pwr6:VCC", "mux2:A", "red", [ "v0" ] ],
+ [ "gnd3:GND", "mux2:B", "black", [ "v0" ] ],
+ [ "pwr4:VCC", "mux3:A", "red", [ "v0" ] ],
+ [ "gnd4:GND", "mux3:B", "black", [ "v0" ] ],
+ [ "gnd5:GND", "mux4:A", "black", [ "v0" ] ],
+ [ "pwr5:VCC", "mux4:B", "red", [ "v0" ] ],
+ [ "sw1:1b", "mux2:SEL", "green", [ "h0" ] ],
+ [ "sw1:1b", "mux3:SEL", "green", [ "h0" ] ],
+ [ "sw1:1b", "mux4:SEL", "green", [ "h0" ] ],
+ [ "mux2:OUT", "bargraph1:A2", "green", [ "v0" ] ],
+ [ "mux3:OUT", "bargraph1:A3", "green", [ "v0" ] ],
+ [ "mux4:OUT", "bargraph1:A4", "green", [ "v0" ] ],
+ [ "pwr7:VCC", "sw2:1a", "red", [ "v0" ] ],
+ [ "sw1:1a", "sw1:2a", "green", [ "h0" ] ],
+ [ "sw1:2a", "sw1:3a", "green", [ "h0" ] ],
+ [ "sw2:1a", "sw2:2a", "green", [ "h0" ] ],
+ [ "sw2:2a", "sw2:3a", "green", [ "h0" ] ],
+ [ "sw2:3a", "sw2:4a", "green", [ "h0" ] ],
+ [ "sw2:4a", "sw2:5a", "green", [ "h0" ] ],
+ [ "sw2:5a", "sw2:6a", "green", [ "h0" ] ],
+ [ "sw2:6a", "sw2:7a", "green", [ "h0" ] ],
+ [ "sw2:7a", "sw2:8a", "green", [ "h0" ] ],
+ [ "sw2:1b", "gate7:A", "green", [ "h0" ] ],
+ [ "sw2:2b", "gate7:B", "green", [ "h0" ] ],
+ [ "sw2:3b", "gate5:IN", "green", [ "h0" ] ],
+ [ "gate5:OUT", "gate4:B", "green", [ "v0" ] ],
+ [ "gate7:OUT", "gate4:A", "green", [ "v0" ] ],
+ [ "r1:2", "sw1:1b", "green", [ "h1.74", "v16.62" ] ],
+ [ "gnd7:GND", "r1:1", "black", [ "v0" ] ],
+ [ "r2:1", "gnd8:GND", "green", [ "h0" ] ],
+ [ "r4:1", "r3:1", "green", [ "h0" ] ],
+ [ "r3:1", "r2:1", "green", [ "h0" ] ],
+ [
+ "gate1:A",
+ "clkgen1:CLK",
+ "green",
+ [ "h0", "v-48", "h-28.8", "v67.2", "h-57.6", "v38.4", "h-28.8", "v-57.6", "h28.8" ]
+ ],
+ [ "r2:2", "sw2:1b", "green", [ "h-9.6", "v17.8" ] ],
+ [ "r3:2", "sw2:2b", "green", [ "h-9.6", "v27.4" ] ],
+ [ "r4:2", "sw2:3b", "green", [ "h-9.6", "v27.4" ] ],
+ [ "bargraph1:A8", "gate4:OUT", "green", [ "h-37.9", "v305.65", "h-269.3" ] ]
+ ]
+}
\ No newline at end of file
