chore: spell hardening config
we also define a blackbox model for user_project_wrapper hardening
spell hardens, but user_project_wrapper fails with LVS errors.
diff --git a/.github/workflows/user_project_ci.yml b/.github/workflows/spell_ci.yml
similarity index 99%
rename from .github/workflows/user_project_ci.yml
rename to .github/workflows/spell_ci.yml
index 0fb3ab6..910a4bf 100644
--- a/.github/workflows/user_project_ci.yml
+++ b/.github/workflows/spell_ci.yml
@@ -89,7 +89,7 @@
- name: Harden using Openlane
run: |
- make user_proj_example
+ make spell
make user_project_wrapper
- name: run precheck
diff --git a/openlane/spell/config.tcl b/openlane/spell/config.tcl
new file mode 100644
index 0000000..5155322
--- /dev/null
+++ b/openlane/spell/config.tcl
@@ -0,0 +1,58 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set ::env(PDK) "gf180mcuC"
+set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0"
+
+set ::env(DESIGN_NAME) spell
+
+set ::env(VERILOG_FILES) "
+ $::env(DESIGN_DIR)/../../verilog/rtl/verispell/src/execute.v
+ $::env(DESIGN_DIR)/../../verilog/rtl/verispell/src/mem_dff.v
+ $::env(DESIGN_DIR)/../../verilog/rtl/verispell/src/mem_io.v
+ $::env(DESIGN_DIR)/../../verilog/rtl/verispell/src/mem.v
+ $::env(DESIGN_DIR)/../../verilog/rtl/verispell/src/spell.v
+ "
+
+set ::env(DESIGN_IS_CORE) 0
+
+set ::env(CLOCK_PORT) "clock"
+set ::env(CLOCK_NET) "clock"
+set ::env(CLOCK_PERIOD) "100.0"
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 900 900"
+
+set ::env(PL_BASIC_PLACEMENT) 0
+set ::env(PL_TARGET_DENSITY) 0.45
+
+set ::env(FP_CORE_UTIL) 40
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+# Maximum layer used for routing is metal 4.
+# This is because this macro will be inserted in a top level (user_project_wrapper)
+# where the PDN is planned on metal 5. So, to avoid having shorts between routes
+# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4.
+#
+set ::env(RT_MAX_LAYER) {Metal4}
+
+# You can draw more power domains if you need to
+set ::env(VDD_NETS) [list {vdd}]
+set ::env(GND_NETS) [list {vss}]
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+# If you're going to use multiple power domains, then disable cvc run.
+set ::env(RUN_CVC) 1
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index df19160..f799504 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -34,14 +34,14 @@
## Clock configurations
set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
+set ::env(CLOCK_NET) "spell.clock"
set ::env(CLOCK_PERIOD) "10"
## Internal Macros
### Macro PDN Connections
set ::env(FP_PDN_MACRO_HOOKS) "\
- mprj vdd vss vdd vss"
+ spell vdd vss vdd vss"
### Macro Placement
set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
@@ -49,13 +49,13 @@
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $::env(DESIGN_DIR)/../../verilog/rtl/user_proj_example.v"
+ $::env(DESIGN_DIR)/../../verilog/rtl/spell_bb.v"
set ::env(EXTRA_LEFS) "\
- $::env(DESIGN_DIR)/../../lef/user_proj_example.lef"
+ $::env(DESIGN_DIR)/../../lef/spell.lef"
set ::env(EXTRA_GDS_FILES) "\
- $::env(DESIGN_DIR)/../../gds/user_proj_example.gds"
+ $::env(DESIGN_DIR)/../../gds/spell.gds"
set ::env(RT_MAX_LAYER) {Metal4}
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..908ce17 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1 @@
-mprj 1175 1690 N
+spell 600 600 N
diff --git a/verilog/rtl/spell_bb.v b/verilog/rtl/spell_bb.v
new file mode 100644
index 0000000..bba4612
--- /dev/null
+++ b/verilog/rtl/spell_bb.v
@@ -0,0 +1,48 @@
+module spell (
+`ifdef USE_POWER_PINS
+ inout vdd, // User area 1 1.8V supply
+ inout vss, // User area 1 digital ground
+`endif
+
+ input wire reset,
+ input wire clock,
+
+ // Logic anaylzer
+ input wire i_la_write,
+ input wire [6:0] i_la_addr,
+ input wire [7:0] i_la_data,
+ input wire i_la_wb_disable,
+ output wire [31:0] la_data_out,
+
+ // Wishbone interface
+ input wire i_wb_cyc, // wishbone transaction
+ input wire i_wb_stb, // strobe
+ input wire i_wb_we, // write enable
+ input wire [31:0] i_wb_addr, // address
+ input wire [31:0] i_wb_data, // incoming data
+ output wire o_wb_ack, // request is completed
+ output reg [31:0] o_wb_data, // output data
+
+ // GPIO
+ input wire [7:0] io_in,
+ output wire [7:0] io_out,
+ output wire [7:0] io_oeb, // out enable bar (low active)
+
+ // Shared RAM wishbone controller
+ output wire rambus_wb_clk_o, // clock, must run at system clock
+ output wire rambus_wb_rst_o, // reset
+ output wire rambus_wb_stb_o, // write strobe
+ output wire rambus_wb_cyc_o, // cycle
+ output wire rambus_wb_we_o, // write enable
+ output wire [ 3:0] rambus_wb_sel_o, // write word select
+ output wire [31:0] rambus_wb_dat_o, // ram data out
+ output wire [ 9:0] rambus_wb_addr_o, // 8 bit address
+ input wire rambus_wb_ack_i, // ack
+ input wire [31:0] rambus_wb_dat_i, // ram data in
+
+ // Interrupt
+ output wire interrupt
+);
+
+endmodule
+
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 146877d..2e78446 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -70,40 +70,39 @@
/* User project is instantiated here */
/*--------------------------------------*/
-user_proj_example mprj (
+spell spell(
`ifdef USE_POWER_PINS
- .vdd(vdd), // User area 1 1.8V power
+ .vdd(vdd), // User area 1 5V power
.vss(vss), // User area 1 digital ground
`endif
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
+ // Logic analyzer
+ .i_la_wb_disable(la_data_in[1]),
+ .i_la_write(la_data_in[2]),
+ .i_la_addr(la_data_in[14:8]),
+ .i_la_data(la_data_in[23:16]),
+ .la_data_out(la_data_out[31:0]),
- // MGMT SoC Wishbone Slave
+ // Wishbone slave
+ .i_wb_cyc(wbs_cyc_i),
+ .i_wb_stb(wbs_stb_i),
+ .i_wb_we(wbs_we_i),
+ .i_wb_addr(wbs_adr_i),
+ .i_wb_data(wbs_dat_i),
+ .o_wb_ack(wbs_ack_o),
+ .o_wb_data(wbs_dat_o),
- .wbs_cyc_i(wbs_cyc_i),
- .wbs_stb_i(wbs_stb_i),
- .wbs_we_i(wbs_we_i),
- .wbs_sel_i(wbs_sel_i),
- .wbs_adr_i(wbs_adr_i),
- .wbs_dat_i(wbs_dat_i),
- .wbs_ack_o(wbs_ack_o),
- .wbs_dat_o(wbs_dat_o),
+ // RAMBus ports - unused
+ .rambus_wb_ack_i (0),
+ .rambus_wb_dat_i (0),
- // Logic Analyzer
+ // IO pins
+ .io_in(io_in[15:8]),
+ .io_out(io_out[15:8]),
+ .io_oeb(io_oeb[15:8]),
- .la_data_in(la_data_in),
- .la_data_out(la_data_out),
- .la_oenb (la_oenb),
-
- // IO Pads
-
- .io_in (io_in),
- .io_out(io_out),
- .io_oeb(io_oeb),
-
- // IRQ
- .irq(user_irq)
+ // Interrupts
+ .interrupt(user_irq[0])
);
endmodule // user_project_wrapper
