commit 21761c90c0a8f10346b26e58e37ecb0c993a63a2
author jeffdi <jeffdi@efabless.com> Mon Oct 24 19:05:41 2022 -0700
committer jeffdi <jeffdi@efabless.com> Mon Oct 24 19:05:41 2022 -0700
tree 4401008849c63ca4b942e8a94c1f38ecd124391e
parent fafaea509346e5de19b317d75aa1da29f951c72f

update quickstart.rst

openlane/user_proj_example/config.json

diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
index 8f0d82d..370d74c 100644
--- a/openlane/user_proj_example/config.json
+++ b/openlane/user_proj_example/config.json
@@ -1,7 +1,7 @@
 {
     "DESIGN_NAME": "user_proj_example",
     "DESIGN_IS_CORE": 0,
-    "VERILOG_FILES": ["dir::project_root/verilog/rtl/defines.v", "dir::project_root/verilog/rtl/user_proj_example.v"],
+    "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
     "CLOCK_PERIOD": 10,
     "CLOCK_PORT": "wb_clk_i",
     "CLOCK_NET": "counter.clk",