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        "time": "Tue Nov 22 07:51:15 2022 -0800"
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      "message": "Merge pull request #206 from efabless/main\n\ngf180mcu redesign"
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      "message": "Merge pull request #1 from efabless/urpj_redesign\n\ngf180 user_project redesign"
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      "message": "First itterations that:\n- Changed config.json back to config.tcl\n- Incorprated the new changes done in caravel configuration\n- New template def file\n- Default configuration is specific for gf180mcuC\n- Fixed user_project_wrapper and example rtl verilog to be the same as\nthe on in caravel\nTODO:\n- reharden user_project_wrapper in caravel with new OpenLane as the via\ninsertion is different and will cause an issue with XOR\n- Make the repo usable for multiple technologies\n"
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        "time": "Tue Nov 15 16:35:21 2022 +0000"
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        "time": "Tue Nov 15 16:35:21 2022 +0000"
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      "message": "fix rst subheadings"
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        "time": "Tue Nov 15 18:07:26 2022 +0200"
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      "message": "feat: rename makefile tragets for running sta\n"
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        "time": "Tue Nov 15 17:16:42 2022 +0200"
      },
      "message": "feat: change default pdk to sky130A\n"
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        "time": "Tue Nov 15 14:04:25 2022 +0200"
      },
      "message": "reformatting\n"
    },
    {
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      },
      "committer": {
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        "email": "karimmhany@gmail.com",
        "time": "Tue Nov 15 11:35:15 2022 +0200"
      },
      "message": "remove components and nets section from template def\n"
    },
    {
      "commit": "a1996978920cad104541477ea15a355743bb68b5",
      "tree": "fd6649fc1dd52f2d72b9adbd25f2cad97abfae86",
      "parents": [
        "7fecf2d77ea90315b4a1d5b0fa38fa6140eddcde"
      ],
      "author": {
        "name": "Kareem Farid",
        "email": "karimmhany@gmail.com",
        "time": "Mon Nov 14 20:19:36 2022 +0200"
      },
      "committer": {
        "name": "Kareem Farid",
        "email": "karimmhany@gmail.com",
        "time": "Mon Nov 14 20:19:36 2022 +0200"
      },
      "message": "feat: add extract-parasitics target that\n\nfetches the macros and extract parasitics for them\n~ suppress makefile shell commands\n\ndiff --git a/Makefile b/Makefile\nindex 42b616a..4e2176a 100644\n--- a/Makefile\n+++ b/Makefile\n@@ -262,36 +262,50 @@ help:\n\n export CUP_ROOT\u003d$(shell pwd)\n-export TIMING_ROOT\u003d$(shell pwd)/deps/timing-scripts\n-export CURRENT_PROJECT\u003d$(CUP_ROOT)\n+export TIMING_ROOT?\u003d$(shell pwd)/deps/timing-scripts\n+export PROJECT_ROOT\u003d$(CUP_ROOT)\n timing-scripts-repo\u003dgit@github.com:efabless/timing-scripts.git\n\n $(TIMING_ROOT):\n-\tgit clone $(timing-scripts-repo) $(TIMING_ROOT)\n+\t@git clone $(timing-scripts-repo) $(TIMING_ROOT)\n\n .PHONY: setup-timing-scripts\n setup-timing-scripts: $(TIMING_ROOT)\n-\t( cd $(TIMING_ROOT) \u0026\u0026 git pull )\n+\t@( cd $(TIMING_ROOT) \u0026\u0026 git pull )\n \t#( cd $(TIMING_ROOT) \u0026\u0026 git fetch \u0026\u0026 git checkout $(MPW_TAG); )\n-\tpython3 -m venv ./venv\n-\t. ./venv/bin/activate \u0026\u0026 \\\n-\tpython3 -m pip install --upgrade pip \u0026\u0026 \\\n-\tpython3 -m pip install -r $(TIMING_ROOT)/requirements.txt \u0026\u0026 \\\n-\tdeactivate\n+\t@python3 -m venv ./venv\n+\t\t. ./venv/bin/activate \u0026\u0026 \\\n+\t\tpython3 -m pip install --upgrade pip \u0026\u0026 \\\n+\t\tpython3 -m pip install -r $(TIMING_ROOT)/requirements.txt \u0026\u0026 \\\n+\t\tdeactivate\n\n ./verilog/gl/user_project_wrapper.v:\n \t$(error you don\u0027t have $@)\n\n-./env/spef-mapping.tcl: $(setup-timing-scripts) ./verilog/gl/user_project_wrapper.v\n-\t. ./venv/bin/activate \u0026\u0026 \\\n-\tpython3 $(TIMING_ROOT)/scripts/generate_spef_mapping.py \\\n-\t\t-i ./verilog/gl/user_project_wrapper.v \\\n-\t\t-o ./env/spef-mapping.tcl \\\n-\t\t--pdk $(PDK) \\\n-\t\t--pdk-root $(PDK_ROOT) \\\n-\t\t--project-root \u0027$$::env(CUP_ROOT)\u0027 \u0026\u0026 \\\n+./env/spef-mapping.tcl: $(TIMING_ROOT) ./verilog/gl/user_project_wrapper.v\n+\t@. ./venv/bin/activate \u0026\u0026 \\\n+\t\tpython3 $(TIMING_ROOT)/scripts/generate_spef_mapping.py \\\n+\t\t\t-i ./verilog/gl/user_project_wrapper.v \\\n+\t\t\t-o ./env/spef-mapping.tcl \\\n+\t\t\t--pdk-path $(PDK_ROOT)/$(PDK) \\\n+\t\t\t--project-root \"$(CUP_ROOT)\" \u0026\u0026 \\\n+\t\tdeactivate\n+\n+.PHONY: extract-parasitics\n+extract-parasitics: $(TIMING_ROOT) ./verilog/gl/user_project_wrapper.v\n+\t@. ./venv/bin/activate \u0026\u0026 \\\n+\tpython3 $(TIMING_ROOT)/scripts/get_macros.py \\\n+\t-i ./verilog/gl/user_project_wrapper.v \\\n+\t-o ./tmp-macros-list \\\n+\t--pdk-path $(PDK_ROOT)/$(PDK) \u0026\u0026 \\\n \tdeactivate\n+\t@cat ./tmp-macros-list | cut -d \" \" -f2 \\\n+\t\t| xargs -I % bash -c \"$(MAKE) -C $(TIMING_ROOT) \\\n+\t\t\t-f $(TIMING_ROOT)/timing.mk rcx-% || echo \u0027Cannot extract %. Probably no def for this macro\u0027\"\n+\n\n .PHONY: caravel-sta\n caravel-sta: ./env/spef-mapping.tcl\n-\t$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-typ-nom\n+\t@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-nom\n+\t@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast\n+\t@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow\n"
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        "time": "Sun Nov 13 18:19:43 2022 +0200"
      },
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        "name": "Kareem Farid",
        "email": "karimmhany@gmail.com",
        "time": "Sun Nov 13 18:19:43 2022 +0200"
      },
      "message": "feat: integrate timing-scripts\n\nclone timing-scripts\nsetup venv\ngenerate_spef_mapping\nTODO: extract modules inside user_project_wrapper\n"
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        "time": "Fri Nov 11 10:36:09 2022 -0800"
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        "time": "Fri Nov 11 10:36:09 2022 -0800"
      },
      "message": "Merge pull request #182 from efabless/config_fix\n\nuser_project_wrapper fix"
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        "time": "Tue Nov 08 09:17:36 2022 -0800"
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        "email": "marwan@ciic.c.catx-ext-efabless.internal",
        "time": "Tue Nov 08 09:17:36 2022 -0800"
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      "message": "fix ci to run after hardening\n"
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        "time": "Tue Nov 08 08:38:29 2022 -0800"
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        "time": "Tue Nov 08 08:10:45 2022 -0800"
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        "time": "Tue Nov 08 07:37:45 2022 -0800"
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      "message": "fix ci to run after hardening\n"
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        "time": "Tue Nov 08 07:00:22 2022 -0800"
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      "message": "fix ci to run after hardening\n"
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        "time": "Fri Nov 04 09:32:10 2022 -0700"
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      "message": "Merge pull request #177 from proppy/docs\n\ndocs: fix intrapage link"
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        "email": "marwan@ciic.c.catx-ext-efabless.internal",
        "time": "Thu Nov 03 04:35:13 2022 -0700"
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      "message": "fix config for user_project_wrapper\n"
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        "time": "Thu Nov 03 04:01:06 2022 -0700"
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      "message": "fix ci to run after hardening\n"
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        "email": "proppy@google.com",
        "time": "Thu Nov 03 18:09:23 2022 +0900"
      },
      "message": "docs: fix intrapage link\n"
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        "time": "Fri Oct 28 10:10:18 2022 -0700"
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